dts: quark_se_c1000_ss_devboard: Add dts support

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>

boards/arc/quark_se_c1000_ss_devboard/Kconfig.board

@@ -2,3 +2,4 @@
 config BOARD_QUARK_SE_C1000_DEVBOARD_SS
 	bool "Quark SE C1000 - Sensor Sub System"
 	depends on SOC_QUARK_SE_C1000_SS
+	select HAS_DTS

boards/arc/quark_se_c1000_ss_devboard/board.cmake

@@ -1,6 +1,7 @@
 include($ENV{ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 
 set(OPENOCD_PRE_CMD "targets 1")
+set(OPENOCD_LOAD_CMD "load_image     ${PROJECT_BINARY_DIR}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}")
 
 set_property(GLOBAL APPEND PROPERTY FLASH_SCRIPT_ENV_VARS
   OPENOCD_PRE_CMD

boards/arc/quark_se_c1000_ss_devboard/dts.fixup

@@ -0,0 +1,14 @@
+#define CONFIG_UART_QMSI_0_BAUDRATE	INTEL_QMSI_UART_B0002000_CURRENT_SPEED
+#define CONFIG_UART_QMSI_0_NAME		INTEL_QMSI_UART_B0002000_LABEL
+
+#define CONFIG_UART_QMSI_1_BAUDRATE	INTEL_QMSI_UART_B0002400_CURRENT_SPEED
+#define CONFIG_UART_QMSI_1_NAME		INTEL_QMSI_UART_B0002400_LABEL
+
+#define SRAM_START			CONFIG_SRAM_BASE_ADDRESS
+#define SRAM_SIZE			CONFIG_SRAM_SIZE
+
+#define FLASH_START			CONFIG_FLASH_BASE_ADDRESS
+#define FLASH_SIZE      		CONFIG_FLASH_SIZE
+
+#define CONFIG_DCCM_BASE_ADDRESS       ARC_DCCM_80000000_BASE_ADDRESS
+#define CONFIG_DCCM_SIZE               ARC_DCCM_80000000_SIZE

boards/arc/quark_se_c1000_ss_devboard/quark_se_c1000_ss_devboard.dts

@@ -0,0 +1,28 @@
+/dts-v1/;
+
+#define DT_FLASH_SIZE		__SIZE_K(152)
+#define DT_SRAM_SIZE		__SIZE_K(24)
+#define DT_DCCM_SIZE		__SIZE_K(8)
+
+#include "quark_se_c1000_ss.dtsi"
+
+/ {
+	model = "quark_se_c1000_ss_devboard";
+	compatible = "intel,quark_se_c1000_ss_devboard", "intel,quark_se_c1000";
+
+	aliases {
+		uart_0 = &uart0;
+		uart_1 = &uart1;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+	};
+};
+
+&uart1 {
+	status = "ok";
+	current-speed = <115200>;
+};

dts/bindings/arc/arc,dccm.yaml

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2017, synopsy
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: ARC DCCM
+id: arc,dccm
+version: 0.1
+
+description: >
+    This binding gives a base representation of the ARC DCCM
+
+properties:
+  - compatible:
+      type: string
+      category: optional
+      description: compatible strings
+      constraint: "arc,dccm"
+
+  - reg:
+      type: array
+      description: DCCM memory mapped address space
+      generation: define
+      category: required
+...

dts/bindings/arc/arc,iccm.yaml

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2017, synopsys
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: ARC ICCM
+id: arc,iccm
+version: 0.1
+
+description: >
+    This binding gives a base representation of the ARC ICCM
+
+properties:
+  - compatible:
+      type: string
+      category: optional
+      description: compatible strings
+      constraint: "arc,iccm"
+
+  - reg:
+      type: array
+      description: ICCM memory mapped address space
+      generation: define
+      category: required
+...

dts/bindings/interrupt-controller/snps,arcv2-intc.yaml

@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2017, synopsy
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: ARCV2 Interrupt Controller
+version: 0.1
+
+description: >
+    This binding describes the ARCV2 IRQ controller
+
+properties:
+  - compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "snps,arcv2-intc"
+
+  - reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+  - arm,num-irq-priority-bits:
+      category: required
+      type: int
+      description: number of bits of IRQ priorities
+      generation: define
+
+cell_string: IRQ
+
+"#cells":
+  - irq
+  - priority
+...