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arm: config settings for frdm_k64f internal clock dividers

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Internal K64 SoC clock dividers were hard-coded. They've been replaced
with config options.

Change-Id: I583307f2e3341525f4445e9ceb89d36634b12802
Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
This commit is contained in:
Jeff Blais 2016-02-11 12:06:12 -05:00 • committed by Benjamin Walsh
commit f428d511f3
2 changed files with 41 additions and 4 deletions
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32
arch/arm/soc/fsl_frdm_k64f/Kconfig
View file

@ -39,6 +39,38 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 120000000
config K64_CORE_CLOCK_DIVIDER
int
prompt "Freescale K64 core clock divider"
default 1
help
This option specifies the divide value for the K64 processor core clock
from the system clock.
config K64_BUS_CLOCK_DIVIDER
int
prompt "Freescale K64 bus clock divider"
default 2
help
This option specifies the divide value for the K64 bus clock from the
system clock.
config K64_FLEXBUS_CLOCK_DIVIDER
int
prompt "Freescale K64 FlexBus clock divider"
default 3
help
This option specifies the divide value for the K64 FlexBus clock from the
system clock.
config K64_FLASH_CLOCK_DIVIDER
int
prompt "Freescale K64 flash clock divider"
default 5
help
This option specifies the divide value for the K64 flash clock from the
system clock.
config WDOG_INIT
def_bool y
# omit prompt to signify a "hidden" option

13
arch/arm/soc/fsl_frdm_k64f/soc.c
View file

@ -301,10 +301,15 @@ static int fsl_frdm_k64f_init(struct device *arg)
* FlexBus clock = 40 MHz (PLL/OUTDIV3)
* Flash clock = 24 MHz (PLL/OUTDIV4)
*/
sim_p->clkdiv1.value = ((SIM_CLKDIV(1) << SIM_CLKDIV1_OUTDIV1_SHIFT) |
(SIM_CLKDIV(2) << SIM_CLKDIV1_OUTDIV2_SHIFT) |
(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
sim_p->clkdiv1.value = (
(SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV1_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV2_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV4_SHIFT));
/* Initialize PLL/system clock to 120 MHz */
clkInit();