diff --git a/arch/arm/soc/fsl_frdm_k64f/Kconfig b/arch/arm/soc/fsl_frdm_k64f/Kconfig
index 9e7ada45ee5..c13bdbb9f18 100644
--- a/arch/arm/soc/fsl_frdm_k64f/Kconfig
+++ b/arch/arm/soc/fsl_frdm_k64f/Kconfig
@@ -39,6 +39,38 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	int
 	default 120000000
 
+config K64_CORE_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 core clock divider"
+	default 1
+	help
+	This option specifies the divide value for the K64 processor core clock
+	from the system clock.
+
+config K64_BUS_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 bus clock divider"
+	default 2
+	help
+	This option specifies the divide value for the K64 bus clock from the
+	system clock.
+
+config K64_FLEXBUS_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 FlexBus clock divider"
+	default 3
+	help
+	This option specifies the divide value for the K64 FlexBus clock from the
+	system clock.
+
+config K64_FLASH_CLOCK_DIVIDER
+	int
+	prompt "Freescale K64 flash clock divider"
+	default 5
+	help
+	This option specifies the divide value for the K64 flash clock from the
+	system clock.
+
 config WDOG_INIT
 	def_bool y
 	# omit prompt to signify a "hidden" option
diff --git a/arch/arm/soc/fsl_frdm_k64f/soc.c b/arch/arm/soc/fsl_frdm_k64f/soc.c
index efea6c517b8..cb252d2bd90 100644
--- a/arch/arm/soc/fsl_frdm_k64f/soc.c
+++ b/arch/arm/soc/fsl_frdm_k64f/soc.c
@@ -301,10 +301,15 @@ static int fsl_frdm_k64f_init(struct device *arg)
 	 * FlexBus clock = 40 MHz (PLL/OUTDIV3)
 	 * Flash clock = 24 MHz (PLL/OUTDIV4)
 	 */
-	sim_p->clkdiv1.value = ((SIM_CLKDIV(1) << SIM_CLKDIV1_OUTDIV1_SHIFT) |
-				(SIM_CLKDIV(2) << SIM_CLKDIV1_OUTDIV2_SHIFT) |
-				(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
-				(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
+	sim_p->clkdiv1.value = (
+		(SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV1_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV2_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV3_SHIFT) |
+		(SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) <<
+			SIM_CLKDIV1_OUTDIV4_SHIFT));
 
 	/* Initialize PLL/system clock to 120 MHz */
 	clkInit();