boards: st: n6: use ic3 as xspi kernel clock
Configure and enable IC3 to 400MHz and use it as kernel clock for XSPI instances. Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
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2 changed files with 21 additions and 0 deletions
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@ -97,6 +97,12 @@
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status = "okay";
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};
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&ic3 {
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pll-src = <1>;
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ic-div = <6>;
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status = "okay";
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};
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&ic6 {
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pll-src = <3>;
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ic-div = <2>;
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@ -224,6 +230,9 @@ zephyr_udc0: &usbotg_hs1 {
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&xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
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&xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
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pinctrl-names = "default";
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clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
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<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
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<&rcc STM32_CLOCK(AHB5, 13)>;
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status = "okay";
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mx25um51245g: ospi-nor-flash@70000000 {
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@ -107,6 +107,12 @@
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status = "okay";
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};
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&ic3 {
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pll-src = <1>;
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ic-div = <6>;
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status = "okay";
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};
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&ic4 {
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pll-src = <2>;
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ic-div = <32>;
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@ -238,6 +244,9 @@ zephyr_udc0: &usbotg_hs1 {
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&xspim_p1_io12_pp12 &xspim_p1_io13_pp13 &xspim_p1_io14_pp14
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&xspim_p1_io15_pp15>;
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pinctrl-names = "default";
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clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
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<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
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<&rcc STM32_CLOCK(AHB5, 13)>;
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status = "okay";
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memc: aps256xxn_obr: memory@90000000 {
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@ -258,6 +267,9 @@ zephyr_udc0: &usbotg_hs1 {
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&xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
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&xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
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pinctrl-names = "default";
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clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
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<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
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<&rcc STM32_CLOCK(AHB5, 13)>;
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status = "okay";
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mx66uw1g45g: ospi-nor-flash@70000000 {
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