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drivers: timer: Harmonize mtime-based RISC-V timers

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This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.

Signed-off-by: Camille BAUD <mail@massdriver.space>
This commit is contained in:
Camille BAUD 2025-01-17 20:20:40 +01:00 • committed by Benjamin Cabé
commit f11f68eade
31 changed files with 151 additions and 205 deletions
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2
boards/intel/niosv_g/niosv_g.dts
View file

@ -27,7 +27,7 @@
};
&mtimer {
reg = <0x90000 0x10>;
reg = <0x90000 0x8 0x90008 0x8>;
};
&uart0 {

2
boards/intel/niosv_m/niosv_m.dts
View file

@ -27,7 +27,7 @@
};
&mtimer {
reg = <0x90000 0x10>;
reg = <0x90000 0x8 0x90008 0x8>;
};
&uart0 {

7
boards/snps/nsim/arc_v/rmx1xx.dtsi
View file

@ -37,6 +37,13 @@
interrupt-names = "soft0", "timer0";
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&cpu0_intc 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
uart0: serial@10000000{
compatible = "ns16550", "snps,dw-apb-uart";
reg = <0x10000000 0x400>;

9
drivers/timer/Kconfig.riscv_machine
View file

@ -6,13 +6,8 @@
config RISCV_MACHINE_TIMER
bool "RISCV Machine Timer"
default y
depends on DT_HAS_ANDESTECH_MACHINE_TIMER_ENABLED || \
DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
DT_HAS_SIFIVE_CLINT0_ENABLED || \
DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED || \
DT_HAS_NIOSV_MACHINE_TIMER_ENABLED
depends on DT_HAS_RISCV_MACHINE_TIMER_ENABLED || \
DT_HAS_NUCLEI_SYSTIMER_ENABLED
select TICKLESS_CAPABLE
select TIMER_HAS_64BIT_CYCLE_COUNTER
help

63
drivers/timer/riscv_machine_timer.c
View file

@ -1,4 +1,5 @@
/*
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
* Copyright (c) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
@ -13,65 +14,11 @@
#include <zephyr/spinlock.h>
#include <zephyr/irq.h>
/* andestech,machine-timer */
#if DT_HAS_COMPAT_STATUS_OKAY(andestech_machine_timer)
#define DT_DRV_COMPAT andestech_machine_timer
#define DT_DRV_COMPAT riscv_machine_timer
#define MTIME_REG DT_INST_REG_ADDR(0)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQN(0)
/* neorv32-machine-timer */
#elif DT_HAS_COMPAT_STATUS_OKAY(neorv32_machine_timer)
#define DT_DRV_COMPAT neorv32_machine_timer
#define MTIME_REG DT_INST_REG_ADDR(0)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQN(0)
/* nuclei,systimer */
#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_systimer)
#define DT_DRV_COMPAT nuclei_systimer
#define MTIME_REG DT_INST_REG_ADDR(0)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq)
/* sifive,clint0 */
#elif DT_HAS_COMPAT_STATUS_OKAY(sifive_clint0)
#define DT_DRV_COMPAT sifive_clint0
#define MTIME_REG (DT_INST_REG_ADDR(0) + 0xbff8U)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x4000U)
#define TIMER_IRQN DT_INST_IRQ_BY_IDX(0, 1, irq)
/* telink,machine-timer */
#elif DT_HAS_COMPAT_STATUS_OKAY(telink_machine_timer)
#define DT_DRV_COMPAT telink_machine_timer
#define MTIME_REG DT_INST_REG_ADDR(0)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQN(0)
/* lowrisc,machine-timer */
#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
#define DT_DRV_COMPAT lowrisc_machine_timer
#define MTIME_REG (DT_INST_REG_ADDR(0) + 0x110)
#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x118)
#define TIMER_IRQN DT_INST_IRQN(0)
/* niosv-machine-timer */
#elif DT_HAS_COMPAT_STATUS_OKAY(niosv_machine_timer)
#define DT_DRV_COMPAT niosv_machine_timer
#define MTIMECMP_REG DT_INST_REG_ADDR(0)
#define MTIME_REG (DT_INST_REG_ADDR(0) + 8)
#define TIMER_IRQN DT_INST_IRQN(0)
/* scr,machine-timer*/
#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer)
#define DT_DRV_COMPAT scr_machine_timer
#define MTIMER_HAS_DIVIDER
#define MTIMEDIV_REG (DT_INST_REG_ADDR_U64(0) + 4)
#define MTIME_REG (DT_INST_REG_ADDR_U64(0) + 8)
#define MTIMECMP_REG (DT_INST_REG_ADDR_U64(0) + 16)
#define TIMER_IRQN DT_INST_IRQN(0)
#endif
#define MTIME_REG DT_INST_REG_ADDR_BY_IDX(0, 0)
#define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
#define TIMER_IRQN DT_INST_IRQN(0)
#define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \
/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)

0
dts/bindings/timer/sifive,clint0.yaml → dts/bindings/interrupt-controller/sifive,clint0.yaml
View file

19
dts/bindings/timer/andestech,machine-timer.yaml
View file

@ -1,19 +0,0 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: |
Andes Machine Timer
The Andes machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "andestech,machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts-extended:
required: true

19
dts/bindings/timer/lowrisc,machine-timer.yaml
View file

@ -1,19 +0,0 @@
# Copyright (c) 2023 Rivos Inc.
# SPDX-License-Identifier: Apache-2.0
description: |
OpenTitan Machine Timer
The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "lowrisc,machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

19
dts/bindings/timer/neorv32-machine-timer.yaml
View file

@ -1,19 +0,0 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: |
NEORV32 Machine Timer
The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "neorv32-machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

19
dts/bindings/timer/niosv-machine-timer.yaml
View file

@ -1,19 +0,0 @@
# Copyright (C) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0
description: |
NIOSV Machine Timer
The NIOSV machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "niosv-machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

8
dts/bindings/timer/nuclei,systimer.yaml
View file

@ -9,15 +9,9 @@ description: |
compatible: "nuclei,systimer"
include: base.yaml
include: "riscv,machine-timer.yaml"
properties:
reg:
required: true
interrupts:
required: true
clk-divider:
type: int
description: |

14
dts/bindings/timer/riscv,machine-timer.yaml Normal file
View file

@ -0,0 +1,14 @@
# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0
description: RISC-V Machine Timer.
compatible: "riscv,machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts-extended:
required: true

8
dts/bindings/timer/starfive,jh7100-clint.yaml
View file

@ -1,8 +0,0 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: Starfive JH7100 RISC-V Core-Local Interruptor.
compatible: "starfive,jh7100-clint"
include: sifive,clint0.yaml

19
dts/bindings/timer/telink,machine-timer.yaml
View file

@ -1,19 +0,0 @@
# Copyright (c) 2022 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: |
Telink Machine Timer
The Telink machine timer provides RISC-V privileged mtime and mtimecmp
registers.
compatible: "telink,machine-timer"
include: base.yaml
properties:
reg:
required: true
interrupts:
required: true

4
dts/riscv/andes/andes_v5_ae350.dtsi
View file

@ -215,8 +215,8 @@
};
mtimer: timer@e6000000 {
compatible = "andestech,machine-timer";
reg = <0xe6000000 0x10>;
compatible = "riscv,machine-timer";
reg = <0xe6000000 0x8 0xe6000008 0x8>;
interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
&cpu2_intc 7 &cpu3_intc 7
&cpu4_intc 7 &cpu5_intc 7

7
dts/riscv/efinix/sapphire_soc.dtsi
View file

@ -65,6 +65,13 @@
reg = <0xf8b00000 0x10000>;
};
mtimer: timer@f8b0bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic 7>;
reg = <0xf8b0bff8 0x8 0xf8b04000 0x8>;
reg-names = "mtime", "mtimecmp";
};
timer0: timer@e0002800 {
compatible = "efinix,sapphire-timer0";
reg = <0xe0002800 0x40>;

6
dts/riscv/gd/gd32vf103.dtsi
View file

@ -41,9 +41,9 @@
ranges;
systimer: timer@d1000000 {
compatible = "nuclei,systimer";
reg = <0xd1000000 0x10000>;
interrupts = <3 0>, <7 0>;
compatible = "nuclei,systimer", "riscv,machine-timer";
reg = <0xd1000000 0x8 0xd1000008 0x8>;
interrupts-extended = <&eclic 7 0>;
clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
};

11
dts/riscv/lowrisc/opentitan_earlgrey.dtsi
View file

@ -44,12 +44,11 @@
reg = <0x10000000 0x10000>;
};
mtimer: timer@40100000 {
compatible = "lowrisc,machine-timer";
reg = <0x40100000 0x200>;
interrupts = <7 0>;
interrupt-parent = <&hlic>;
status = "disabled";
mtimer: timer@40100110 {
compatible = "riscv,machine-timer";
reg = <0x40100110 0x8 0x40100118 0x8>;
reg-names = "mtime", "mtimecmp";
interrupts-extended = <&hlic 7>;
};
aontimer: aontimer@40470000 {

7
dts/riscv/microchip/microchip-miv.dtsi
View file

@ -48,6 +48,13 @@
reg = <0x44000000 0x10000>;
};
mtimer: timer@4400bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic 7>;
reg = <0x4400bff8 0x8 0x44004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
plic: interrupt-controller@40000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;

11
dts/riscv/microchip/mpfs.dtsi
View file

@ -114,6 +114,17 @@
reg = <0x2000000 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic0 7
&hlic1 7
&hlic2 7
&hlic3 7
&hlic4 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
#interrupt-cells = <2>;

6
dts/riscv/neorv32.dtsi
View file

@ -65,9 +65,9 @@
ranges;
mtimer: timer@ffffff90 {
compatible = "neorv32-machine-timer";
reg = <0xffffff90 0x10>;
interrupts = <7>;
compatible = "riscv,machine-timer";
reg = <0xffffff90 0x8 0xffffff98 0x8>;
interrupts-extended = <&intc 7>;
};
uart0: serial@ffffffa0 {

7
dts/riscv/niosv/niosv-g.dtsi
View file

@ -44,9 +44,10 @@
};
mtimer: machine-timer@90000 {
compatible = "niosv-machine-timer";
reg = <0x90000 0x10>;
interrupts = <7>;
compatible = "riscv,machine-timer";
reg = <0x90000 0x8 0x90008 0x8>;
reg-names = "mtime", "mtimecmp";
interrupts-extended = <&intc 7>;
};
uart0: serial@90078 {

7
dts/riscv/niosv/niosv-m.dtsi
View file

@ -44,9 +44,10 @@
};
mtimer: machine-timer@90000 {
compatible = "niosv-machine-timer";
reg = <0x90000 0x10>;
interrupts = <7>;
compatible = "riscv,machine-timer";
reg = <0x90000 0x8 0x90008 0x8>;
reg-names = "mtime", "mtimecmp";
interrupts-extended = <&intc 7>;
};
uart0: serial@90078 {

14
dts/riscv/qemu/virt-riscv.dtsi
View file

@ -193,5 +193,19 @@
&hlic6 0x03 &hlic6 0x07
&hlic7 0x03 &hlic7 0x07>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic0 7
&hlic1 7
&hlic2 7
&hlic3 7
&hlic4 7
&hlic5 7
&hlic6 7
&hlic7 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
};
};

7
dts/riscv/renode_riscv32_virt.dtsi
View file

@ -50,6 +50,13 @@
reg = <0x2000000 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
plic0: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;

6
dts/riscv/sifive/riscv32-fe310.dtsi
View file

@ -65,6 +65,12 @@
interrupts-extended = <&hlic 3 &hlic 7>;
reg = <0x2000000 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
debug: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&hlic 65535>;

11
dts/riscv/sifive/riscv64-fu540.dtsi
View file

@ -182,6 +182,17 @@
reg = <0x2000000 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic0 7
&hlic1 7
&hlic2 7
&hlic3 7
&hlic4 7>;
reg = <0x200bff8 0x8 0x2004000 0x8>;
reg-names = "mtime", "mtimecmp";
};
l2lim: l2lim@8000000 {
compatible = "sifive,l2lim0";
reg = <0x8000000 0x2000000>;

12
dts/riscv/sifive/riscv64-fu740.dtsi
View file

@ -137,13 +137,23 @@
reg = <0x0 0x2000000 0x0 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&hlic0 7
&hlic1 7
&hlic2 7
&hlic3 7
&hlic4 7>;
reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
reg-names = "mtime", "mtimecmp";
};
l2lim: l2lim@8000000 {
compatible = "sifive,l2lim0";
reg = <0x0 0x8000000 0x0 0x200000>;
reg-names = "mem";
};
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;

15
dts/riscv/starfive/jh7110-visionfive-v2.dtsi
View file

@ -145,8 +145,8 @@
compatible = "starfive,jh7110", "simple-bus";
ranges;
clint: timer@2000000 {
compatible = "starfive,jh7110-clint", "sifive,clint0";
clint: clint@2000000 {
compatible = "sifive,clint0";
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
&cpu2_intc 3 &cpu2_intc 7
@ -155,6 +155,17 @@
reg = <0x0 0x2000000 0x0 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&cpu0_intc 7
&cpu1_intc 7
&cpu2_intc 7
&cpu3_intc 7
&cpu4_intc 7>;
reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
reg-names = "mtime", "mtimecmp";
};
ccache: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;

9
dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
View file

@ -115,12 +115,19 @@
};
clint: clint@2000000 {
compatible = "starfive,jh7100-clint", "sifive,clint0";
compatible = "sifive,clint0";
interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
&cpu1intctrl 3 &cpu1intctrl 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
};
mtimer: timer@200bff8 {
compatible = "riscv,machine-timer";
interrupts-extended = <&cpu0intctrl 7 &cpu1intctrl 7>;
reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
reg-names = "mtime", "mtimecmp";
};
plic: plic@c000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;

8
dts/riscv/telink/telink_b91.dtsi
View file

@ -48,10 +48,10 @@
};
mtimer: timer@e6000000 {
compatible = "telink,machine-timer";
reg = <0xe6000000 0x10000>;
interrupts = <7 0>;
interrupt-parent = <&plic0>;
compatible = "riscv,machine-timer";
reg = <0xe6000000 0x8 0xe6000008 0x8>;
reg-names = "mtime", "mtimecmp";
interrupts-extended = <&plic0 7 0>;
};
flash_mspi: flash-controller@80140100 {