This commit replaces a bunch of ifdefs and bindings with a single extensible binding, and makes all standard mtime system timers consistent. Signed-off-by: Camille BAUD <mail@massdriver.space>
287 lines
6.1 KiB
Text
287 lines
6.1 KiB
Text
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <freq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
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model = "sifive,FU540";
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clocks {
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coreclk: core-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(1000)>;
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};
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tlclk: tl-clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&coreclk>;
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clock-div = <2>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "sifive,e51", "riscv";
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device_type = "cpu";
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i-cache-line-size = <0x4000>;
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reg = <0x0>;
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riscv,isa = "rv64imac_zicsr_zifencei";
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hlic0: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@1 {
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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mmu-type = "riscv,sv39";
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i-cache-line-size = <0x8000>;
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d-cache-line-size = <0x8000>;
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reg = <0x1>;
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riscv,isa = "rv64gc";
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hlic1: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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mmu-type = "riscv,sv39";
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i-cache-line-size = <0x8000>;
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d-cache-line-size = <0x8000>;
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reg = <0x2>;
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riscv,isa = "rv64gc";
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hlic2: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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mmu-type = "riscv,sv39";
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i-cache-line-size = <0x8000>;
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d-cache-line-size = <0x8000>;
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reg = <0x3>;
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riscv,isa = "rv64gc";
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hlic3: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54", "riscv";
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device_type = "cpu";
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mmu-type = "riscv,sv39";
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i-cache-line-size = <0x8000>;
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d-cache-line-size = <0x8000>;
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reg = <0x4>;
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riscv,isa = "rv64gc";
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hlic4: interrupt-controller {
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compatible = "riscv,cpu-intc";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fu540-soc", "sifive-soc", "simple-bus";
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ranges;
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modeselect: rom@1000 {
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compatible = "sifive,modeselect0";
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reg = <0x1000 0x1000>;
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reg-names = "mem";
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};
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maskrom: rom@10000 {
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compatible = "sifive,maskrom0";
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reg = <0x10000 0x8000>;
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reg-names = "mem";
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};
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dtim: dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x1000000 0x2000>;
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reg-names = "mem";
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};
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itim0: itim0@1800000 {
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compatible = "sifive,itim0";
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reg = <0x1800000 0x2000>;
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reg-names = "mem";
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};
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itim1: itim1@1808000 {
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compatible = "sifive,itim0";
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reg = <0x1808000 0x7000>;
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reg-names = "mem";
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};
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itim2: itim2@1810000 {
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compatible = "sifive,itim0";
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reg = <0x1810000 0x7000>;
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reg-names = "mem";
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};
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itim3: itim3@1818000 {
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compatible = "sifive,itim0";
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reg = <0x1818000 0x7000>;
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reg-names = "mem";
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};
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itim4: itim4@1820000 {
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compatible = "sifive,itim0";
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reg = <0x1820000 0x7000>;
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reg-names = "mem";
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};
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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interrupts-extended = <&hlic0 3 &hlic0 7
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&hlic1 3 &hlic1 7
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&hlic2 3 &hlic2 7
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&hlic3 3 &hlic3 7
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&hlic4 3 &hlic4 7>;
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interrupt-names = "soft0", "timer0", "soft1", "timer1",
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"soft2", "timer2", "soft3", "timer3",
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"soft4", "timer4";
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reg = <0x2000000 0x10000>;
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};
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mtimer: timer@200bff8 {
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compatible = "riscv,machine-timer";
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interrupts-extended = <&hlic0 7
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&hlic1 7
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&hlic2 7
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&hlic3 7
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&hlic4 7>;
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reg = <0x200bff8 0x8 0x2004000 0x8>;
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reg-names = "mtime", "mtimecmp";
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};
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l2lim: l2lim@8000000 {
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compatible = "sifive,l2lim0";
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reg = <0x8000000 0x2000000>;
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reg-names = "mem";
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,plic-1.0.0";
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#interrupt-cells = <2>;
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#address-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&hlic0 11
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&hlic1 11 &hlic1 9
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&hlic2 11 &hlic2 9
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&hlic3 11 &hlic3 9
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&hlic4 11 &hlic4 9>;
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reg = <0x0c000000 0x04000000>;
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riscv,max-priority = <7>;
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riscv,ndev = <52>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <4 1>;
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reg = <0x10010000 0x1000>;
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reg-names = "control";
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status = "disabled";
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};
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uart1: serial@10011000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <5 1>;
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reg = <0x10011000 0x1000>;
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reg-names = "control";
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status = "disabled";
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};
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spi0: spi@10040000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <51 1>;
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reg = <0x10040000 0x1000 0x20000000 0x10000000>;
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reg-names = "control", "mem";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@10041000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <52 1>;
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reg = <0x10041000 0x1000>;
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reg-names = "control";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@10050000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <6 1>;
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reg = <0x10050000 0x1000>;
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reg-names = "control";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gpio0: gpio@10060000 {
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compatible = "sifive,gpio0";
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gpio-controller;
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ngpios = <16>;
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interrupt-parent = <&plic>;
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interrupts = <7 1>, <8 1>, <9 1>, <10 1>,
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<11 1>, <12 1>, <13 1>, <14 1>,
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<15 1>, <16 1>, <17 1>, <18 1>,
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<19 1>, <20 1>, <21 1>, <22 1>;
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reg = <0x10060000 0x1000>;
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reg-names = "control";
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status = "disabled";
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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};
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};
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