drivers: timer: Harmonize mtime-based RISC-V timers

This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.

Signed-off-by: Camille BAUD <mail@massdriver.space>

boards/intel/niosv_g/niosv_g.dts

@@ -27,7 +27,7 @@
 };
 
 &mtimer {
-	reg = <0x90000 0x10>;
+	reg = <0x90000 0x8 0x90008 0x8>;
 };
 
 &uart0 {

boards/intel/niosv_m/niosv_m.dts

@@ -27,7 +27,7 @@
 };
 
 &mtimer {
-	reg = <0x90000 0x10>;
+	reg = <0x90000 0x8 0x90008 0x8>;
 };
 
 &uart0 {

boards/snps/nsim/arc_v/rmx1xx.dtsi

@@ -37,6 +37,13 @@
 				interrupt-names = "soft0", "timer0";
 			};
 
+			mtimer: timer@200bff8 {
+				compatible = "riscv,machine-timer";
+				interrupts-extended = <&cpu0_intc 7>;
+				reg = <0x200bff8 0x8 0x2004000 0x8>;
+				reg-names = "mtime", "mtimecmp";
+			};
+
 			uart0: serial@10000000{
 				compatible = "ns16550", "snps,dw-apb-uart";
 				reg = <0x10000000 0x400>;

drivers/timer/Kconfig.riscv_machine

@@ -6,13 +6,8 @@
 config RISCV_MACHINE_TIMER
 	bool "RISCV Machine Timer"
 	default y
-	depends on DT_HAS_ANDESTECH_MACHINE_TIMER_ENABLED || \
+	depends on DT_HAS_RISCV_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
+		   DT_HAS_NUCLEI_SYSTIMER_ENABLED
-		   DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
-		   DT_HAS_SIFIVE_CLINT0_ENABLED || \
-		   DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_NIOSV_MACHINE_TIMER_ENABLED
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER
 	help

drivers/timer/riscv_machine_timer.c

@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
  * Copyright (c) 2018-2023 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -13,65 +14,11 @@
 #include <zephyr/spinlock.h>
 #include <zephyr/irq.h>
 
-/* andestech,machine-timer */
+#define DT_DRV_COMPAT riscv_machine_timer
-#if DT_HAS_COMPAT_STATUS_OKAY(andestech_machine_timer)
-#define DT_DRV_COMPAT andestech_machine_timer
 
-#define MTIME_REG	DT_INST_REG_ADDR(0)
+#define MTIME_REG    DT_INST_REG_ADDR_BY_IDX(0, 0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
+#define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
-#define TIMER_IRQN	DT_INST_IRQN(0)
+#define TIMER_IRQN   DT_INST_IRQN(0)
-/* neorv32-machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(neorv32_machine_timer)
-#define DT_DRV_COMPAT neorv32_machine_timer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* nuclei,systimer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_systimer)
-#define DT_DRV_COMPAT nuclei_systimer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQ_BY_IDX(0, 1, irq)
-/* sifive,clint0 */
-#elif DT_HAS_COMPAT_STATUS_OKAY(sifive_clint0)
-#define DT_DRV_COMPAT sifive_clint0
-
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 0xbff8U)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 0x4000U)
-#define TIMER_IRQN	DT_INST_IRQ_BY_IDX(0, 1, irq)
-/* telink,machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(telink_machine_timer)
-#define DT_DRV_COMPAT telink_machine_timer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* lowrisc,machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
-#define DT_DRV_COMPAT lowrisc_machine_timer
-
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 0x110)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 0x118)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* niosv-machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(niosv_machine_timer)
-#define DT_DRV_COMPAT niosv_machine_timer
-
-#define MTIMECMP_REG	DT_INST_REG_ADDR(0)
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* scr,machine-timer*/
-#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer)
-#define DT_DRV_COMPAT scr_machine_timer
-#define MTIMER_HAS_DIVIDER
-
-#define MTIMEDIV_REG	(DT_INST_REG_ADDR_U64(0) + 4)
-#define MTIME_REG	(DT_INST_REG_ADDR_U64(0) + 8)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR_U64(0) + 16)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-#endif
 
 #define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \
 				/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)

dts/bindings/timer/andestech,machine-timer.yaml

@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Andes Machine Timer
-
-  The Andes machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "andestech,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts-extended:
-    required: true

dts/bindings/timer/lowrisc,machine-timer.yaml

@@ -1,19 +0,0 @@
-# Copyright (c) 2023 Rivos Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  OpenTitan Machine Timer
-
-  The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "lowrisc,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true

dts/bindings/timer/neorv32-machine-timer.yaml

@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  NEORV32 Machine Timer
-
-  The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "neorv32-machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true

dts/bindings/timer/niosv-machine-timer.yaml

@@ -1,19 +0,0 @@
-# Copyright (C) 2023, Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  NIOSV Machine Timer
-
-  The NIOSV machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "niosv-machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true

dts/bindings/timer/nuclei,systimer.yaml

@@ -9,15 +9,9 @@ description: |
 
 compatible: "nuclei,systimer"
 
-include: base.yaml
+include: "riscv,machine-timer.yaml"
 
 properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
   clk-divider:
     type: int
     description: |

dts/bindings/timer/riscv,machine-timer.yaml

@@ -0,0 +1,14 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V Machine Timer.
+
+compatible: "riscv,machine-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  interrupts-extended:
+    required: true

dts/bindings/timer/starfive,jh7100-clint.yaml

@@ -1,8 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: Starfive JH7100 RISC-V Core-Local Interruptor.
-
-compatible: "starfive,jh7100-clint"
-
-include: sifive,clint0.yaml

dts/bindings/timer/telink,machine-timer.yaml

@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Telink Machine Timer
-
-  The Telink machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "telink,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true

dts/riscv/andes/andes_v5_ae350.dtsi

@@ -215,8 +215,8 @@
 		};
 
 		mtimer: timer@e6000000 {
-			compatible = "andestech,machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0xe6000000 0x10>;
+			reg = <0xe6000000 0x8 0xe6000008 0x8>;
 			interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
 					       &cpu2_intc 7 &cpu3_intc 7
 					       &cpu4_intc 7 &cpu5_intc 7

dts/riscv/efinix/sapphire_soc.dtsi

@@ -65,6 +65,13 @@
 			reg = <0xf8b00000 0x10000>;
 		};
 
+		mtimer: timer@f8b0bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0xf8b0bff8 0x8 0xf8b04000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		timer0: timer@e0002800 {
 			compatible = "efinix,sapphire-timer0";
 			reg = <0xe0002800 0x40>;

dts/riscv/gd/gd32vf103.dtsi

@@ -41,9 +41,9 @@
 		ranges;
 
 		systimer: timer@d1000000 {
-			compatible = "nuclei,systimer";
+			compatible = "nuclei,systimer", "riscv,machine-timer";
-			reg = <0xd1000000 0x10000>;
+			reg = <0xd1000000 0x8 0xd1000008 0x8>;
-			interrupts = <3 0>, <7 0>;
+			interrupts-extended = <&eclic 7 0>;
 			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
 		};
 

dts/riscv/lowrisc/opentitan_earlgrey.dtsi

@@ -44,12 +44,11 @@
 			reg = <0x10000000 0x10000>;
 		};
 
-		mtimer: timer@40100000 {
+		mtimer: timer@40100110 {
-			compatible = "lowrisc,machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0x40100000 0x200>;
+			reg = <0x40100110 0x8 0x40100118 0x8>;
-			interrupts = <7 0>;
+			reg-names = "mtime", "mtimecmp";
-			interrupt-parent = <&hlic>;
+			interrupts-extended = <&hlic 7>;
-			status = "disabled";
 		};
 
 		aontimer: aontimer@40470000 {

dts/riscv/microchip/microchip-miv.dtsi

@@ -48,6 +48,13 @@
 			reg = <0x44000000 0x10000>;
 		};
 
+		mtimer: timer@4400bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x4400bff8 0x8 0x44004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: interrupt-controller@40000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;

dts/riscv/microchip/mpfs.dtsi

@@ -114,6 +114,17 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#interrupt-cells = <2>;

dts/riscv/neorv32.dtsi

@@ -65,9 +65,9 @@
 		ranges;
 
 		mtimer: timer@ffffff90 {
-			compatible = "neorv32-machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0xffffff90 0x10>;
+			reg = <0xffffff90 0x8 0xffffff98 0x8>;
-			interrupts = <7>;
+			interrupts-extended = <&intc 7>;
 		};
 
 		uart0: serial@ffffffa0 {

dts/riscv/niosv/niosv-g.dtsi

@@ -44,9 +44,10 @@
 		};
 
 		mtimer: machine-timer@90000 {
-			compatible = "niosv-machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0x90000 0x10>;
+			reg = <0x90000 0x8 0x90008 0x8>;
-			interrupts = <7>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&intc 7>;
 		};
 
 		uart0: serial@90078 {

dts/riscv/niosv/niosv-m.dtsi

@@ -44,9 +44,10 @@
 		};
 
 		mtimer: machine-timer@90000 {
-			compatible = "niosv-machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0x90000 0x10>;
+			reg = <0x90000 0x8 0x90008 0x8>;
-			interrupts = <7>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&intc 7>;
 		};
 
 		uart0: serial@90078 {

dts/riscv/qemu/virt-riscv.dtsi

@@ -193,5 +193,19 @@
 					       &hlic6 0x03 &hlic6 0x07
 					       &hlic7 0x03 &hlic7 0x07>;
 		};
+
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7
+						&hlic5 7
+						&hlic6 7
+						&hlic7 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
 	};
 };

dts/riscv/renode_riscv32_virt.dtsi

@@ -50,6 +50,13 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic0: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;

dts/riscv/sifive/riscv32-fe310.dtsi

@@ -65,6 +65,12 @@
 			interrupts-extended = <&hlic 3 &hlic 7>;
 			reg = <0x2000000 0x10000>;
 		};
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
 		debug: debug-controller@0 {
 			compatible = "sifive,debug-013", "riscv,debug-013";
 			interrupts-extended = <&hlic 65535>;

dts/riscv/sifive/riscv64-fu540.dtsi

@@ -182,6 +182,17 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		l2lim: l2lim@8000000 {
 			compatible = "sifive,l2lim0";
 			reg = <0x8000000 0x2000000>;

dts/riscv/sifive/riscv64-fu740.dtsi

@@ -137,13 +137,23 @@
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		l2lim: l2lim@8000000 {
 			compatible = "sifive,l2lim0";
 			reg = <0x0 0x8000000 0x0 0x200000>;
 			reg-names = "mem";
 		};
 
-
 		plic: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;

dts/riscv/starfive/jh7110-visionfive-v2.dtsi

@@ -145,8 +145,8 @@
 		compatible = "starfive,jh7110", "simple-bus";
 		ranges;
 
-		clint: timer@2000000 {
+		clint: clint@2000000 {
-			compatible = "starfive,jh7110-clint", "sifive,clint0";
+			compatible = "sifive,clint0";
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 						&cpu1_intc 3 &cpu1_intc 7
 						&cpu2_intc 3 &cpu2_intc 7
@@ -155,6 +155,17 @@
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&cpu0_intc 7
+						&cpu1_intc 7
+						&cpu2_intc 7
+						&cpu3_intc 7
+						&cpu4_intc 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		ccache: cache-controller@2010000 {
 			cache-block-size = <64>;
 			cache-level = <2>;

dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi

@@ -115,12 +115,19 @@
 		};
 
 		clint: clint@2000000 {
-			compatible = "starfive,jh7100-clint", "sifive,clint0";
+			compatible = "sifive,clint0";
 			interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 					       &cpu1intctrl 3 &cpu1intctrl 7>;
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&cpu0intctrl 7 &cpu1intctrl 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: plic@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;

dts/riscv/telink/telink_b91.dtsi

@@ -48,10 +48,10 @@
 		};
 
 		mtimer: timer@e6000000 {
-			compatible = "telink,machine-timer";
+			compatible = "riscv,machine-timer";
-			reg = <0xe6000000 0x10000>;
+			reg = <0xe6000000 0x8 0xe6000008 0x8>;
-			interrupts = <7 0>;
+			reg-names = "mtime", "mtimecmp";
-			interrupt-parent = <&plic0>;
+			interrupts-extended = <&plic0 7 0>;
 		};
 
 		flash_mspi: flash-controller@80140100 {