From f028973f4329f5f65be095053db29e821d8af995 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Iv=C3=A1n=20Briano?= Date: Wed, 26 Oct 2016 19:00:46 -0200 Subject: [PATCH] gpio qmsi: Enable SoC level GPIO to work on ARC too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GPIO and AON GPIO ports are available to both the x86 and ARC cores, but the driver always assumed only the x86 at the time of configuring interrupts. Use the available macros to set the correct values independently of which core it's being built for. Jira: ZEP-1030 Change-Id: I310afcc48780fbe1cac9dc3368a6de11bd797fda Signed-off-by: Iván Briano --- .../arc/soc/quark_se_c1000_ss/Kconfig.defconfig | 2 +- drivers/gpio/gpio_qmsi.c | 17 ++++++++++------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig b/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig index d6a017608dd..65097461687 100644 --- a/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig +++ b/arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig @@ -83,7 +83,7 @@ endif # RTC if GPIO config GPIO_QMSI - def_bool n + def_bool y if GPIO_QMSI diff --git a/drivers/gpio/gpio_qmsi.c b/drivers/gpio/gpio_qmsi.c index 28905b36f5e..16563a10b07 100644 --- a/drivers/gpio/gpio_qmsi.c +++ b/drivers/gpio/gpio_qmsi.c @@ -27,6 +27,7 @@ #include "gpio_utils.h" #include "qm_isr.h" #include "clk.h" +#include "soc.h" #include struct gpio_qmsi_config { @@ -419,18 +420,20 @@ static int gpio_qmsi_init(struct device *port) CLK_PERIPH_GPIO_INTERRUPT | CLK_PERIPH_GPIO_DB | CLK_PERIPH_CLK); - IRQ_CONNECT(QM_IRQ_GPIO_0_INT, CONFIG_GPIO_QMSI_0_IRQ_PRI, - qm_gpio_0_isr, 0, IOAPIC_LEVEL | IOAPIC_HIGH); - irq_enable(QM_IRQ_GPIO_0_INT); - QM_INTERRUPT_ROUTER->gpio_0_int_mask &= ~BIT(0); + IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT), + CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0, + IOAPIC_LEVEL | IOAPIC_HIGH); + irq_enable(IRQ_GET_NUMBER(QM_IRQ_GPIO_0_INT)); + QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask); break; #ifdef CONFIG_GPIO_QMSI_1 case QM_AON_GPIO_0: - IRQ_CONNECT(QM_IRQ_AON_GPIO_0_INT, + IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT), CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr, 0, IOAPIC_LEVEL | IOAPIC_HIGH); - irq_enable(QM_IRQ_AON_GPIO_0_INT); - QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask &= ~BIT(0); + irq_enable(IRQ_GET_NUMBER(QM_IRQ_AON_GPIO_0_INT)); + QM_IR_UNMASK_INTERRUPTS( + QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask); break; #endif /* CONFIG_GPIO_QMSI_1 */ default: