arch/x86: (Intel64) rename kernel segment constants
There's no need to qualify the 64-bit CS/DS selectors, and the GS and TR selectors are renamed CPU0_GS and CPU0_TR as they are CPU-specific. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
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90bf0da332
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2 changed files with 11 additions and 11 deletions
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@ -63,17 +63,17 @@ __start:
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lgdt gdt48
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lidt idt48
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jmpl $X86_KERNEL_CS_64, $1f
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jmpl $X86_KERNEL_CS, $1f
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.code64
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1: movl $X86_KERNEL_DS_64, %eax
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1: movl $X86_KERNEL_DS, %eax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movl $X86_KERNEL_TSS, %eax
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movl $X86_KERNEL_CPU0_TR, %eax
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ltr %ax
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movl $X86_KERNEL_GS_64, %eax
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movl $X86_KERNEL_CPU0_GS, %eax
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movw %ax, %gs
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movl $(_interrupt_stack + CONFIG_ISR_STACK_SIZE), %esp
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@ -158,10 +158,10 @@ z_arch_switch:
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*/
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__resume:
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pushq $X86_KERNEL_DS_64 /* SS */
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pushq $X86_KERNEL_DS /* SS */
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pushq _thread_offset_to_rsp(%rdi) /* RSP */
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pushq _thread_offset_to_rflags(%rdi) /* RFLAGS */
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pushq $X86_KERNEL_CS_64 /* CS */
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pushq $X86_KERNEL_CS /* CS */
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pushq _thread_offset_to_rip(%rdi) /* RIP */
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movq _thread_offset_to_rbx(%rdi), %rbx
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@ -231,7 +231,7 @@ gdt48:
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#define INTR 0x8e
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#define IDT(nr, type, ist) \
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.word vector_ ## nr, X86_KERNEL_CS_64; \
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.word vector_ ## nr, X86_KERNEL_CS; \
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.byte ist, type; \
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.word 0, 0, 0, 0, 0
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@ -20,11 +20,11 @@
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#define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
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#define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
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#define X86_KERNEL_CS_64 0x18 /* 64-bit kernel code */
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#define X86_KERNEL_DS_64 0x20 /* 64-bit kernel data */
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#define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
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#define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
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#define X86_KERNEL_GS_64 0x30 /* data selector covering TSS */
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#define X86_KERNEL_TSS 0x40 /* 64-bit task state segment */
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#define X86_KERNEL_CPU0_GS 0x30 /* data selector covering TSS */
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#define X86_KERNEL_CPU0_TR 0x40 /* 64-bit task state segment */
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#ifndef _ASMLANGUAGE
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