arch/x86: (Intel64) rename kernel segment constants

There's no need to qualify the 64-bit CS/DS selectors, and the GS and
TR selectors are renamed CPU0_GS and CPU0_TR as they are CPU-specific.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-09-28 17:50:03 -04:00 committed by Anas Nashif
commit edf5761c83
2 changed files with 11 additions and 11 deletions

View file

@ -63,17 +63,17 @@ __start:
lgdt gdt48
lidt idt48
jmpl $X86_KERNEL_CS_64, $1f
jmpl $X86_KERNEL_CS, $1f
.code64
1: movl $X86_KERNEL_DS_64, %eax
1: movl $X86_KERNEL_DS, %eax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movl $X86_KERNEL_TSS, %eax
movl $X86_KERNEL_CPU0_TR, %eax
ltr %ax
movl $X86_KERNEL_GS_64, %eax
movl $X86_KERNEL_CPU0_GS, %eax
movw %ax, %gs
movl $(_interrupt_stack + CONFIG_ISR_STACK_SIZE), %esp
@ -158,10 +158,10 @@ z_arch_switch:
*/
__resume:
pushq $X86_KERNEL_DS_64 /* SS */
pushq $X86_KERNEL_DS /* SS */
pushq _thread_offset_to_rsp(%rdi) /* RSP */
pushq _thread_offset_to_rflags(%rdi) /* RFLAGS */
pushq $X86_KERNEL_CS_64 /* CS */
pushq $X86_KERNEL_CS /* CS */
pushq _thread_offset_to_rip(%rdi) /* RIP */
movq _thread_offset_to_rbx(%rdi), %rbx
@ -231,7 +231,7 @@ gdt48:
#define INTR 0x8e
#define IDT(nr, type, ist) \
.word vector_ ## nr, X86_KERNEL_CS_64; \
.word vector_ ## nr, X86_KERNEL_CS; \
.byte ist, type; \
.word 0, 0, 0, 0, 0

View file

@ -20,11 +20,11 @@
#define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
#define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
#define X86_KERNEL_CS_64 0x18 /* 64-bit kernel code */
#define X86_KERNEL_DS_64 0x20 /* 64-bit kernel data */
#define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
#define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
#define X86_KERNEL_GS_64 0x30 /* data selector covering TSS */
#define X86_KERNEL_TSS 0x40 /* 64-bit task state segment */
#define X86_KERNEL_CPU0_GS 0x30 /* data selector covering TSS */
#define X86_KERNEL_CPU0_TR 0x40 /* 64-bit task state segment */
#ifndef _ASMLANGUAGE