arch: x86: Better document that CR0.WP will also be set when CR0.PG is
Setting bit CR0.WP (bit 16) will inhibit supervisor threads from writing to RO pages. It's a necessary flag to be set, and the constant name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was being set. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
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2 changed files with 3 additions and 3 deletions
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@ -368,9 +368,9 @@ __csSet:
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orl $0x800, %eax
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wrmsr
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#endif
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/* set CR0.PG bit (31st bit in CR0)*/
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/* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
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movl %cr0, %eax
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orl $CR0_PAGING_ENABLE, %eax
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orl $CR0_PG_WP_ENABLE, %eax
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movl %eax, %cr0
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#endif /* CONFIG_X86_MMU */
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@ -386,7 +386,7 @@
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#define EFLAGS_MASK 0x00003200
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/* Enable paging and write protection */
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#define CR0_PAGING_ENABLE 0x80010000
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#define CR0_PG_WP_ENABLE 0x80010000
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/* Clear the 5th bit in CR4 */
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#define CR4_PAE_DISABLE 0xFFFFFFEF
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/* Set the 5th bit in CR4 */
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