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arch: x86: Better document that CR0.WP will also be set when CR0.PG is

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Setting bit CR0.WP (bit 16) will inhibit supervisor threads from
writing to RO pages.  It's a necessary flag to be set, and the constant
name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was
being set.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This commit is contained in:
Leandro Pereira 2018-05-25 16:23:12 -07:00 • committed by Anas Nashif
commit edd18c8f5a
2 changed files with 3 additions and 3 deletions
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4
arch/x86/core/crt0.S
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@ -368,9 +368,9 @@ __csSet:
orl $0x800, %eax
wrmsr
#endif
/* set CR0.PG bit (31st bit in CR0)*/
/* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */
movl %cr0, %eax
orl $CR0_PAGING_ENABLE, %eax
orl $CR0_PG_WP_ENABLE, %eax
movl %eax, %cr0
#endif /* CONFIG_X86_MMU */

2
arch/x86/include/kernel_arch_data.h
View file

@ -386,7 +386,7 @@
#define EFLAGS_MASK 0x00003200
/* Enable paging and write protection */
#define CR0_PAGING_ENABLE 0x80010000
#define CR0_PG_WP_ENABLE 0x80010000
/* Clear the 5th bit in CR4 */
#define CR4_PAE_DISABLE 0xFFFFFFEF
/* Set the 5th bit in CR4 */