From edd18c8f5aab10f5dd0dc13813911ecb537da33a Mon Sep 17 00:00:00 2001 From: Leandro Pereira Date: Fri, 25 May 2018 16:23:12 -0700 Subject: [PATCH] arch: x86: Better document that CR0.WP will also be set when CR0.PG is Setting bit CR0.WP (bit 16) will inhibit supervisor threads from writing to RO pages. It's a necessary flag to be set, and the constant name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was being set. Signed-off-by: Leandro Pereira --- arch/x86/core/crt0.S | 4 ++-- arch/x86/include/kernel_arch_data.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/core/crt0.S b/arch/x86/core/crt0.S index 696ac558c49..038a10adbc1 100644 --- a/arch/x86/core/crt0.S +++ b/arch/x86/core/crt0.S @@ -368,9 +368,9 @@ __csSet: orl $0x800, %eax wrmsr #endif - /* set CR0.PG bit (31st bit in CR0)*/ + /* Enable paging (CR0.PG, bit 31) / write protect (CR0.WP, bit 16) */ movl %cr0, %eax - orl $CR0_PAGING_ENABLE, %eax + orl $CR0_PG_WP_ENABLE, %eax movl %eax, %cr0 #endif /* CONFIG_X86_MMU */ diff --git a/arch/x86/include/kernel_arch_data.h b/arch/x86/include/kernel_arch_data.h index 0834b525a65..d91b109d0de 100644 --- a/arch/x86/include/kernel_arch_data.h +++ b/arch/x86/include/kernel_arch_data.h @@ -386,7 +386,7 @@ #define EFLAGS_MASK 0x00003200 /* Enable paging and write protection */ -#define CR0_PAGING_ENABLE 0x80010000 +#define CR0_PG_WP_ENABLE 0x80010000 /* Clear the 5th bit in CR4 */ #define CR4_PAE_DISABLE 0xFFFFFFEF /* Set the 5th bit in CR4 */