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drivers: interrupt_controller: intc_clic: add CLIC SMCLICCONFIG extension

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Add support for CLIC SMCLICCONFIG extension, allowing user to configure
the number of available interrupt level bits at runtime.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2025-02-12 14:36:53 +08:00 • committed by Benjamin Cabé
commit ed97af9309
2 changed files with 12 additions and 3 deletions
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7
drivers/interrupt_controller/Kconfig.clic
View file

@ -16,6 +16,7 @@ config NUCLEI_ECLIC
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
select CLIC
select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
select CLIC_SMCLICCONFIG_EXT
help
Interrupt controller for Nuclei SoC core.
@ -36,6 +37,12 @@ config CLIC_SMCLICSHV_EXT
to select the behavior for each interrupt. The CLIC driver needs to
implement the riscv_clic_irq_vector_set() function.
config CLIC_SMCLICCONFIG_EXT
bool
help
Enables the SMCLICCONFIG extension, allowing configuration of CLIC
parameters such as the number of interrupt level bits.
config LEGACY_CLIC
bool "Use the legacy clic specification"
depends on RISCV_HAS_CLIC

8
drivers/interrupt_controller/intc_clic.c
View file

@ -222,15 +222,17 @@ static int clic_init(const struct device *dev)
if (data->nlbits > data->intctlbits) {
data->nlbits = data->intctlbits;
}
} else {
/* Configure the interrupt level threshold by CSR mintthresh. */
csr_write(CSR_MINTTHRESH, 0x0);
}
if (IS_ENABLED(CONFIG_CLIC_SMCLICCONFIG_EXT)) {
/* Configure the number of bits assigned to interrupt levels. */
union CLICCFG cliccfg = {.qw = read_clic32(dev, CLIC_CFG)};
cliccfg.w.nlbits = data->nlbits;
write_clic32(dev, CLIC_CFG, cliccfg.qw);
} else {
/* Configure the interrupt level threshold by CSR mintthresh. */
csr_write(CSR_MINTTHRESH, 0x0);
}
/* Reset all interrupt control register */