diff --git a/drivers/interrupt_controller/Kconfig.clic b/drivers/interrupt_controller/Kconfig.clic
index c8e09a7502f..0c5f768d680 100644
--- a/drivers/interrupt_controller/Kconfig.clic
+++ b/drivers/interrupt_controller/Kconfig.clic
@@ -16,6 +16,7 @@ config NUCLEI_ECLIC
 	depends on DT_HAS_NUCLEI_ECLIC_ENABLED
 	select CLIC
 	select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
+	select CLIC_SMCLICCONFIG_EXT
 	help
 	  Interrupt controller for Nuclei SoC core.
 
@@ -36,6 +37,12 @@ config CLIC_SMCLICSHV_EXT
 	  to select the behavior for each interrupt. The CLIC driver needs to
 	  implement the riscv_clic_irq_vector_set() function.
 
+config CLIC_SMCLICCONFIG_EXT
+	bool
+	help
+	  Enables the SMCLICCONFIG extension, allowing configuration of CLIC
+	  parameters such as the number of interrupt level bits.
+
 config LEGACY_CLIC
 	bool "Use the legacy clic specification"
 	depends on RISCV_HAS_CLIC
diff --git a/drivers/interrupt_controller/intc_clic.c b/drivers/interrupt_controller/intc_clic.c
index dec5d19c219..d6411dbf452 100644
--- a/drivers/interrupt_controller/intc_clic.c
+++ b/drivers/interrupt_controller/intc_clic.c
@@ -222,15 +222,17 @@ static int clic_init(const struct device *dev)
 		if (data->nlbits > data->intctlbits) {
 			data->nlbits = data->intctlbits;
 		}
+	} else {
+		/* Configure the interrupt level threshold by CSR mintthresh. */
+		csr_write(CSR_MINTTHRESH, 0x0);
+	}
 
+	if (IS_ENABLED(CONFIG_CLIC_SMCLICCONFIG_EXT)) {
 		/* Configure the number of bits assigned to interrupt levels. */
 		union CLICCFG cliccfg = {.qw = read_clic32(dev, CLIC_CFG)};
 
 		cliccfg.w.nlbits = data->nlbits;
 		write_clic32(dev, CLIC_CFG, cliccfg.qw);
-	} else {
-		/* Configure the interrupt level threshold by CSR mintthresh. */
-		csr_write(CSR_MINTTHRESH, 0x0);
 	}
 
 	/* Reset all interrupt control register */