michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: intel_adsp: Clean up shim driver

Browse source 
Each platform was defining its own shim.h header, with slightly
variant field definitions, for a register block that is almost
completely compatible between versions.  This is made worse by the
fact that these represent an API imported fairly early from SOF, the
upstream version of which has since diverged.

Move the existing shim struct into a header ("cavs-shim.h") of its
own, remove a bunch of unused symbols, fill in definitions for some
registers that were left out, correct naming to match the hardware
docs in a few places, make sure all hardware dependencies are source
from devicetree only, and modify existing usage to use the new API
exclusively.

Interestingly this leaves the older shim.h header in place, as it
turns out to contain definitions for a bunch of things that were never
part of the shim register block.  Those will be unified in separate
patches.

Finally: note that the existing IPM_CAVS_IDC driver (soon to be
removed from all the intel_adsp soc's) is still using the old API, so
redeclare the minimal subset that it needs for the benefit of the
platforms in transition.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-09-05 15:27:46 -07:00 • committed by Anas Nashif
commit ed9434c812
21 changed files with 220 additions and 1124 deletions
Download patch file Download diff file Expand all files Collapse all files

36
drivers/timer/cavs_timer.c
View file

@ -8,6 +8,7 @@
#include <sys_clock.h>
#include <spinlock.h>
#include <cavs-idc.h>
#include <cavs-shim.h>
/**
* @file
@ -27,30 +28,26 @@
#define MIN_DELAY (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 100000)
BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK);
BUILD_ASSERT(TIMER >= 0 && TIMER <= 1);
static struct k_spinlock lock;
static uint64_t last_count;
static volatile struct soc_dsp_shim_regs *shim_regs =
(volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
static void set_compare(uint64_t time)
{
/* Disarm the comparator to prevent spurious triggers */
shim_regs->dspwctcs &= ~DSP_WCT_CS_TA(TIMER);
CAVS_SHIM.dspwctcs &= ~DSP_WCT_CS_TA(TIMER);
#if (TIMER == 0)
/* Set compare register */
shim_regs->dspwct0c = time;
#elif (TIMER == 1)
/* Set compare register */
shim_regs->dspwct1c = time;
#else
#error "TIMER has to be 0 or 1!"
#endif
if (TIMER == 0) {
CAVS_SHIM.dspwct0c_lo = (uint32_t)time;
CAVS_SHIM.dspwct0c_hi = (uint32_t)(time >> 32);
} else {
CAVS_SHIM.dspwct1c_lo = (uint32_t)time;
CAVS_SHIM.dspwct1c_hi = (uint32_t)(time >> 32);
}
/* Arm the timer */
shim_regs->dspwctcs |= DSP_WCT_CS_TA(TIMER);
CAVS_SHIM.dspwctcs |= DSP_WCT_CS_TA(TIMER);
}
static uint64_t count(void)
@ -61,13 +58,12 @@ static uint64_t count(void)
* word. Wrap the low read between two reads of the high word
* and make sure it didn't change.
*/
volatile uint32_t *wc = (void *)&shim_regs->walclk;
uint32_t hi0, hi1, lo;
do {
hi0 = wc[1];
lo = wc[0];
hi1 = wc[1];
hi0 = CAVS_SHIM.dspwc_hi;
lo = CAVS_SHIM.dspwc_lo;
hi1 = CAVS_SHIM.dspwc_hi;
} while (hi0 != hi1);
return (((uint64_t)hi0) << 32) | lo;
@ -75,7 +71,7 @@ static uint64_t count(void)
static uint32_t count32(void)
{
return shim_regs->walclk32_lo;
return CAVS_SHIM.dspwc_lo;
}
static void compare_isr(const void *arg)
@ -104,7 +100,7 @@ static void compare_isr(const void *arg)
dticks = (uint32_t)((curr - last_count) / CYC_PER_TICK);
/* Clear the triggered bit */
shim_regs->dspwctcs |= DSP_WCT_CS_TT(TIMER);
CAVS_SHIM.dspwctcs |= DSP_WCT_CS_TT(TIMER);
last_count += dticks * CYC_PER_TICK;