diff --git a/drivers/ipm/ipm_cavs_idc.h b/drivers/ipm/ipm_cavs_idc.h index f30a31b72a2..0be933bcc18 100644 --- a/drivers/ipm/ipm_cavs_idc.h +++ b/drivers/ipm/ipm_cavs_idc.h @@ -7,6 +7,28 @@ #ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ #define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ +/* Redeclaration of the earlier IDC register API for platforms being + * held back on this driver. + */ +#ifndef CONFIG_SOC_INTEL_S1000 +# ifndef IPC_DSP_BASE +# define IPC_DSP_BASE(core) (DT_REG_ADDR(DT_NODELABEL(idc)) + 0x80 * (core)) +# endif +#define IPC_IDCTFC(x) (x * 0x10) +#define IPC_IDCTFC_BUSY BIT(31) +#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF +#define IPC_IDCTEFC(x) (0x4 + x * 0x10) +#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF +#define IPC_IDCITC(x) (0x8 + x * 0x10) +#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF +#define IPC_IDCITC_BUSY BIT(31) +#define IPC_IDCIETC(x) (0xc + x * 0x10) +#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF +#define IPC_IDCIETC_DONE BIT(30) +#define IPC_IDCCTL 0x50 +#define IPC_IDCCTL_IDCTBIE(x) BIT(x) +#endif + #define IPM_CAVS_IDC_ID_MASK \ (CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \ CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK)) diff --git a/drivers/timer/cavs_timer.c b/drivers/timer/cavs_timer.c index 33ea1b7b28c..92c29e3f4ed 100644 --- a/drivers/timer/cavs_timer.c +++ b/drivers/timer/cavs_timer.c @@ -8,6 +8,7 @@ #include #include #include +#include /** * @file @@ -27,30 +28,26 @@ #define MIN_DELAY (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 100000) BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK); +BUILD_ASSERT(TIMER >= 0 && TIMER <= 1); static struct k_spinlock lock; static uint64_t last_count; -static volatile struct soc_dsp_shim_regs *shim_regs = - (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE; - static void set_compare(uint64_t time) { /* Disarm the comparator to prevent spurious triggers */ - shim_regs->dspwctcs &= ~DSP_WCT_CS_TA(TIMER); + CAVS_SHIM.dspwctcs &= ~DSP_WCT_CS_TA(TIMER); -#if (TIMER == 0) - /* Set compare register */ - shim_regs->dspwct0c = time; -#elif (TIMER == 1) - /* Set compare register */ - shim_regs->dspwct1c = time; -#else -#error "TIMER has to be 0 or 1!" -#endif + if (TIMER == 0) { + CAVS_SHIM.dspwct0c_lo = (uint32_t)time; + CAVS_SHIM.dspwct0c_hi = (uint32_t)(time >> 32); + } else { + CAVS_SHIM.dspwct1c_lo = (uint32_t)time; + CAVS_SHIM.dspwct1c_hi = (uint32_t)(time >> 32); + } /* Arm the timer */ - shim_regs->dspwctcs |= DSP_WCT_CS_TA(TIMER); + CAVS_SHIM.dspwctcs |= DSP_WCT_CS_TA(TIMER); } static uint64_t count(void) @@ -61,13 +58,12 @@ static uint64_t count(void) * word. Wrap the low read between two reads of the high word * and make sure it didn't change. */ - volatile uint32_t *wc = (void *)&shim_regs->walclk; uint32_t hi0, hi1, lo; do { - hi0 = wc[1]; - lo = wc[0]; - hi1 = wc[1]; + hi0 = CAVS_SHIM.dspwc_hi; + lo = CAVS_SHIM.dspwc_lo; + hi1 = CAVS_SHIM.dspwc_hi; } while (hi0 != hi1); return (((uint64_t)hi0) << 32) | lo; @@ -75,7 +71,7 @@ static uint64_t count(void) static uint32_t count32(void) { - return shim_regs->walclk32_lo; + return CAVS_SHIM.dspwc_lo; } static void compare_isr(const void *arg) @@ -104,7 +100,7 @@ static void compare_isr(const void *arg) dticks = (uint32_t)((curr - last_count) / CYC_PER_TICK); /* Clear the triggered bit */ - shim_regs->dspwctcs |= DSP_WCT_CS_TT(TIMER); + CAVS_SHIM.dspwctcs |= DSP_WCT_CS_TT(TIMER); last_count += dticks * CYC_PER_TICK; diff --git a/dts/xtensa/intel/intel_cavs15.dtsi b/dts/xtensa/intel/intel_cavs15.dtsi index 49f3788b90d..d816d19516d 100644 --- a/dts/xtensa/intel/intel_cavs15.dtsi +++ b/dts/xtensa/intel/intel_cavs15.dtsi @@ -37,6 +37,11 @@ }; soc { + shim: shim@1000 { + compatible = "intel,cavs-shim"; + reg = <0x1000 0x100>; + }; + core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; diff --git a/dts/xtensa/intel/intel_cavs18.dtsi b/dts/xtensa/intel/intel_cavs18.dtsi index 15ba95e7468..aed380fb327 100644 --- a/dts/xtensa/intel/intel_cavs18.dtsi +++ b/dts/xtensa/intel/intel_cavs18.dtsi @@ -51,6 +51,11 @@ }; soc { + shim: shim@71f00 { + compatible = "intel,cavs-shim"; + reg = <0x71f00 0x100>; + }; + core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; diff --git a/dts/xtensa/intel/intel_cavs20.dtsi b/dts/xtensa/intel/intel_cavs20.dtsi index 15ba95e7468..aed380fb327 100644 --- a/dts/xtensa/intel/intel_cavs20.dtsi +++ b/dts/xtensa/intel/intel_cavs20.dtsi @@ -51,6 +51,11 @@ }; soc { + shim: shim@71f00 { + compatible = "intel,cavs-shim"; + reg = <0x71f00 0x100>; + }; + core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; diff --git a/dts/xtensa/intel/intel_cavs25.dtsi b/dts/xtensa/intel/intel_cavs25.dtsi index f6dd7e8f7d8..a567ba1aa79 100644 --- a/dts/xtensa/intel/intel_cavs25.dtsi +++ b/dts/xtensa/intel/intel_cavs25.dtsi @@ -51,6 +51,11 @@ }; soc { + shim: shim@71f00 { + compatible = "intel,cavs-shim"; + reg = <0x71f00 0x100>; + }; + core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 37f54ed131f..4e4b81df4e2 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -140,10 +140,6 @@ #define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_OFFSET 0x20000000 -/* shim */ -#define SHIM_BASE 0x00001000 -#define SHIM_SIZE 0x00000100 - /* IRQ controller */ #define IRQ_BASE 0x00001600 #define IRQ_SIZE 0x00000200 diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h index c811397da2e..ab60fef63f3 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h @@ -10,260 +10,14 @@ #define __PLATFORM_LIB_SHIM_H__ #include - -#ifndef ASSEMBLY -#include -#include -#endif - -#if !defined(__ASSEMBLER__) && !defined(LINKER) -#include -#include -#endif - -#ifndef BIT -#define BIT(b) (1 << (b)) -#endif - -/* DSP IPC for Host Registers */ -#define IPC_DIPCT 0x00 -#define IPC_DIPCTE 0x04 -#define IPC_DIPCI 0x08 -#define IPC_DIPCIE 0x0c -#define IPC_DIPCCTL 0x10 - -/* DIPCT */ -#define IPC_DIPCT_BUSY BIT(31) -#define IPC_DIPCT_MSG_MASK 0x7FFFFFFF - -/* DIPCTE */ -#define IPC_DIPCTE_MSG_MASK 0x3FFFFFFF - -/* DIPCI */ -#define IPC_DIPCI_BUSY BIT(31) -#define IPC_DIPCI_MSG_MASK 0x7FFFFFFF - -/* DIPCIE */ -#define IPC_DIPCIE_DONE BIT(30) -#define IPC_DIPCIE_MSG_MASK 0x3FFFFFFF - -/* DIPCCTL */ -#define IPC_DIPCCTL_IPCIDIE BIT(1) -#define IPC_DIPCCTL_IPCTBIE BIT(0) - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) +#include #define IRQ_CPU_OFFSET 0x40 -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief Request Audio PLL Clock */ -#define SHIM_CLKCTL_RAPLLC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request Fast RING Oscillator Clock */ -#define SHIM_CLKCTL_RFROSCC BIT(29) - -/** \brief LP GPDMA Force Dynamic Clock Gating bits, 0: enable */ -#define SHIM_CLKCTL_LPGPDMAFDCGB(x) BIT(26 + x) - -/** \brief DMIC Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_DMICFDCGB BIT(24) - -/** \brief I2S Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) - -/** \brief I2S Extension Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 - -/** \brief Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) (0x3 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV1(x) (0x0 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV2(x) (0x1 << (8 + x * 2)) -#define SHIM_CLKCTL_DPCS_DIV4(x) (0x3 << (8 + x * 2)) - -/** \brief Tensilica Core Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS_EN BIT(7) -#define SHIM_CLKCTL_TCPAPLLS_DIS 0 - -/** \brief LP domain clock select, 0: PLL, 1: oscillator */ -#define SHIM_CLKCTL_LDCS_XTAL BIT(5) -#define SHIM_CLKCTL_LDCS_PLL 0 - -/** \brief HP domain clock select */ -#define SHIM_CLKCTL_HDCS BIT(4) -#define SHIM_CLKCTL_HDCS_XTAL BIT(4) -#define SHIM_CLKCTL_HDCS_PLL 0 - -/** \brief LP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_LDOCS BIT(3) - -/** \brief HP domain oscillator clock select select, 0: XTAL, 1: Fast RING */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/** \brief LP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_LPMPCS_DIV4 BIT(1) -#define SHIM_CLKCTL_LPMPCS_DIV2 0 - -/** \brief HP memory clock PLL divisor, 0: div by 2, 1: div by 4 */ -#define SHIM_CLKCTL_HPMPCS_DIV4 BIT(0) -#define SHIM_CLKCTL_HPMPCS_DIV2 0 - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRSTS 0x92 -#define SHIM_LPSCTL 0x94 - -/* HP & LP SRAM Power Gating */ -#define SHIM_HSPGCTL 0x80 -#define SHIM_LSPGCTL 0x84 -#define SHIM_SPSREQ 0xa0 -#define LSPGCTL (SHIM_BASE + SHIM_LSPGCTL) - -#define SHIM_SPSREQ_RVNNP BIT(0) - -/** \brief GPDMA shim registers Control */ -#define SHIM_GPDMA_BASE_OFFSET 0xC00 -#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x80) - -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(5) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(4, 0, x) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - -#define SHIM_HSPGISTS 0xb0 -#define SHIM_LSPGISTS 0xb4 -#define LSPGISTS (SHIM_BASE + SHIM_LSPGISTS) - - -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_FDMARUN BIT(8) - -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -#define SHIM_LPGPDMAC(x) (0x1110 + (2 * x)) -#define SHIM_LPGPDMAC_CTLOSEL BIT(15) -#define SHIM_LPGPDMAC_CHOSEL 0xFF - -#define SHIM_DSPIOPO 0x1118 -#define SHIM_DSPIOPO_DMICOSEL BIT(0) -#define SHIM_DSPIOPO_I2SOSEL (0x3F << 8) - -#define SHIM_GENO 0x111C -#define SHIM_GENO_SHIMOSEL BIT(0) -#define SHIM_GENO_MDIVOSEL BIT(1) -#define SHIM_GENO_DIOPTOSEL BIT(2) - -#define SHIM_L2_CACHE_CTRL (SHIM_BASE + 0x500) -#define SHIM_L2_PREF_CFG (SHIM_BASE + 0x508) -#define SHIM_L2_CACHE_PREF (SHIM_BASE + 0x510) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) #define DMWBA_ENABLE BIT(0) #define DMWBA_READONLY BIT(1) - #endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index ab8302d1fc3..3bccafddca2 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -137,10 +137,6 @@ #define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_OFFSET 0x20000000 -/* shim */ -#define SHIM_BASE 0x00071F00 -#define SHIM_SIZE 0x00000100 - /* IRQ controller */ #define IRQ_BASE 0x00078800 #define IRQ_SIZE 0x00000200 diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h index 20cfc4bf7c4..ff575386e8d 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h @@ -11,199 +11,10 @@ #define __PLATFORM_LIB_SHIM_H__ #include - -#ifndef ASSEMBLY -#include -#include -#endif - -#if !defined(__ASSEMBLER__) && !defined(LINKER) -#include -#include -#endif - -#ifndef BIT -#define BIT(b) (1 << (b)) -#endif - -/* DSP IPC for Host Registers */ -#define IPC_DIPCTDR 0x00 -#define IPC_DIPCTDA 0x04 -#define IPC_DIPCTDD 0x08 -#define IPC_DIPCIDR 0x10 -#define IPC_DIPCIDA 0x14 -#define IPC_DIPCIDD 0x18 -#define IPC_DIPCCTL 0x28 - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) +#include #define IRQ_CPU_OFFSET 0x40 -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 -#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \ - SHIM_CLKCTL_TCPLCG_DIS(1) | \ - SHIM_CLKCTL_TCPLCG_DIS(2) | \ - SHIM_CLKCTL_TCPLCG_DIS(3)) - -/** \brief Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) - -/** \brief DMIC Force Dynamic Clock Gating */ -#define SHIM_CLKCTL_DMICFDCGB BIT(30) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/* Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) - -/* Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS BIT(7) - -/* 0--from PLL, 1--from oscillator */ -#define SHIM_CLKCTL_HDCS BIT(4) - -/* Oscillator select */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/* HP memory clock PLL divisor */ -#define SHIM_CLKCTL_HPMPCS BIT(0) - -/** \brief Mask for requesting clock - */ -#define SHIM_CLKCTL_OSC_REQUEST_MASK \ - (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ - SHIM_CLKCTL_RLROSCC) - -/** \brief Mask for setting previously requested clock - */ -#define SHIM_CLKCTL_OSC_SOURCE_MASK \ - (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ - SHIM_CLKCTL_HMCS_DIV4) - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) -#define SHIM_PWRCTL_TCPCTLPG BIT(4) - -#define SHIM_PWRSTS 0x92 - -#define SHIM_LPSCTL 0x94 -#define SHIM_LPSCTL_BID BIT(7) -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_BATTR_0 BIT(12) - /** \brief GPDMA shim registers Control */ #define SHIM_GPDMA_BASE_OFFSET 0x6500 #define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) @@ -213,21 +24,10 @@ /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ #define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(7) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) - -#define L2LMCAP 0x71D00 -#define L2MPAT 0x71D04 - #define HSPGCTL0 0x71D10 #define HSRMCTL0 0x71D14 #define HSPGISTS0 0x71D18 -#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) -#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) - #define HSPGCTL1 0x71D20 #define HSRMCTL1 0x71D24 #define HSPGISTS1 0x71D28 @@ -236,50 +36,18 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define LPGPDMA_CTLOSEL_FLAG BIT(15) #define LPGPDMA_CHOSEL_FLAG 0xFF -#define DSP_INIT_IOPO 0x71A68 -#define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG (7 << 8) - #define DSP_INIT_GENO 0x71A6C #define GENO_MDIVOSEL BIT(1) #define GENO_DIOPTOSEL BIT(2) -#define DSP_INIT_ALHO 0x71A70 -#define ALHO_ASO_FLAG BIT(0) -#define ALHO_CSO_FLAG BIT(1) -#define ALHO_CFO_FLAG BIT(2) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) #define DMWBA_ENABLE BIT(0) #define DMWBA_READONLY BIT(1) -/* DMIC power ON bit */ -#define DMICLCTL_SPA ((uint32_t) BIT(0)) - -/* DMIC disable clock gating */ -#define DMIC_DCGD ((uint32_t) BIT(30)) - #endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 0ffcebc39ba..6734ae15484 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -137,10 +137,6 @@ #define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_OFFSET 0x20000000 -/* shim */ -#define SHIM_BASE 0x00071F00 -#define SHIM_SIZE 0x00000100 - /* IRQ controller */ #define IRQ_BASE 0x00078800 #define IRQ_SIZE 0x00000200 diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h index f17254255b2..ff575386e8d 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h @@ -11,193 +11,10 @@ #define __PLATFORM_LIB_SHIM_H__ #include - -#ifndef ASSEMBLY -#include -#include -#endif - -#if !defined(__ASSEMBLER__) && !defined(LINKER) -#include -#include -#endif - -#ifndef BIT -#define BIT(b) (1 << (b)) -#endif - -/* DSP IPC for Host Registers */ -#define IPC_DIPCTDR 0x00 -#define IPC_DIPCTDA 0x04 -#define IPC_DIPCTDD 0x08 -#define IPC_DIPCIDR 0x10 -#define IPC_DIPCIDA 0x14 -#define IPC_DIPCIDD 0x18 -#define IPC_DIPCCTL 0x28 - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) +#include #define IRQ_CPU_OFFSET 0x40 -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 -#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \ - SHIM_CLKCTL_TCPLCG_DIS(1) | \ - SHIM_CLKCTL_TCPLCG_DIS(2) | \ - SHIM_CLKCTL_TCPLCG_DIS(3)) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/* Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) - -/* Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS BIT(7) - -/* 0--from PLL, 1--from oscillator */ -#define SHIM_CLKCTL_HDCS BIT(4) - -/* Oscillator select */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/* HP memory clock PLL divisor */ -#define SHIM_CLKCTL_HPMPCS BIT(0) - -/** \brief Mask for requesting clock - */ -#define SHIM_CLKCTL_OSC_REQUEST_MASK \ - (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ - SHIM_CLKCTL_RLROSCC) - -/** \brief Mask for setting previously requested clock - */ -#define SHIM_CLKCTL_OSC_SOURCE_MASK \ - (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ - SHIM_CLKCTL_HMCS_DIV4) - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) -#define SHIM_PWRCTL_TCPCTLPG BIT(4) - -#define SHIM_PWRSTS 0x92 - -#define SHIM_LPSCTL 0x94 -#define SHIM_LPSCTL_BID BIT(7) -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_BATTR_0 BIT(12) - /** \brief GPDMA shim registers Control */ #define SHIM_GPDMA_BASE_OFFSET 0x6500 #define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) @@ -207,21 +24,10 @@ /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ #define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(7) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) - -#define L2LMCAP 0x71D00 -#define L2MPAT 0x71D04 - #define HSPGCTL0 0x71D10 #define HSRMCTL0 0x71D14 #define HSPGISTS0 0x71D18 -#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) -#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) - #define HSPGCTL1 0x71D20 #define HSRMCTL1 0x71D24 #define HSPGISTS1 0x71D28 @@ -230,50 +36,18 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define LPGPDMA_CTLOSEL_FLAG BIT(15) #define LPGPDMA_CHOSEL_FLAG 0xFF -#define DSP_INIT_IOPO 0x71A68 -#define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) - #define DSP_INIT_GENO 0x71A6C #define GENO_MDIVOSEL BIT(1) #define GENO_DIOPTOSEL BIT(2) -#define DSP_INIT_ALHO 0x71A70 -#define ALHO_ASO_FLAG BIT(0) -#define ALHO_CSO_FLAG BIT(1) -#define ALHO_CFO_FLAG BIT(2) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) #define DMWBA_ENABLE BIT(0) #define DMWBA_READONLY BIT(1) -/* DMIC power ON bit */ -#define DMICLCTL_SPA ((uint32_t) BIT(0)) - -/* DMIC disable clock gating */ -#define DMIC_DCGD ((uint32_t) BIT(30)) - #endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 7751ef6078a..5bdee07c78e 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -139,10 +139,6 @@ #define SRAM_ALIAS_MASK 0xFF000000 #define SRAM_ALIAS_OFFSET 0x20000000 -/* shim */ -#define SHIM_BASE 0x00071F00 -#define SHIM_SIZE 0x00000100 - /* IRQ controller */ #define IRQ_BASE 0x00078800 #define IRQ_SIZE 0x00000200 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h index 42e62dd1a22..b9c47950b7c 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h @@ -11,225 +11,22 @@ #define __PLATFORM_LIB_SHIM_H__ #include - -#ifndef ASSEMBLY -#include -#include -#endif - -#if !defined(__ASSEMBLER__) && !defined(LINKER) -#include -#include -#endif - -#ifndef BIT -#define BIT(b) (1 << (b)) -#endif - -/* DSP IPC for Host Registers */ -#define IPC_DIPCTDR 0x00 -#define IPC_DIPCTDA 0x04 -#define IPC_DIPCTDD 0x08 -#define IPC_DIPCIDR 0x10 -#define IPC_DIPCIDA 0x14 -#define IPC_DIPCIDD 0x18 -#define IPC_DIPCCTL 0x28 - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) +#include #define IRQ_CPU_OFFSET 0x40 -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 -#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \ - SHIM_CLKCTL_TCPLCG_DIS(1) | \ - SHIM_CLKCTL_TCPLCG_DIS(2) | \ - SHIM_CLKCTL_TCPLCG_DIS(3)) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/* Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) - -/* Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS BIT(7) - -/* 0--from PLL, 1--from oscillator */ -#define SHIM_CLKCTL_HDCS BIT(4) - -/* Oscillator select */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/* HP memory clock PLL divisor */ -#define SHIM_CLKCTL_HPMPCS BIT(0) - -/** \brief Mask for requesting clock - */ -#define SHIM_CLKCTL_OSC_REQUEST_MASK \ - (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ - SHIM_CLKCTL_RLROSCC) - -/** \brief Mask for setting previously requested clock - */ -#define SHIM_CLKCTL_OSC_SOURCE_MASK \ - (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ - SHIM_CLKCTL_HMCS_DIV4) - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) -#define SHIM_PWRCTL_TCPCTLPG BIT(4) - -#define SHIM_PWRSTS 0x92 - -#define SHIM_LPSCTL 0x94 -#define SHIM_LPSCTL_BID BIT(7) -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_BATTR_0 BIT(12) - /** \brief GPDMA shim registers Control */ -#define SHIM_GPDMA_BASE_OFFSET 0x6500 -#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) +#define SHIM_GPDMA_BASE_OFFSET 0x6500 +#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) /** \brief GPDMA Clock Control */ -#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) +#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) /* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ -#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) +#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(7) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) - -/* I2S SHIM Registers */ -#define I2SLCTL 0x71C04 - -/* SPA register should be set for each I2S port and DSP should - * wait for CPA to be set - */ -#define I2SLCTL_SPA(x) BIT(0 + x) -#define I2SLCTL_CPA(x) BIT(8 + x) - -#define L2LMCAP 0x71D00 -#define L2MPAT 0x71D04 - -#define HSPGCTL0 0x71D10 -#define HSRMCTL0 0x71D14 -#define HSPGISTS0 0x71D18 - -#define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) -#define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) +#define HSPGCTL0 0x71D10 +#define HSRMCTL0 0x71D14 +#define HSPGISTS0 0x71D18 #define HSPGCTL1 0x71D20 #define HSRMCTL1 0x71D24 @@ -239,39 +36,14 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16)) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - #define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) #define LPGPDMA_CTLOSEL_FLAG BIT(15) #define LPGPDMA_CHOSEL_FLAG 0xFF -#define DSP_INIT_IOPO 0x71A68 -#define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG GENMASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) - #define DSP_INIT_GENO 0x71A6C #define GENO_MDIVOSEL BIT(1) #define GENO_DIOPTOSEL BIT(2) -#define DSP_INIT_ALHO 0x71A70 -#define ALHO_ASO_FLAG BIT(0) -#define ALHO_CSO_FLAG BIT(1) -#define ALHO_CFO_FLAG BIT(2) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - /* host windows */ #define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) #define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) @@ -279,10 +51,4 @@ #define DMWBA_ENABLE BIT(0) #define DMWBA_READONLY BIT(1) -/* DMIC power ON bit */ -#define DMICLCTL_SPA ((uint32_t) BIT(0)) - -/* DMIC disable clock gating */ -#define DMIC_DCGD ((uint32_t) BIT(30)) - #endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S index 6c6b66c9b5c..3715518863a 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_entry.S @@ -13,12 +13,18 @@ * 2) Stack is in first HPSRAM bank. */ +#include #include +#include #include #include #include #include +#define SHIM_ADDR DT_REG_ADDR(DT_NODELABEL(shim)) +#define SHIM_L2_MECS (SHIM_ADDR + 0xd0) +#define SHIM_L2_PREF_CFG (SHIM_ADDR + 0x508) + .type boot_master_core, @function .begin literal_prefix .boot_entry @@ -66,7 +72,7 @@ wnd0_error_address: #if defined(PLATFORM_MEM_INIT_AT_BOOT) shim_ldoctl_address: - .word SHIM_BASE + SHIM_LDOCTL + .word (SHIM_ADDR + 0xa4) ldoctl_hpsram_ldo_on: .word SHIM_LDOCTL_HPSRAM_LDO_ON diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index 6e94988ff8d..beabbd224ee 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -6,6 +6,7 @@ * Author: Liam Girdwood */ +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include "manifest.h" #if CONFIG_SOC_INTEL_S1000 @@ -191,7 +193,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks) uint32_t ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1; uint32_t total_banks_count = PLATFORM_HPSRAM_EBB_COUNT; - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON); + CAVS_SHIM.ldoctl = SHIM_LDOCTL_HPSRAM_LDO_ON; /* add some delay before touch power register */ idelay(delay_count); @@ -245,7 +247,7 @@ static int32_t hp_sram_pm_banks(uint32_t banks) /* add some delay before touch power register */ idelay(delay_count); - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS); + CAVS_SHIM.ldoctl = SHIM_LDOCTL_HPSRAM_LDO_BYPASS; return 0; } @@ -293,19 +295,17 @@ static uint32_t hp_sram_init(void) static int32_t lp_sram_init(void) { - uint32_t status; - uint32_t lspgctl_value; + uint32_t status = 0; uint32_t timeout_counter, delay_count = 256; timeout_counter = delay_count; - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON); + CAVS_SHIM.ldoctl = SHIM_LDOCTL_LPSRAM_LDO_ON; /* add some delay before writing power registers */ idelay(delay_count); - lspgctl_value = io_reg_read(LSPGISTS); - io_reg_write(LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0)); + CAVS_SHIM.lspgctl = CAVS_SHIM.lspgists & ~LPSRAM_MASK(0); /* add some delay before checking the status */ idelay(delay_count); @@ -313,16 +313,15 @@ static int32_t lp_sram_init(void) /* query the power status of first part of LP memory */ /* to check whether it has been powered up. A few */ /* cycles are needed for it to be powered up */ - status = io_reg_read(LSPGISTS); - while (status) { + while (CAVS_SHIM.lspgists) { if (!timeout_counter--) { + status = 1; break; } idelay(delay_count); - status = io_reg_read(LSPGISTS); } - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_BYPASS); + CAVS_SHIM.ldoctl = SHIM_LDOCTL_LPSRAM_LDO_BYPASS; return status; } diff --git a/soc/xtensa/intel_adsp/common/include/adsp/io.h b/soc/xtensa/intel_adsp/common/include/adsp/io.h index 727fa037212..c5b92de7339 100644 --- a/soc/xtensa/intel_adsp/common/include/adsp/io.h +++ b/soc/xtensa/intel_adsp/common/include/adsp/io.h @@ -25,41 +25,4 @@ static inline void io_reg_write(uint32_t reg, uint32_t val) sys_write32(val, reg); } -static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, - uint32_t value) -{ - io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); -} - -static inline uint16_t io_reg_read16(uint32_t reg) -{ - return sys_read16(reg); -} - -static inline void io_reg_write16(uint32_t reg, uint16_t val) -{ - /* Note: Parameters in different order */ - sys_write16(val, reg); -} - -static inline uint32_t shim_read(uint32_t reg) -{ - return sys_read32(SHIM_BASE + reg); -} - -static inline void shim_write(uint32_t reg, uint32_t val) -{ - sys_write32(val, (SHIM_BASE + reg)); -} - -static inline uint64_t shim_read64(uint32_t reg) -{ - return *((volatile uint64_t*)(SHIM_BASE + reg)); -} - -static inline void shim_write64(uint32_t reg, uint64_t val) -{ - *((volatile uint64_t*)(SHIM_BASE + reg)) = val; -} - #endif diff --git a/soc/xtensa/intel_adsp/common/include/cavs-shim.h b/soc/xtensa/intel_adsp/common/include/cavs-shim.h new file mode 100644 index 00000000000..141dc4dbde7 --- /dev/null +++ b/soc/xtensa/intel_adsp/common/include/cavs-shim.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ +#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ + +/* The "shim" block contains most of the general system control + * registers on cAVS platforms. While the base address changes, it + * has remained largely, but not perfectly, compatible between + * versions. + */ + +#ifndef _ASMLANGUAGE +struct cavs_shim { + uint32_t skuid; + uint32_t _unused0[7]; + uint32_t dspwc_lo; + uint32_t dspwc_hi; + uint32_t dspwctcs; + uint32_t _unused1[1]; + uint32_t dspwct0c_lo; + uint32_t dspwct0c_hi; + uint32_t dspwct1c_lo; + uint32_t dspwct1c_hi; + uint32_t _unused2[14]; + uint32_t clkctl; + uint32_t clksts; + uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ + uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ + uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ + uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */ + uint16_t pwrctl; + uint16_t pwrsts; + uint32_t lpsctl; + uint32_t lpsdmas0; + uint32_t lpsdmas1; + uint32_t spsreq; + uint32_t ldoctl; + uint32_t _unused3[2]; + union { + /* cAVS 1.5 */ + struct { + uint32_t hspgists; + uint32_t lspgists; + uint32_t _unused4[2]; + }; + /* cAVS 1.8+ */ + struct { + uint32_t lpsalhss0; + uint32_t lpsalhss1; + uint32_t lpsalhss2; + uint32_t lpsalhss3; + }; + }; + uint32_t _unused5[4]; + uint32_t l2mecs; + uint32_t l2mpat; + uint32_t _unused6[2]; + uint32_t ltrc; + uint32_t _unused8[3]; + uint32_t dbgo; + uint32_t svcfg; + uint32_t _unused9[2]; +}; +#endif /* _ASMLANGUAGE */ + +#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) + +/* cAVS 1.8+ CLKCTL bits */ +#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */ +#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */ +#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */ +#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/ +#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */ +#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */ +#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */ +#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */ +#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */ + +/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */ +#define CAVS15_CLKCTL_RAPLLC BIT(31) +#define CAVS15_CLKCTL_RFROSCC BIT(29) +#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28) +#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x) +#define CAVS15_CLKCTL_SLIMFDCGB BIT(25) +#define CAVS15_CLKCTL_DMICFDCGB BIT(24) +#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x) +#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x) +#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */ +#define CAVS15_CLKCTL_TCPAPLLS BIT(7) +#define CAVS15_CLKCTL_LDCS BIT(5) +#define CAVS15_CLKCTL_HDCS BIT(4) +#define CAVS15_CLKCTL_LDOCS BIT(3) +#define CAVS15_CLKCTL_HDOCS BIT(2) +#define CAVS15_CLKCTL_LMPCS BIT(1) +#define CAVS15_CLKCTL_HMPCS BIT(0) + +#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) + +#ifdef SOC_SERIES_INTEL_CAVS_V25 +# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) +# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16) +#else +# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) +# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) +#endif +#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) +#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) + +#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */ diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/xtensa/intel_adsp/common/include/soc.h index 3430ee0fd76..f0e4b0ee24c 100644 --- a/soc/xtensa/intel_adsp/common/include/soc.h +++ b/soc/xtensa/intel_adsp/common/include/soc.h @@ -65,13 +65,6 @@ #define PDM_BASE DMIC_BASE -/* SOC DSP SHIM Registers */ -#if CAVS_VERSION == CAVS_VERSION_1_5 -#define SOC_DSP_SHIM_REG_BASE 0x00001000 -#else -#define SOC_DSP_SHIM_REG_BASE 0x00071f00 -#endif - /* DSP Wall Clock Timers (0 and 1) */ #define DSP_WCT_IRQ(x) \ SOC_AGGREGATE_IRQ((22 + x), CAVS_L2_AGG_INT_LEVEL2) @@ -79,43 +72,6 @@ #define DSP_WCT_CS_TA(x) BIT(x) #define DSP_WCT_CS_TT(x) BIT(4 + x) -struct soc_dsp_shim_regs { - uint32_t reserved[8]; - union { - struct { - uint32_t walclk32_lo; - uint32_t walclk32_hi; - }; - uint64_t walclk; - }; - uint32_t dspwctcs; - uint32_t reserved1[1]; - union { - struct { - uint32_t dspwct0c32_lo; - uint32_t dspwct0c32_hi; - }; - uint64_t dspwct0c; - }; - union { - struct { - uint32_t dspwct1c32_lo; - uint32_t dspwct1c32_hi; - }; - uint64_t dspwct1c; - }; - uint32_t reserved2[14]; - uint32_t clkctl; - uint32_t clksts; - uint32_t reserved3[4]; - uint16_t pwrctl; - uint16_t pwrsts; - uint32_t lpsctl; - uint32_t lpsdmas0; - uint32_t lpsdmas1; - uint32_t reserved4[22]; -}; - extern void z_soc_irq_enable(uint32_t irq); extern void z_soc_irq_disable(uint32_t irq); extern int z_soc_irq_is_enabled(unsigned int irq); diff --git a/soc/xtensa/intel_adsp/common/soc.c b/soc/xtensa/intel_adsp/common/soc.c index 7701509823a..e0e80f045ea 100644 --- a/soc/xtensa/intel_adsp/common/soc.c +++ b/soc/xtensa/intel_adsp/common/soc.c @@ -11,6 +11,7 @@ #include #include +#include #include #include "soc.h" @@ -194,12 +195,7 @@ irq_connect_out: static void power_init_v15(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15 - volatile struct soc_dsp_shim_regs *dsp_shim_regs = - (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE; - - /* - * HP domain clocked by PLL + /* HP domain clocked by PLL * LP domain clocked by PLL * DSP Core 0 PLL Clock Select divide by 1 * DSP Core 1 PLL Clock Select divide by 1 @@ -210,60 +206,43 @@ static void power_init_v15(void) * Disable Tensilica Core Prevent Local Clock Gating (Core 1) * - Disabling "prevent clock gating" means allowing clock gating */ - dsp_shim_regs->clkctl = - SHIM_CLKCTL_HDCS_PLL | - SHIM_CLKCTL_LDCS_PLL | - SHIM_CLKCTL_DPCS_DIV1(0) | - SHIM_CLKCTL_DPCS_DIV1(1) | - SHIM_CLKCTL_HPMPCS_DIV2 | - SHIM_CLKCTL_LPMPCS_DIV4 | - SHIM_CLKCTL_TCPAPLLS_DIS | - SHIM_CLKCTL_TCPLCG_DIS(0) | - SHIM_CLKCTL_TCPLCG_DIS(1); + CAVS_SHIM.clkctl = CAVS15_CLKCTL_LMPCS; /* Rewrite the low power sequencing control bits */ - dsp_shim_regs->lpsctl = dsp_shim_regs->lpsctl; -#endif + CAVS_SHIM.lpsctl = CAVS_SHIM.lpsctl; } static void power_init(void) { -#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15 - volatile struct soc_dsp_shim_regs *dsp_shim_regs = - (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE; - - /* - * Request HP ring oscillator and + /* Request HP ring oscillator and * wait for status to indicate it's ready. */ - dsp_shim_regs->clkctl |= SHIM_CLKCTL_RHROSCC; - while ((dsp_shim_regs->clkctl & SHIM_CLKCTL_RHROSCC) != - SHIM_CLKCTL_RHROSCC) { + CAVS_SHIM.clkctl |= CAVS_CLKCTL_RHROSCC; + while ((CAVS_SHIM.clkctl & CAVS_CLKCTL_RHROSCC) != CAVS_CLKCTL_RHROSCC) { k_busy_wait(10); } - /* - * Request HP Ring Oscillator + /* Request HP Ring Oscillator * Select HP Ring Oscillator * High Power Domain PLL Clock Select device by 2 * Low Power Domain PLL Clock Select device by 4 * Disable Tensilica Core(s) Prevent Local Clock Gating * - Disabling "prevent clock gating" means allowing clock gating */ - dsp_shim_regs->clkctl = - SHIM_CLKCTL_RHROSCC | - SHIM_CLKCTL_OCS_HP_RING | - SHIM_CLKCTL_HMCS_DIV2 | - SHIM_CLKCTL_LMCS_DIV4 | - SHIM_CLKCTL_TCPLCG_DIS_ALL; + CAVS_SHIM.clkctl = (CAVS_CLKCTL_RHROSCC | + CAVS_CLKCTL_OCS | + CAVS_CLKCTL_LMCS); +#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15 /* Prevent LP GPDMA 0 & 1 clock gating */ sys_write32(SHIM_CLKCTL_LPGPDMAFDCGB, SHIM_GPDMA_CLKCTL(0)); sys_write32(SHIM_CLKCTL_LPGPDMAFDCGB, SHIM_GPDMA_CLKCTL(1)); +#endif /* Disable power gating for first cores */ - dsp_shim_regs->pwrctl |= SHIM_PWRCTL_TCPDSPPG(0); + CAVS_SHIM.pwrctl |= SHIM_PWRCTL_TCPDSPPG(0); +#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15 /* On cAVS 1.8+, we must demand ownership of the timestamping * and clock generator registers. Lacking the former will * prevent wall clock timer interrupts from arriving, even diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 48b8616034f..262c0e93c10 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -23,6 +23,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL); #include #include +#include #include #include @@ -306,11 +307,9 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, * turn itself off when it gets to the WAITI instruction in * the idle thread. */ - volatile struct soc_dsp_shim_regs *shim = (void *)SOC_DSP_SHIM_REG_BASE; - - shim->pwrctl |= BIT(cpu_num); + CAVS_SHIM.pwrctl |= BIT(cpu_num); if (!IS_ENABLED(CONFIG_SOC_SERIES_INTEL_CAVS_V15)) { - shim->clkctl |= BIT(16 + cpu_num); + CAVS_SHIM.clkctl |= BIT(16 + cpu_num); } /* Send power up message to the other core */ @@ -437,7 +436,6 @@ void soc_idc_init(void) */ int soc_relaunch_cpu(int id) { - volatile struct soc_dsp_shim_regs *shim = (void *)SOC_DSP_SHIM_REG_BASE; int ret = 0; k_spinlock_key_t k = k_spin_lock(&mplock); @@ -446,7 +444,7 @@ int soc_relaunch_cpu(int id) goto out; } - if (shim->pwrsts & BIT(id)) { + if (CAVS_SHIM.pwrsts & BIT(id)) { ret = -EINVAL; goto out; } @@ -477,7 +475,6 @@ int soc_relaunch_cpu(int id) */ int soc_halt_cpu(int id) { - volatile struct soc_dsp_shim_regs *shim = (void *)SOC_DSP_SHIM_REG_BASE; int ret = 0; k_spinlock_key_t k = k_spin_lock(&mplock); @@ -491,11 +488,11 @@ int soc_halt_cpu(int id) * be woken up by scheduler IPIs */ CAVS_INTCTRL[id].l2.set = CAVS_L2_IDC; - shim->pwrctl &= ~BIT(id); - shim->clkctl &= ~BIT(16 + id); + CAVS_SHIM.pwrctl &= ~BIT(id); + CAVS_SHIM.clkctl &= ~BIT(16 + id); /* Wait for the CPU to reach an idle state before returing */ - while (shim->pwrsts & BIT(id)) { + while (CAVS_SHIM.pwrsts & BIT(id)) { } out: