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xtensa: specify which SR to store pointer to _kernel.cpu struct

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This allows Kconfig to specify which special register is being
used to store the pointer to the _kernel.cpu struct.
Since the SoC itself is highly configurable, sometimes MISC0 is not
available. So this adds the ability to use other special registers.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2018-10-19 09:22:47 -07:00 • committed by Anas Nashif
commit ecfc1b4ec1
3 changed files with 21 additions and 4 deletions
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7
arch/xtensa/Kconfig
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@ -89,4 +89,11 @@ config XTENSA_USE_CORE_CRT1
SoC or boards might define their own __start by setting this setting SoC or boards might define their own __start by setting this setting
to false. to false.
config XTENSA_KERNEL_CPU_PTR_SR
string
default "MISC0"
help
Specify which special register to store the pointer to
_kernel.cpus[] for the current CPU.
endmenu endmenu

2
arch/xtensa/core/xtensa-asm2-util.S
View file

@ -236,7 +236,7 @@ _switch_restore_pc:
*/ */
.align 4 .align 4
_handle_excint: _handle_excint:
EXCINT_HANDLER MISC0, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET EXCINT_HANDLER CONFIG_XTENSA_KERNEL_CPU_PTR_SR, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
/* Define the actual vectors for the hardware-defined levels with /* Define the actual vectors for the hardware-defined levels with
* DEF_EXCINT. These load a C handler address and jump to our handler * DEF_EXCINT. These load a C handler address and jump to our handler

16
arch/xtensa/include/kernel_arch_func.h
View file

@ -11,6 +11,7 @@
#ifndef _ASMLANGUAGE #ifndef _ASMLANGUAGE
#include <string.h> #include <string.h>
#include <stdbool.h>
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -21,6 +22,16 @@ extern "C" {
#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE) #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE) #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
#define RSR(sr) \
({u32_t v; \
__asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
v; })
#define WSR(sr, v) \
do { \
__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
} while (false)
extern void FatalErrorHandler(void); extern void FatalErrorHandler(void);
extern void ReservedInterruptHandler(unsigned int intNo); extern void ReservedInterruptHandler(unsigned int intNo);
@ -34,7 +45,7 @@ static ALWAYS_INLINE _cpu_t *_arch_curr_cpu(void)
#ifdef CONFIG_XTENSA_ASM2 #ifdef CONFIG_XTENSA_ASM2
void *val; void *val;
__asm__ volatile("rsr.misc0 %0" : "=r"(val)); val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
return val; return val;
#else #else
@ -68,8 +79,7 @@ static ALWAYS_INLINE void kernel_arch_init(void)
* this record is a per-CPU thing and having it stored in a SR * this record is a per-CPU thing and having it stored in a SR
* already is a big win. * already is a big win.
*/ */
__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(cpu0)); WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0);
#endif #endif
#if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0 #if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0