diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 696169a90e6..042a9bfbade 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -89,4 +89,11 @@ config XTENSA_USE_CORE_CRT1
 	  SoC or boards might define their own __start by setting this setting
 	  to false.
 
+config XTENSA_KERNEL_CPU_PTR_SR
+	string
+	default "MISC0"
+	help
+	  Specify which special register to store the pointer to
+	  _kernel.cpus[] for the current CPU.
+
 endmenu
diff --git a/arch/xtensa/core/xtensa-asm2-util.S b/arch/xtensa/core/xtensa-asm2-util.S
index df783844b24..c12a498b0cd 100644
--- a/arch/xtensa/core/xtensa-asm2-util.S
+++ b/arch/xtensa/core/xtensa-asm2-util.S
@@ -236,7 +236,7 @@ _switch_restore_pc:
  */
 .align 4
 _handle_excint:
-	EXCINT_HANDLER MISC0, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
+	EXCINT_HANDLER CONFIG_XTENSA_KERNEL_CPU_PTR_SR, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
 
 /* Define the actual vectors for the hardware-defined levels with
  * DEF_EXCINT.  These load a C handler address and jump to our handler
diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h
index 59484afec1f..04c07dfde03 100644
--- a/arch/xtensa/include/kernel_arch_func.h
+++ b/arch/xtensa/include/kernel_arch_func.h
@@ -11,6 +11,7 @@
 
 #ifndef _ASMLANGUAGE
 #include <string.h>
+#include <stdbool.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -21,6 +22,16 @@ extern "C" {
 #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
 #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
 
+#define RSR(sr) \
+	({u32_t v; \
+	 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
+	 v; })
+
+#define WSR(sr, v) \
+	do { \
+		__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
+	} while (false)
+
 extern void FatalErrorHandler(void);
 extern void ReservedInterruptHandler(unsigned int intNo);
 
@@ -34,7 +45,7 @@ static ALWAYS_INLINE _cpu_t *_arch_curr_cpu(void)
 #ifdef CONFIG_XTENSA_ASM2
 	void *val;
 
-	__asm__ volatile("rsr.misc0 %0" : "=r"(val));
+	val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
 
 	return val;
 #else
@@ -68,8 +79,7 @@ static ALWAYS_INLINE void kernel_arch_init(void)
 	 * this record is a per-CPU thing and having it stored in a SR
 	 * already is a big win.
 	 */
-	__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(cpu0));
-
+	WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0);
 #endif
 
 #if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0