drivers: mcux_gpt_timer: Enabled GPT timer on MIMXRT1064 EVK

This enables the GPT timer for use as a hardware clock on the
MIMXRT1064. The timer will be disabled when builds use the GPT timer as
a counter, and the build will fall back to using the Cortex M systick as
a timer. This was tested using the kernel tickless test, to verify the
driver functions as expected.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2021-10-14 09:24:30 -05:00 committed by Christopher Friedt
commit e99eb6bb70
5 changed files with 25 additions and 4 deletions

View file

@ -124,6 +124,8 @@ features:
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| SPI | on-chip | spi | | SPI | on-chip | spi |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma | | DMA | on-chip | dma |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| HWINFO | on-chip | Unique device serial number | | HWINFO | on-chip | Unique device serial number |
@ -277,8 +279,8 @@ The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.
System Clock System Clock
============ ============
The MIMXRT1064 SoC is configured to use the 24 MHz external oscillator on the The MIMXRT1064 SoC is configured to use the 32 KHz low frequency oscillator on
board with the on-chip PLL to generate a 600 MHz core clock. the board as a source for the GPT timer to generate a system clock.
Serial Port Serial Port
=========== ===========

View file

@ -266,3 +266,10 @@ zephyr_udc0: &usb1 {
&adc1 { &adc1 {
status = "okay"; status = "okay";
}; };
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
* to use systick, change this node from "gpt_hw_timer" to "systick"
*/
&gpt_hw_timer {
status = "okay";
};

View file

@ -9,8 +9,6 @@ CONFIG_SOC_SERIES_IMX_RT=y
CONFIG_CONSOLE=y CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y CONFIG_GPIO=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000
CONFIG_ARM_MPU=y CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y CONFIG_HW_STACK_PROTECTION=y

View file

@ -23,4 +23,7 @@ config IPG_DIV
config GPIO config GPIO
default y default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 600000000 if CORTEX_M_SYSTICK
endif # SOC_MIMXRT1064 endif # SOC_MIMXRT1064

View file

@ -198,6 +198,17 @@ config TEST_EXTRA_STACKSIZE
default 1024 default 1024
endif # MBEDTLS endif # MBEDTLS
if MCUX_GPT_TIMER
# set the tick per sec as a divider of the GPT clock source
config SYS_CLOCK_TICKS_PER_SEC
default 8192
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32786
endif #MCUX_GPT_TIMER
source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*" source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"
endif # SOC_SERIES_IMX_RT endif # SOC_SERIES_IMX_RT