From e6a1dc9674a7618054fa6838f2064a94c059d519 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 1 Apr 2020 17:33:01 -0500 Subject: [PATCH] soc: arm: nxp_imx: Convert from Kconfig to DT_NODELABEL As prep for drivers being converted to utilize DT_INST and removal of per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL instead. Signed-off-by: Kumar Gala --- include/dt-bindings/rdc/imx_rdc.h | 2 + soc/arm/nxp_imx/mcimx6x_m4/soc.c | 100 +++++++++++++++--------------- soc/arm/nxp_imx/mcimx7_m4/soc.c | 80 ++++++++++++------------ 3 files changed, 92 insertions(+), 90 deletions(-) diff --git a/include/dt-bindings/rdc/imx_rdc.h b/include/dt-bindings/rdc/imx_rdc.h index 1fb4c35dd79..be8c6aa8eda 100644 --- a/include/dt-bindings/rdc/imx_rdc.h +++ b/include/dt-bindings/rdc/imx_rdc.h @@ -18,4 +18,6 @@ #define RDC_DOMAIN_PERM(domain, perm) (perm << (domain * 2)) +#define RDC_DT_VAL(nodelabel) DT_PROP(DT_NODELABEL(nodelabel), rdc) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ */ diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c index 2a502cdfb95..d5a543d6856 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c +++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c @@ -21,72 +21,72 @@ static void SOC_RdcInit(void) RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW), false, false); -#ifdef CONFIG_UART_IMX_UART_1 +#if DT_HAS_NODE(DT_NODELABEL(uart1)) /* Set access to UART_1 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart1, DT_NXP_IMX_UART_UART_1_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_1 */ -#ifdef CONFIG_UART_IMX_UART_2 + RDC_SetPdapAccess(RDC, rdcPdapUart1, RDC_DT_VAL(uart1), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(uart2)) /* Set access to UART_2 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart2, DT_NXP_IMX_UART_UART_2_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_2 */ -#ifdef CONFIG_UART_IMX_UART_3 + RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(uart3)) /* Set access to UART_3 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart3, DT_NXP_IMX_UART_UART_3_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_3 */ -#ifdef CONFIG_UART_IMX_UART_4 + RDC_SetPdapAccess(RDC, rdcPdapUart3, RDC_DT_VAL(uart3), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(uart4)) /* Set access to UART_4 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart4, DT_NXP_IMX_UART_UART_4_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_4 */ -#ifdef CONFIG_UART_IMX_UART_5 + RDC_SetPdapAccess(RDC, rdcPdapUart4, RDC_DT_VAL(uart4), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(uart5)) /* Set access to UART_5 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart5, DT_NXP_IMX_UART_UART_5_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_5 */ -#ifdef CONFIG_UART_IMX_UART_6 + RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(uart6)) /* Set access to UART_6 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapUart6, DT_NXP_IMX_UART_UART_6_RDC, false, false); -#endif /* CONFIG_UART_IMX_UART_6 */ -#ifdef CONFIG_GPIO_IMX_PORT_1 + RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio1)) /* Set access to GPIO_1 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio1, DT_NXP_IMX_GPIO_GPIO_1_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_1 */ -#ifdef CONFIG_GPIO_IMX_PORT_2 + RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio2)) /* Set access to GPIO_2 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio2, DT_NXP_IMX_GPIO_GPIO_2_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_2 */ -#ifdef CONFIG_GPIO_IMX_PORT_3 + RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio3)) /* Set access to GPIO_3 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio3, DT_NXP_IMX_GPIO_GPIO_3_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_3 */ -#ifdef CONFIG_GPIO_IMX_PORT_4 + RDC_SetPdapAccess(RDC, rdcPdapGpio3, RDC_DT_VAL(gpio3), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio4)) /* Set access to GPIO_4 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio4, DT_NXP_IMX_GPIO_GPIO_4_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_4 */ -#ifdef CONFIG_GPIO_IMX_PORT_5 + RDC_SetPdapAccess(RDC, rdcPdapGpio4, RDC_DT_VAL(gpio4), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio5)) /* Set access to GPIO_5 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio5, DT_NXP_IMX_GPIO_GPIO_5_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_5 */ -#ifdef CONFIG_GPIO_IMX_PORT_6 + RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio6)) /* Set access to GPIO_6 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio6, DT_NXP_IMX_GPIO_GPIO_6_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_6 */ -#ifdef CONFIG_GPIO_IMX_PORT_7 + RDC_SetPdapAccess(RDC, rdcPdapGpio6, RDC_DT_VAL(gpio6), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(gpio7)) /* Set access to GPIO_7 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapGpio7, DT_NXP_IMX_GPIO_GPIO_7_RDC, false, false); -#endif /* CONFIG_GPIO_IMX_PORT_7 */ + RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false); +#endif #ifdef CONFIG_IPM_IMX /* Set access to MU B for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapMuB, DT_NXP_IMX_MU_MU_B_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false); #endif /* CONFIG_IPM_IMX */ -#ifdef CONFIG_COUNTER_IMX_EPIT_1 +#if DT_HAS_NODE(DT_NODELABEL(epit1)) /* Set access to EPIT_1 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapEpit1, DT_NXP_IMX_EPIT_EPIT_1_RDC, false, false); -#endif /* CONFIG_COUNTER_IMX_EPIT_1 */ -#ifdef CONFIG_COUNTER_IMX_EPIT_2 + RDC_SetPdapAccess(RDC, rdcPdapEpit1, RDC_DT_VAL(epit1), false, false); +#endif +#if DT_HAS_NODE(DT_NODELABEL(epit2)) /* Set access to EPIT_2 for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapEpit2, DT_NXP_IMX_EPIT_EPIT_2_RDC, false, false); -#endif /* CONFIG_COUNTER_IMX_EPIT_2 */ + RDC_SetPdapAccess(RDC, rdcPdapEpit2, RDC_DT_VAL(epit2), false, false); +#endif } /* Initialize cache. */ @@ -151,12 +151,12 @@ static void SOC_ClockInit(void) CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0); /* Enable EPIT clocks */ -#ifdef CONFIG_COUNTER_IMX_EPIT_1 +#if DT_HAS_NODE(DT_NODELABEL(epit1)) CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll); -#endif /* CONFIG_COUNTER_IMX_EPIT_1 */ -#ifdef CONFIG_COUNTER_IMX_EPIT_2 +#endif +#if DT_HAS_NODE(DT_NODELABEL(epit2)) CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll); -#endif /* CONFIG_COUNTER_IMX_EPIT_2 */ +#endif #endif /* CONFIG_COUNTER_IMX_EPIT */ } diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc.c b/soc/arm/nxp_imx/mcimx7_m4/soc.c index d232ef97ee0..f2739ecbe00 100644 --- a/soc/arm/nxp_imx/mcimx7_m4/soc.c +++ b/soc/arm/nxp_imx/mcimx7_m4/soc.c @@ -56,25 +56,25 @@ void SOC_RdcInit(void) static void nxp_mcimx7_gpio_config(void) { -#ifdef CONFIG_GPIO_IMX_PORT_1 - RDC_SetPdapAccess(RDC, rdcPdapGpio1, DT_NXP_IMX_GPIO_GPIO_1_RDC, false, false); +#if DT_HAS_NODE(DT_NODELABEL(gpio1)) + RDC_SetPdapAccess(RDC, rdcPdapGpio1, RDC_DT_VAL(gpio1), false, false); /* Enable gpio clock gate */ CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait); -#endif /* CONFIG_GPIO_IMX_PORT_1 */ +#endif -#ifdef CONFIG_GPIO_IMX_PORT_2 - RDC_SetPdapAccess(RDC, rdcPdapGpio2, DT_NXP_IMX_GPIO_GPIO_2_RDC, false, false); +#if DT_HAS_NODE(DT_NODELABEL(gpio2)) + RDC_SetPdapAccess(RDC, rdcPdapGpio2, RDC_DT_VAL(gpio2), false, false); /* Enable gpio clock gate */ CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait); -#endif /* CONFIG_GPIO_IMX_PORT_2 */ +#endif -#ifdef CONFIG_GPIO_IMX_PORT_7 - RDC_SetPdapAccess(RDC, rdcPdapGpio7, DT_NXP_IMX_GPIO_GPIO_7_RDC, false, false); +#if DT_HAS_NODE(DT_NODELABEL(gpio7)) + RDC_SetPdapAccess(RDC, rdcPdapGpio7, RDC_DT_VAL(gpio7), false, false); /* Enable gpio clock gate */ CCM_ControlGate(CCM, ccmCcgrGateGpio7, ccmClockNeededRunWait); -#endif /* CONFIG_GPIO_IMX_PORT_2 */ +#endif } #endif /* CONFIG_GPIO_IMX */ @@ -83,9 +83,9 @@ static void nxp_mcimx7_gpio_config(void) static void nxp_mcimx7_uart_config(void) { -#ifdef CONFIG_UART_IMX_UART_2 +#if DT_HAS_NODE(DT_NODELABEL(uart2)) /* We need to grasp board uart exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapUart2, DT_NXP_IMX_UART_UART_2_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapUart2, RDC_DT_VAL(uart2), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0); /* Enable uart clock */ @@ -96,11 +96,11 @@ static void nxp_mcimx7_uart_config(void) * So we need UART clock all the time */ CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll); -#endif /* #ifdef CONFIG_UART_IMX_UART_2 */ +#endif -#ifdef CONFIG_UART_IMX_UART_6 +#if DT_HAS_NODE(DT_NODELABEL(uart6)) /* We need to grasp board uart exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapUart6, DT_NXP_IMX_UART_UART_6_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapUart6, RDC_DT_VAL(uart6), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootUart6, ccmRootmuxUartOsc24m, 0, 0); /* Enable uart clock */ @@ -111,7 +111,7 @@ static void nxp_mcimx7_uart_config(void) * So we need UART clock all the time */ CCM_ControlGate(CCM, ccmCcgrGateUart6, ccmClockNeededAll); -#endif /* #ifdef CONFIG_UART_IMX_UART_6 */ +#endif } #endif /* CONFIG_UART_IMX */ @@ -120,45 +120,45 @@ static void nxp_mcimx7_uart_config(void) static void nxp_mcimx7_i2c_config(void) { -#ifdef CONFIG_I2C_1 +#if DT_HAS_NODE(DT_NODELABEL(i2c1)) /* In this example, we need to grasp board I2C exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapI2c1, DT_FSL_IMX7D_I2C_I2C_1_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapI2c1, RDC_DT_VAL(i2c1), false, false); /* Select I2C clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootI2c1, ccmRootmuxI2cOsc24m, 0, 0); /* Enable I2C clock */ CCM_EnableRoot(CCM, ccmRootI2c1); CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait); -#endif /* CONFIG_I2C_1 */ +#endif -#ifdef CONFIG_I2C_2 +#if DT_HAS_NODE(DT_NODELABEL(i2c2)) /* In this example, we need to grasp board I2C exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapI2c2, DT_FSL_IMX7D_I2C_I2C_2_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapI2c2, RDC_DT_VAL(i2c2), false, false); /* Select I2C clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootI2c2, ccmRootmuxI2cOsc24m, 0, 0); /* Enable I2C clock */ CCM_EnableRoot(CCM, ccmRootI2c2); CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait); -#endif /* CONFIG_I2C_2 */ +#endif -#ifdef CONFIG_I2C_3 +#if DT_HAS_NODE(DT_NODELABEL(i2c3)) /* In this example, we need to grasp board I2C exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapI2c3, DT_FSL_IMX7D_I2C_I2C_3_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapI2c3, RDC_DT_VAL(i2c3), false, false); /* Select I2C clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootI2c3, ccmRootmuxI2cOsc24m, 0, 0); /* Enable I2C clock */ CCM_EnableRoot(CCM, ccmRootI2c3); CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait); -#endif /* CONFIG_I2C_3 */ +#endif -#ifdef CONFIG_I2C_4 +#if DT_HAS_NODE(DT_NODELABEL(i2c4)) /* In this example, we need to grasp board I2C exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapI2c4, DT_FSL_IMX7D_I2C_I2C_4_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapI2c4, RDC_DT_VAL(i2c4), false, false); /* Select I2C clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootI2c4, ccmRootmuxI2cOsc24m, 0, 0); /* Enable I2C clock */ CCM_EnableRoot(CCM, ccmRootI2c4); CCM_ControlGate(CCM, ccmCcgrGateI2c4, ccmClockNeededRunWait); -#endif /* CONFIG_I2C_4 */ +#endif } #endif /* CONFIG_I2C_IMX */ @@ -167,45 +167,45 @@ static void nxp_mcimx7_i2c_config(void) static void nxp_mcimx7_pwm_config(void) { -#ifdef CONFIG_PWM_1 +#if DT_HAS_NODE(DT_NODELABEL(pwm1)) /* We need to grasp board pwm exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapPwm1, DT_FSL_IMX7D_PWM_PWM_1_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapPwm1, RDC_DT_VAL(pwm1), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootPwm1, ccmRootmuxPwmOsc24m, 0, 0); /* Enable pwm clock */ CCM_EnableRoot(CCM, ccmRootPwm1); CCM_ControlGate(CCM, ccmCcgrGatePwm1, ccmClockNeededAll); -#endif /* #ifdef CONFIG_PWM_1 */ +#endif -#ifdef CONFIG_PWM_2 +#if DT_HAS_NODE(DT_NODELABEL(pwm2)) /* We need to grasp board pwm exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapPwm2, DT_FSL_IMX7D_PWM_PWM_2_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapPwm2, RDC_DT_VAL(pwm2), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootPwm2, ccmRootmuxPwmOsc24m, 0, 0); /* Enable pwm clock */ CCM_EnableRoot(CCM, ccmRootPwm2); CCM_ControlGate(CCM, ccmCcgrGatePwm2, ccmClockNeededAll); -#endif /* #ifdef CONFIG_PWM_2 */ +#endif -#ifdef CONFIG_PWM_3 +#if DT_HAS_NODE(DT_NODELABEL(pwm3)) /* We need to grasp board pwm exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapPwm3, DT_FSL_IMX7D_PWM_PWM_3_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapPwm3, RDC_DT_VAL(pwm3), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootPwm3, ccmRootmuxPwmOsc24m, 0, 0); /* Enable pwm clock */ CCM_EnableRoot(CCM, ccmRootPwm3); CCM_ControlGate(CCM, ccmCcgrGatePwm3, ccmClockNeededAll); -#endif /* #ifdef CONFIG_PWM_3 */ +#endif -#ifdef CONFIG_PWM_4 +#if DT_HAS_NODE(DT_NODELABEL(pwm4)) /* We need to grasp board pwm exclusively */ - RDC_SetPdapAccess(RDC, rdcPdapPwm4, DT_FSL_IMX7D_PWM_PWM_4_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapPwm4, RDC_DT_VAL(pwm4), false, false); /* Select clock derived from OSC clock(24M) */ CCM_UpdateRoot(CCM, ccmRootPwm4, ccmRootmuxPwmOsc24m, 0, 0); /* Enable pwm clock */ CCM_EnableRoot(CCM, ccmRootPwm4); CCM_ControlGate(CCM, ccmCcgrGatePwm4, ccmClockNeededAll); -#endif /* #ifdef CONFIG_PWM_4 */ +#endif } #endif /* CONFIG_PWM_IMX */ @@ -214,7 +214,7 @@ static void nxp_mcimx7_pwm_config(void) static void nxp_mcimx7_mu_config(void) { /* Set access to MU B for M4 core */ - RDC_SetPdapAccess(RDC, rdcPdapMuB, DT_NXP_IMX_MU_MU_B_RDC, false, false); + RDC_SetPdapAccess(RDC, rdcPdapMuB, RDC_DT_VAL(mub), false, false); /* Enable clock gate for MU*/ CCM_ControlGate(CCM, ccmCcgrGateMu, ccmClockNeededRun);