michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: nxp_imx: rt: fix enet pll initialization config macro name

Browse source 
- Update config macro name for enet pll
- Update impacted defconfig of RT1052

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit is contained in:
Ryan QIAN 2019-01-09 14:01:41 +08:00 • committed by Maureen Helm
commit e66e6b054c
2 changed files with 6 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

3
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052
View file

@ -56,6 +56,9 @@ if NET_L2_ETHERNET
config ETH_MCUX config ETH_MCUX
def_bool y def_bool y
config INIT_ENET_PLL
def_bool y
endif # NET_L2_ETHERNET endif # NET_L2_ETHERNET

5
soc/arm/nxp_imx/rt/soc.c
View file

@ -34,7 +34,8 @@ const clock_usb_pll_config_t usb1PllConfig = {
}; };
#endif #endif
#ifdef CONFIG_ETH_MCUX_0 #ifdef CONFIG_INIT_ENET_PLL
/* ENET PLL configuration for RUN mode */
const clock_enet_pll_config_t ethPllConfig = { const clock_enet_pll_config_t ethPllConfig = {
.enableClkOutput = true, .enableClkOutput = true,
.enableClkOutput25M = false, .enableClkOutput25M = false,
@ -81,7 +82,7 @@ static ALWAYS_INLINE void clkInit(void)
#ifdef CONFIG_INIT_USB1_PLL #ifdef CONFIG_INIT_USB1_PLL
CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */ CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
#endif #endif
#ifdef CONFIG_ETH_MCUX_0 #ifdef CONFIG_INIT_ENET_PLL
CLOCK_InitEnetPll(&ethPllConfig); CLOCK_InitEnetPll(&ethPllConfig);
#endif #endif