soc: espressif: common: update to hal_espressif v5.1
Modify and reorganize SoC to meet updated hal. Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com> Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Carles Cufí
parent
fe57a12cf2
commit
e63ddb70b3
6 changed files with 723 additions and 213 deletions
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@ -1,215 +1,12 @@
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config ESPTOOLPY_FLASHFREQ_80M
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bool
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config FLASH_SIZE
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int
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config FLASH_BASE_ADDRESS
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hex
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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config ESP_SPIRAM
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bool "Support for external, SPI-connected RAM"
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help
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This enables support for an external SPI RAM chip, connected in
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parallel with the main SPI flash chip.
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config ESP_HEAP_MIN_EXTRAM_THRESHOLD
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int "Minimum threshold for external RAM allocation"
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default 8192
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range 1024 131072
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depends on ESP_SPIRAM
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help
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Threshold to decide if memory will be allocated from DRAM
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or SPIRAM. If value of allocation size is less than this value,
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memory will be allocated from internal RAM.
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config ESP_HEAP_SEARCH_ALL_REGIONS
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bool "Search for all available heap regions"
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depends on ESP_SPIRAM
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default y
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help
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This configuration enables searching all available heap
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regions. If the region of desired capability is exhausted,
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memory will be allocated from other available region.
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config ESP_SPIRAM_HEAP_SIZE
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int "Size of SPIRAM heap"
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default 262134 if SYS_HEAP_SMALL_ONLY
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default 1048576 if !SYS_HEAP_SMALL_ONLY
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depends on ESP_SPIRAM
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help
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Specify size of SPIRAM heap.
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menu "SPI RAM config"
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depends on ESP_SPIRAM
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choice SPIRAM_MODE
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prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
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default SPIRAM_MODE_QUAD
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config SPIRAM_MODE_QUAD
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bool "Quad Mode PSRAM"
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endchoice # SPIRAM_MODE
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choice SPIRAM_TYPE
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prompt "Type of SPI RAM chip in use"
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depends on ESP_SPIRAM
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default SPIRAM_TYPE_ESPPSRAM16
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config SPIRAM_TYPE_ESPPSRAM16
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bool "ESP-PSRAM16 or APS1604"
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config SPIRAM_TYPE_ESPPSRAM32
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bool "ESP-PSRAM32 or IS25WP032"
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config SPIRAM_TYPE_ESPPSRAM64
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bool "ESP-PSRAM64 or LY68L6400"
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endchoice # SPIRAM_TYPE
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config ESP_SPIRAM_SIZE
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int "Size of SPIRAM part"
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default 2097152 if SPIRAM_TYPE_ESPPSRAM16
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default 4194304 if SPIRAM_TYPE_ESPPSRAM32
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default 8388608 if SPIRAM_TYPE_ESPPSRAM64
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help
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Specify size of SPIRAM part.
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NOTE: If SPIRAM size is greater than 4MB, only
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lower 4MB can be allocated using k_malloc().
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choice SPIRAM_SPEED
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prompt "Set RAM clock speed"
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default SPIRAM_SPEED_40M
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help
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Select the speed for the SPI RAM chip.
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If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now:
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1. Flash SPI running at 40MHz and RAM SPI running at 40MHz
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2. Flash SPI running at 80MHz and RAM SPI running at 40MHz
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3. Flash SPI running at 80MHz and RAM SPI running at 80MHz
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Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host
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will be occupied by the system. Which SPI host to use can be selected by the config item
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SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The
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option to select 80MHz will only be visible if the flash SPI speed is also 80MHz.
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(ESPTOOLPY_FLASHFREQ_79M is true)
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config SPIRAM_SPEED_26M
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bool "26MHz clock speed"
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depends on SOC_SERIES_ESP32S2
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config SPIRAM_SPEED_20M
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bool "20MHz clock speed"
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depends on SOC_SERIES_ESP32S2
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config SPIRAM_SPEED_40M
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bool "40MHz clock speed"
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config SPIRAM_SPEED_80M
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depends on ESPTOOLPY_FLASHFREQ_80M
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bool "80MHz clock speed"
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config SPIRAM_SPEED_120M
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depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
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bool "120MHz clock speed"
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endchoice # SPIRAM_SPEED
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menu "PSRAM clock and cs IO for ESP32-DOWD"
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config D0WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 17
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help
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The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D0WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 16
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
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1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu # PSRAM clock and cs IO for ESP32-DOWD
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menu "PSRAM clock and cs IO for ESP32-D2WD"
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config D2WD_PSRAM_CLK_IO
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int "PSRAM CLK IO number"
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range 0 33
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default 9
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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config D2WD_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
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so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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endmenu # PSRAM clock and cs IO for ESP32-D2WD
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menu "PSRAM clock and cs IO for ESP32-PICO"
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config PICO_PSRAM_CS_IO
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int "PSRAM CS IO number"
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range 0 33
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default 10
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help
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The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
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For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
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IO.
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For the reference hardware design, please refer to
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https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
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endmenu # PSRAM clock and cs IO for ESP32-PICO
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config SPIRAM_CUSTOM_SPIWP_SD3_PIN
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bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
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default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5
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default n
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help
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This setting is only used if the SPI flash pins have been overridden by setting the eFuses
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SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
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When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
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ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
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mode, so a WP pin setting is necessary.
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If this config item is set to N (default), the correct WP pin will be automatically used for any
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Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
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to Y and specify the GPIO number connected to the WP pin.
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When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
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configured in the bootloader.
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config SPIRAM_SPIWP_SD3_PIN
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int "Custom SPI PSRAM WP(SD3) Pin"
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range 0 33
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default 7
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help
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The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
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If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
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value to the GPIO number of the SPIRAM WP pin.
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config SPIRAM
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bool
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default y
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endmenu # SPI RAM config
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endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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rsource "Kconfig.spiram"
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rsource "Kconfig.esptool"
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rsource "Kconfig.flash"
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@ -21,9 +21,6 @@ config ISR_STACK_SIZE
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config ATOMIC_OPERATIONS_C
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default y
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config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
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default n
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 16000000
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@ -33,7 +30,7 @@ config SYS_CLOCK_TICKS_PER_SEC
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config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE
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default n
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config CLOCK_CONTROL
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config SOC_FLASH_ESP32
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default y
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if BOOTLOADER_MCUBOOT
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@ -54,9 +51,6 @@ endif # BOOTLOADER_MCUBOOT
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endif # SOC_SERIES_ESP32C3
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# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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# Xtensa default options for ESP32 family
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@ -75,6 +69,9 @@ config GEN_IRQ_VECTOR_TABLE
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config CLOCK_CONTROL
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default y
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config SOC_FLASH_ESP32
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default y
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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218
soc/espressif/common/Kconfig.esptool
Normal file
218
soc/espressif/common/Kconfig.esptool
Normal file
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@ -0,0 +1,218 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_ESPRESSIF_ESP32
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config ESPTOOLPY_OCT_FLASH
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bool "Use Octal Flash"
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depends on SOC_SERIES_ESP32S3
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default n
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config ESPTOOLPY_FLASH_MODE_AUTO_DETECT
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depends on SOC_SERIES_ESP32S3
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bool "Choose flash mode automatically (please read help)"
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default y
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help
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This config option helps decide whether flash is Quad or Octal, but please note some limitations:
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1. If the flash chip is an Octal one, even if one of "QIO", "QOUT", "DIO", "DOUT" options is
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selected in `ESPTOOLPY_FLASHMODE`, our code will automatically change the
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mode to "OPI" and the sample mode will be STR.
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2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code will
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automatically change the mode to "DIO".
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3. Please do not rely on this option when you are pretty sure that you are using Octal flash,
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please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode
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in `ESPTOOLPY_FLASH_SAMPLE_MODE`. Otherwise, only `STR` mode is available.
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4. Enabling this feature reduces available internal RAM size (around 900 bytes).
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If your IRAM space is insufficient and you're aware of your flash type,
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disable this option and select corresponding flash type options.
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choice ESPTOOLPY_FLASHMODE
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prompt "Flash SPI mode"
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default ESPTOOLPY_FLASHMODE_DIO
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default ESPTOOLPY_FLASHMODE_OPI if ESPTOOLPY_OCT_FLASH
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help
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Mode the flash chip is flashed in, as well as the default mode for the
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binary to run in.
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config ESPTOOLPY_FLASHMODE_QIO
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bool "QIO"
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depends on !ESPTOOLPY_OCT_FLASH
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config ESPTOOLPY_FLASHMODE_QOUT
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bool "QOUT"
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depends on !ESPTOOLPY_OCT_FLASH
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config ESPTOOLPY_FLASHMODE_DIO
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bool "DIO"
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depends on !ESPTOOLPY_OCT_FLASH
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config ESPTOOLPY_FLASHMODE_DOUT
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bool "DOUT"
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depends on !ESPTOOLPY_OCT_FLASH
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config ESPTOOLPY_FLASHMODE_OPI
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bool "OPI"
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depends on ESPTOOLPY_OCT_FLASH
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endchoice # ESPTOOLPY_FLASHMODE
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choice ESPTOOLPY_FLASH_SAMPLE_MODE
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prompt "Flash Sampling Mode"
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default ESPTOOLPY_FLASH_SAMPLE_MODE_DTR if ESPTOOLPY_OCT_FLASH
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default ESPTOOLPY_FLASH_SAMPLE_MODE_STR if !ESPTOOLPY_OCT_FLASH
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config ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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bool "STR Mode"
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config ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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bool "DTR Mode"
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depends on ESPTOOLPY_OCT_FLASH
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endchoice # ESPTOOLPY_FLASH_SAMPLE_MODE
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config ESPTOOLPY_FLASHMODE
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string
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default "dio" if ESPTOOLPY_FLASHMODE_QIO
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default "dio" if ESPTOOLPY_FLASHMODE_QOUT
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default "dio" if ESPTOOLPY_FLASHMODE_DIO
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default "dout" if ESPTOOLPY_FLASHMODE_DOUT
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# The 1st and 2nd bootloader doesn't support opi mode,
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# using fastrd instead. For now the ESPTOOL doesn't support
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# fasted (see ESPTOOL-274), using dout instead. In ROM the flash mode
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# information get from efuse, so don't care this dout choice.
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default "dout" if ESPTOOLPY_FLASHMODE_OPI
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choice ESPTOOLPY_FLASHFREQ
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prompt "Flash SPI speed"
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default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32
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default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
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config ESPTOOLPY_FLASHFREQ_120M
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bool "120 MHz"
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select SPI_FLASH_HPM_ENABLE
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depends on SOC_SERIES_ESP32S3 && ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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help
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- Flash 120 MHz SDR mode is stable.
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- Flash 120 MHz DDR mode is an experimental feature, it works when
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the temperature is stable.
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Risks:
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If your chip powers on at a certain temperature, then after the temperature
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increases or decreases by approximately 20 Celsius degrees (depending on the
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chip), the program will crash randomly.
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config ESPTOOLPY_FLASHFREQ_80M
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bool "80 MHz"
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config ESPTOOLPY_FLASHFREQ_40M
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bool "40 MHz"
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config ESPTOOLPY_FLASHFREQ_26M
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bool "26 MHz"
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depends on !SOC_SERIES_ESP32S3
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config ESPTOOLPY_FLASHFREQ_20M
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bool "20 MHz"
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endchoice # ESPTOOLPY_FLASHFREQ
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config ESPTOOLPY_FLASHFREQ_80M_DEFAULT
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bool
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default y if SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
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help
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This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
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config ESPTOOLPY_FLASHFREQ
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string
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# On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m.
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# We currently define this to `80m`.
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default '80m' if ESPTOOLPY_FLASHFREQ_120M
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default '80m' if ESPTOOLPY_FLASHFREQ_80M
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default '40m' if ESPTOOLPY_FLASHFREQ_40M
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default '26m' if ESPTOOLPY_FLASHFREQ_26M
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default '20m' if ESPTOOLPY_FLASHFREQ_20M
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default '20m' # if no clock can match in bin headers, go with minimal.
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choice ESPTOOLPY_FLASHSIZE
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prompt "Flash size"
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default ESPTOOLPY_FLASHSIZE_2MB
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help
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SPI flash size, in megabytes
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config ESPTOOLPY_FLASHSIZE_1MB
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bool "1 MB"
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config ESPTOOLPY_FLASHSIZE_2MB
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bool "2 MB"
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config ESPTOOLPY_FLASHSIZE_4MB
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bool "4 MB"
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config ESPTOOLPY_FLASHSIZE_8MB
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bool "8 MB"
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config ESPTOOLPY_FLASHSIZE_16MB
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bool "16 MB"
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config ESPTOOLPY_FLASHSIZE_32MB
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bool "32 MB"
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config ESPTOOLPY_FLASHSIZE_64MB
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bool "64 MB"
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config ESPTOOLPY_FLASHSIZE_128MB
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bool "128 MB"
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endchoice
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config ESPTOOLPY_FLASHSIZE
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string
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default "1MB" if ESPTOOLPY_FLASHSIZE_1MB
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default "2MB" if ESPTOOLPY_FLASHSIZE_2MB
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default "4MB" if ESPTOOLPY_FLASHSIZE_4MB
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default "8MB" if ESPTOOLPY_FLASHSIZE_8MB
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default "16MB" if ESPTOOLPY_FLASHSIZE_16MB
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default "32MB" if ESPTOOLPY_FLASHSIZE_32MB
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default "64MB" if ESPTOOLPY_FLASHSIZE_64MB
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default "128MB" if ESPTOOLPY_FLASHSIZE_128MB
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config ESPTOOLPY_HEADER_FLASHSIZE_UPDATE
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bool "Detect flash size when flashing bootloader"
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default n
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help
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If this option is set, flashing the project will automatically detect
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the flash size of the target chip and update the bootloader image
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before it is flashed.
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Enabling this option turns off the image protection against corruption
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by a SHA256 digest. Updating the bootloader image before flashing would
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invalidate the digest.
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choice ESPTOOLPY_BEFORE
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prompt "Before flashing"
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default ESPTOOLPY_BEFORE_RESET
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help
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Configure whether esptool.py should reset the ESP32 before flashing.
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Automatic resetting depends on the RTS & DTR signals being
|
||||
wired from the serial port to the ESP32. Most USB development
|
||||
boards do this internally.
|
||||
|
||||
config ESPTOOLPY_BEFORE_RESET
|
||||
bool "Reset to bootloader"
|
||||
config ESPTOOLPY_BEFORE_NORESET
|
||||
bool "No reset"
|
||||
endchoice # ESPTOOLPY_BEFORE
|
||||
|
||||
config ESPTOOLPY_BEFORE
|
||||
string
|
||||
default "default_reset" if ESPTOOLPY_BEFORE_RESET
|
||||
default "no_reset" if ESPTOOLPY_BEFORE_NORESET
|
||||
|
||||
choice ESPTOOLPY_AFTER
|
||||
prompt "After flashing"
|
||||
default ESPTOOLPY_AFTER_RESET
|
||||
help
|
||||
Configure whether esptool.py should reset the ESP32 after flashing.
|
||||
|
||||
Automatic resetting depends on the RTS & DTR signals being
|
||||
wired from the serial port to the ESP32. Most USB development
|
||||
boards do this internally.
|
||||
|
||||
config ESPTOOLPY_AFTER_RESET
|
||||
bool "Reset after flashing"
|
||||
config ESPTOOLPY_AFTER_NORESET
|
||||
bool "Stay in bootloader"
|
||||
endchoice
|
||||
|
||||
config ESPTOOLPY_AFTER
|
||||
string
|
||||
default "hard_reset" if ESPTOOLPY_AFTER_RESET
|
||||
default "no_reset" if ESPTOOLPY_AFTER_NORESET
|
||||
|
||||
endif # SOC_FAMILY_ESPRESSIF_ESP32
|
||||
130
soc/espressif/common/Kconfig.flash
Normal file
130
soc/espressif/common/Kconfig.flash
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_FAMILY_ESPRESSIF_ESP32
|
||||
|
||||
config MMU_PAGE_SIZE
|
||||
hex
|
||||
default 0x10000
|
||||
|
||||
config SPI_FLASH_VENDOR_MXIC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SPI_FLASH_SUPPORT_ISSI_CHIP
|
||||
bool "ISSI"
|
||||
default y
|
||||
help
|
||||
Enable this to support auto detection of ISSI chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_SUPPORT_MXIC_CHIP
|
||||
bool "MXIC"
|
||||
default y
|
||||
help
|
||||
Enable this to support auto detection of MXIC chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_SUPPORT_GD_CHIP
|
||||
bool "GigaDevice"
|
||||
default y
|
||||
help
|
||||
Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
|
||||
directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
|
||||
modules, please don't disable this, otherwise your flash may not work in 4-bit
|
||||
mode.
|
||||
|
||||
This adds support for variant chips, however will extend detecting time and image
|
||||
size. Note that the default chip driver supports the GD chips with product ID
|
||||
60H.
|
||||
|
||||
config SPI_FLASH_SUPPORT_WINBOND_CHIP
|
||||
bool "Winbond"
|
||||
default y
|
||||
help
|
||||
Enable this to support auto detection of Winbond chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_SUPPORT_BOYA_CHIP
|
||||
bool "BOYA"
|
||||
default y if !SOC_SERIES_ESP32
|
||||
help
|
||||
Enable this to support auto detection of BOYA chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_SUPPORT_TH_CHIP
|
||||
bool "TH"
|
||||
default y if !SOC_SERIES_ESP32
|
||||
help
|
||||
Enable this to support auto detection of TH chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
|
||||
bool "mxic (opi)"
|
||||
depends on SOC_SERIES_ESP32S3
|
||||
default y
|
||||
help
|
||||
Enable this to support auto detection of Octal MXIC chips if chip vendor not directly
|
||||
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
||||
chips, however will extend detecting time.
|
||||
|
||||
config SPI_FLASH_ROM_DRIVER_PATCH
|
||||
bool "SPI flash ROM driver patched functions"
|
||||
default y
|
||||
help
|
||||
Enable this flag to use patched versions of SPI flash ROM driver functions.
|
||||
This option should be enabled, if any one of the following is true: (1) need to write
|
||||
to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main
|
||||
SPI flash chip is manufactured by ISSI.
|
||||
|
||||
config BOOTLOADER_FLASH_XMC_SUPPORT
|
||||
bool "Support flash chips of XMC (READ HELP FIRST)"
|
||||
default y
|
||||
help
|
||||
Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
|
||||
XMC chips will be forbidden to be used, when this option is disabled.
|
||||
|
||||
DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
|
||||
|
||||
choice BOOTLOADER_VDDSDIO_BOOST
|
||||
bool "VDDSDIO LDO voltage"
|
||||
default BOOTLOADER_VDDSDIO_BOOST_1_9V
|
||||
depends on !SOC_SERIES_ESP32C3
|
||||
help
|
||||
If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse
|
||||
or MTDI bootstrapping pin), bootloader will change LDO settings to
|
||||
output 1.9V instead. This helps prevent flash chip from browning out
|
||||
during flash programming operations.
|
||||
|
||||
This option has no effect if VDDSDIO is set to 3.3V, or if the internal
|
||||
VDDSDIO regulator is disabled via eFuse.
|
||||
|
||||
config BOOTLOADER_VDDSDIO_BOOST_1_8V
|
||||
bool "1.8V"
|
||||
depends on !ESPTOOLPY_FLASHFREQ_80M
|
||||
config BOOTLOADER_VDDSDIO_BOOST_1_9V
|
||||
bool "1.9V"
|
||||
endchoice
|
||||
|
||||
config BOOTLOADER_REGION_PROTECTION_ENABLE
|
||||
bool "Protect unmapped memory regions from unintended accesses"
|
||||
default y
|
||||
help
|
||||
Protects the unmapped memory regions of the entire address space from unintended accesses.
|
||||
This will ensure that an exception will be triggered whenever the CPU performs a memory
|
||||
operation on unmapped regions of the address space.
|
||||
|
||||
config SPI_FLASH_HPM_ENABLE
|
||||
bool
|
||||
depends on SOC_SERIES_ESP32S3
|
||||
default n
|
||||
help
|
||||
This option is invisible, and will be selected automatically
|
||||
when ``ESPTOOLPY_FLASHFREQ_120M`` is selected.
|
||||
|
||||
endif # SOC_FAMILY_ESPRESSIF_ESP32
|
||||
235
soc/espressif/common/Kconfig.spiram
Normal file
235
soc/espressif/common/Kconfig.spiram
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
|
||||
config ESP_SPIRAM
|
||||
bool "Support for external, SPI-connected RAM"
|
||||
default n if MCUBOOT
|
||||
help
|
||||
This enables support for an external SPI RAM chip, connected in
|
||||
parallel with the main SPI flash chip.
|
||||
|
||||
menu "SPI RAM config"
|
||||
depends on ESP_SPIRAM
|
||||
|
||||
config ESP_HEAP_MIN_EXTRAM_THRESHOLD
|
||||
int "Minimum threshold for external RAM allocation"
|
||||
default 8192
|
||||
range 1024 131072
|
||||
help
|
||||
Threshold to decide if memory will be allocated from DRAM
|
||||
or SPIRAM. If value of allocation size is less than this value,
|
||||
memory will be allocated from internal RAM.
|
||||
|
||||
config ESP_HEAP_SEARCH_ALL_REGIONS
|
||||
bool "Search for all available heap regions"
|
||||
default y
|
||||
help
|
||||
This configuration enables searching all available heap
|
||||
regions. If the region of desired capability is exhausted,
|
||||
memory will be allocated from other available region.
|
||||
|
||||
config ESP_SPIRAM_HEAP_SIZE
|
||||
int "Size of SPIRAM heap"
|
||||
default 262134 if SYS_HEAP_SMALL_ONLY
|
||||
default 1048576 if !SYS_HEAP_SMALL_ONLY
|
||||
help
|
||||
Specify size of SPIRAM heap.
|
||||
|
||||
choice SPIRAM_MODE
|
||||
prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
|
||||
default SPIRAM_MODE_QUAD
|
||||
|
||||
config SPIRAM_MODE_QUAD
|
||||
bool "Quad Mode PSRAM"
|
||||
|
||||
config SPIRAM_MODE_OCT
|
||||
bool "Octal Mode PSRAM"
|
||||
depends on SOC_SERIES_ESP32S3
|
||||
|
||||
endchoice # SPIRAM_MODE
|
||||
|
||||
choice SPIRAM_TYPE
|
||||
prompt "Type of SPI RAM chip in use"
|
||||
default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD
|
||||
default SPIRAM_TYPE_ESPPSRAM64
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM16
|
||||
bool "ESP-PSRAM16 or APS1604"
|
||||
depends on SPIRAM_MODE_QUAD
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM32
|
||||
bool "ESP-PSRAM32 or IS25WP032"
|
||||
depends on SPIRAM_MODE_QUAD
|
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM64
|
||||
bool "ESP-PSRAM64, LY68L6400 or APS6408"
|
||||
|
||||
endchoice # SPIRAM_TYPE
|
||||
|
||||
config ESP_SPIRAM_SIZE
|
||||
int "Size of SPIRAM part"
|
||||
default 2097152 if SPIRAM_TYPE_ESPPSRAM16
|
||||
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
|
||||
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
|
||||
help
|
||||
Specify size of SPIRAM part.
|
||||
NOTE: If SPIRAM size is greater than 4MB, only
|
||||
lower 4MB can be allocated using k_malloc().
|
||||
|
||||
choice SPIRAM_SPEED
|
||||
prompt "Set RAM clock speed"
|
||||
default SPIRAM_SPEED_40M
|
||||
help
|
||||
Select the speed for the SPI RAM chip.
|
||||
|
||||
config SPIRAM_SPEED_20M
|
||||
bool "20MHz clock speed"
|
||||
depends on SOC_SERIES_ESP32S2
|
||||
|
||||
config SPIRAM_SPEED_26M
|
||||
bool "26MHz clock speed"
|
||||
depends on SOC_SERIES_ESP32S2
|
||||
|
||||
config SPIRAM_SPEED_40M
|
||||
bool "40MHz clock speed"
|
||||
|
||||
config SPIRAM_SPEED_80M
|
||||
bool "80MHz clock speed"
|
||||
depends on ESPTOOLPY_FLASHFREQ_80M
|
||||
|
||||
config SPIRAM_SPEED_120M
|
||||
bool "120MHz clock speed"
|
||||
depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3
|
||||
|
||||
endchoice # SPIRAM_SPEED
|
||||
|
||||
config SPIRAM_SPEED
|
||||
int
|
||||
default 120 if SPIRAM_SPEED_120M
|
||||
default 80 if SPIRAM_SPEED_80M
|
||||
default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M
|
||||
|
||||
config SPIRAM_CLK_IO
|
||||
int
|
||||
depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
default 30
|
||||
|
||||
config SPIRAM_CS_IO
|
||||
int
|
||||
depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
default 26
|
||||
|
||||
config SPIRAM_FETCH_INSTRUCTIONS
|
||||
bool "Move Instructions in Flash to PSRAM"
|
||||
depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
default n
|
||||
help
|
||||
If enabled, instructions in flash will be moved into PSRAM on startup.
|
||||
If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation
|
||||
can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
|
||||
for more details).
|
||||
|
||||
config SPIRAM_RODATA
|
||||
bool "Move Read-Only Data in Flash to PSRAM"
|
||||
depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
default n
|
||||
help
|
||||
If enabled, rodata in flash will be moved into PSRAM on startup.
|
||||
If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation
|
||||
can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation
|
||||
for more details).
|
||||
|
||||
if SOC_SERIES_ESP32
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-DOWD"
|
||||
|
||||
config D0WD_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 17
|
||||
help
|
||||
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
|
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
config D0WD_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 16
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
|
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-DOWD
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-D2WD"
|
||||
|
||||
config D2WD_PSRAM_CLK_IO
|
||||
int "PSRAM CLK IO number"
|
||||
range 0 33
|
||||
default 9
|
||||
help
|
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
|
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
config D2WD_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 10
|
||||
help
|
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
|
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-D2WD
|
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-PICO"
|
||||
|
||||
config PICO_PSRAM_CS_IO
|
||||
int "PSRAM CS IO number"
|
||||
range 0 33
|
||||
default 10
|
||||
help
|
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
|
||||
|
||||
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock
|
||||
IO For the reference hardware design, please refer to
|
||||
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
|
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-PICO
|
||||
|
||||
config SPIRAM_CUSTOM_SPIWP_SD3_PIN
|
||||
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)"
|
||||
depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT
|
||||
default n
|
||||
help
|
||||
This setting is only used if the SPI flash pins have been overridden by setting the eFuses
|
||||
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT.
|
||||
|
||||
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
|
||||
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI
|
||||
mode, so a WP pin setting is necessary.
|
||||
|
||||
If this config item is set to N (default), the correct WP pin will be automatically used for any
|
||||
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item
|
||||
to Y and specify the GPIO number connected to the WP pin.
|
||||
|
||||
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin
|
||||
configured in the bootloader.
|
||||
|
||||
config SPIRAM_SPIWP_SD3_PIN
|
||||
int "Custom SPI PSRAM WP(SD3) Pin"
|
||||
depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN
|
||||
range 0 33
|
||||
default 7
|
||||
help
|
||||
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored
|
||||
|
||||
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this
|
||||
value to the GPIO number of the SPIRAM WP pin.
|
||||
|
||||
endif # SOC_SERIES_ESP32
|
||||
|
||||
endmenu # ESP_SPIRAM
|
||||
|
||||
endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
|
||||
133
soc/espressif/common/loader.c
Normal file
133
soc/espressif/common/loader.c
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
#include <hal/mmu_hal.h>
|
||||
#include <hal/mmu_types.h>
|
||||
#include <hal/cache_types.h>
|
||||
#include <hal/cache_ll.h>
|
||||
#include <hal/cache_hal.h>
|
||||
#include <rom/cache.h>
|
||||
#include <esp_rom_sys.h>
|
||||
|
||||
#define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1))
|
||||
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
#include <zephyr/storage/flash_map.h>
|
||||
#include "esp_rom_uart.h"
|
||||
|
||||
#define BOOT_LOG_INF(_fmt, ...) \
|
||||
ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__)
|
||||
|
||||
#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
|
||||
|
||||
void __start(void);
|
||||
|
||||
static HDR_ATTR void (*_entry_point)(void) = &__start;
|
||||
|
||||
extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
|
||||
extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
|
||||
#endif /* CONFIG_BOOTLOADER_MCUBOOT */
|
||||
|
||||
void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
|
||||
uint32_t app_drom_size, uint32_t app_irom_start,
|
||||
uint32_t app_irom_vaddr, uint32_t app_irom_size)
|
||||
{
|
||||
uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
|
||||
uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
|
||||
|
||||
uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
|
||||
uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
|
||||
uint32_t actual_mapped_len = 0;
|
||||
|
||||
#if CONFIG_SOC_SERIES_ESP32
|
||||
Cache_Read_Disable(0);
|
||||
Cache_Flush(0);
|
||||
#else
|
||||
cache_hal_disable(CACHE_TYPE_ALL);
|
||||
#endif
|
||||
|
||||
/* Clear the MMU entries that are already set up,
|
||||
* so the new app only has the mappings it creates.
|
||||
*/
|
||||
mmu_hal_unmap_all();
|
||||
|
||||
#if CONFIG_SOC_SERIES_ESP32
|
||||
int rc = 0;
|
||||
uint32_t drom_page_count =
|
||||
(app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
|
||||
|
||||
rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned,
|
||||
app_drom_start_aligned, 64, drom_page_count);
|
||||
rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned,
|
||||
app_drom_start_aligned, 64, drom_page_count);
|
||||
|
||||
uint32_t irom_page_count =
|
||||
(app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
|
||||
|
||||
rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned,
|
||||
app_irom_start_aligned, 64, irom_page_count);
|
||||
rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned,
|
||||
app_irom_start_aligned, 64, irom_page_count);
|
||||
if (rc != 0) {
|
||||
esp_rom_printf("Failed to setup XIP, aborting\n");
|
||||
abort();
|
||||
}
|
||||
#else
|
||||
mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned,
|
||||
app_drom_size, &actual_mapped_len);
|
||||
|
||||
mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned,
|
||||
app_irom_size, &actual_mapped_len);
|
||||
#endif
|
||||
|
||||
/* ----------------------Enable corresponding buses---------------- */
|
||||
cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size);
|
||||
|
||||
cache_ll_l1_enable_bus(0, bus_mask);
|
||||
bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
|
||||
cache_ll_l1_enable_bus(0, bus_mask);
|
||||
#if CONFIG_MP_MAX_NUM_CPUS > 1
|
||||
bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
|
||||
cache_ll_l1_enable_bus(1, bus_mask);
|
||||
bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
|
||||
cache_ll_l1_enable_bus(1, bus_mask);
|
||||
#endif
|
||||
|
||||
/* ----------------------Enable Cache---------------- */
|
||||
#if CONFIG_SOC_SERIES_ESP32
|
||||
/* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */
|
||||
Cache_Read_Enable(0);
|
||||
#else
|
||||
cache_hal_enable(CACHE_TYPE_ALL);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
#ifdef CONFIG_BOOTLOADER_MCUBOOT
|
||||
size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition);
|
||||
uint32_t _app_irom_start = (_partition_offset + (uint32_t)&_image_irom_start);
|
||||
uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
|
||||
uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr);
|
||||
|
||||
uint32_t _app_drom_start = (_partition_offset + (uint32_t)&_image_drom_start);
|
||||
uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
|
||||
uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr);
|
||||
uint32_t actual_mapped_len = 0;
|
||||
|
||||
map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size,
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size);
|
||||
|
||||
/* Show map segments continue using same log format as during MCUboot phase */
|
||||
BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map",
|
||||
_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size);
|
||||
BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n",
|
||||
_app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size);
|
||||
esp_rom_uart_tx_wait_idle(0);
|
||||
#endif
|
||||
__esp_platform_start();
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue