From e63ddb70b349b6588a1a2d9ba03f34e46e1bdeff Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 6 Mar 2024 23:48:51 -0300 Subject: [PATCH] soc: espressif: common: update to hal_espressif v5.1 Modify and reorganize SoC to meet updated hal. Signed-off-by: Lucas Tamborrino Signed-off-by: Sylvio Alves --- soc/espressif/common/Kconfig | 209 +--------------------- soc/espressif/common/Kconfig.defconfig | 11 +- soc/espressif/common/Kconfig.esptool | 218 +++++++++++++++++++++++ soc/espressif/common/Kconfig.flash | 130 ++++++++++++++ soc/espressif/common/Kconfig.spiram | 235 +++++++++++++++++++++++++ soc/espressif/common/loader.c | 133 ++++++++++++++ 6 files changed, 723 insertions(+), 213 deletions(-) create mode 100644 soc/espressif/common/Kconfig.esptool create mode 100644 soc/espressif/common/Kconfig.flash create mode 100644 soc/espressif/common/Kconfig.spiram create mode 100644 soc/espressif/common/loader.c diff --git a/soc/espressif/common/Kconfig b/soc/espressif/common/Kconfig index 34d3c153c06..42d1961a611 100644 --- a/soc/espressif/common/Kconfig +++ b/soc/espressif/common/Kconfig @@ -1,215 +1,12 @@ # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config ESPTOOLPY_FLASHFREQ_80M - bool - config FLASH_SIZE int config FLASH_BASE_ADDRESS hex -if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 - -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -config ESP_HEAP_SEARCH_ALL_REGIONS - bool "Search for all available heap regions" - depends on ESP_SPIRAM - default y - help - This configuration enables searching all available heap - regions. If the region of desired capability is exhausted, - memory will be allocated from other available region. - -config ESP_SPIRAM_HEAP_SIZE - int "Size of SPIRAM heap" - default 262134 if SYS_HEAP_SMALL_ONLY - default 1048576 if !SYS_HEAP_SMALL_ONLY - depends on ESP_SPIRAM - help - Specify size of SPIRAM heap. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_MODE - prompt "Mode (QUAD/OCT) of SPI RAM chip in use" - default SPIRAM_MODE_QUAD - -config SPIRAM_MODE_QUAD - bool "Quad Mode PSRAM" - -endchoice # SPIRAM_MODE - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - depends on ESP_SPIRAM - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_26M - bool "26MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_20M - bool "20MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -config SPIRAM_SPEED_120M - depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 - bool "120MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO - -config SPIRAM_CUSTOM_SPIWP_SD3_PIN - bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" - default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. - - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI - mode, so a WP pin setting is necessary. - - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item - to Y and specify the GPIO number connected to the WP pin. - - When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin - configured in the bootloader. - -config SPIRAM_SPIWP_SD3_PIN - int "Custom SPI PSRAM WP(SD3) Pin" - range 0 33 - default 7 - help - The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored - - If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this - value to the GPIO number of the SPIRAM WP pin. - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 +rsource "Kconfig.spiram" +rsource "Kconfig.esptool" +rsource "Kconfig.flash" diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig index 62f930b0283..e451dfaae64 100644 --- a/soc/espressif/common/Kconfig.defconfig +++ b/soc/espressif/common/Kconfig.defconfig @@ -21,9 +21,6 @@ config ISR_STACK_SIZE config ATOMIC_OPERATIONS_C default y -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - config SYS_CLOCK_HW_CYCLES_PER_SEC default 16000000 @@ -33,7 +30,7 @@ config SYS_CLOCK_TICKS_PER_SEC config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE default n -config CLOCK_CONTROL +config SOC_FLASH_ESP32 default y if BOOTLOADER_MCUBOOT @@ -54,9 +51,6 @@ endif # BOOTLOADER_MCUBOOT endif # SOC_SERIES_ESP32C3 -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 # Xtensa default options for ESP32 family @@ -75,6 +69,9 @@ config GEN_IRQ_VECTOR_TABLE config CLOCK_CONTROL default y +config SOC_FLASH_ESP32 + default y + config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/espressif/common/Kconfig.esptool b/soc/espressif/common/Kconfig.esptool new file mode 100644 index 00000000000..f7c6e7b5c34 --- /dev/null +++ b/soc/espressif/common/Kconfig.esptool @@ -0,0 +1,218 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +config ESPTOOLPY_OCT_FLASH + bool "Use Octal Flash" + depends on SOC_SERIES_ESP32S3 + default n + +config ESPTOOLPY_FLASH_MODE_AUTO_DETECT + depends on SOC_SERIES_ESP32S3 + bool "Choose flash mode automatically (please read help)" + default y + help + This config option helps decide whether flash is Quad or Octal, but please note some limitations: + + 1. If the flash chip is an Octal one, even if one of "QIO", "QOUT", "DIO", "DOUT" options is + selected in `ESPTOOLPY_FLASHMODE`, our code will automatically change the + mode to "OPI" and the sample mode will be STR. + 2. If the flash chip is a Quad one, even if "OPI" is selected in `ESPTOOLPY_FLASHMODE`, our code will + automatically change the mode to "DIO". + 3. Please do not rely on this option when you are pretty sure that you are using Octal flash, + please enable `ESPTOOLPY_OCT_FLASH` option, then you can choose `DTR` sample mode + in `ESPTOOLPY_FLASH_SAMPLE_MODE`. Otherwise, only `STR` mode is available. + 4. Enabling this feature reduces available internal RAM size (around 900 bytes). + If your IRAM space is insufficient and you're aware of your flash type, + disable this option and select corresponding flash type options. + +choice ESPTOOLPY_FLASHMODE + prompt "Flash SPI mode" + default ESPTOOLPY_FLASHMODE_DIO + default ESPTOOLPY_FLASHMODE_OPI if ESPTOOLPY_OCT_FLASH + help + Mode the flash chip is flashed in, as well as the default mode for the + binary to run in. + +config ESPTOOLPY_FLASHMODE_QIO + bool "QIO" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_QOUT + bool "QOUT" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_DIO + bool "DIO" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_DOUT + bool "DOUT" + depends on !ESPTOOLPY_OCT_FLASH +config ESPTOOLPY_FLASHMODE_OPI + bool "OPI" + depends on ESPTOOLPY_OCT_FLASH + +endchoice # ESPTOOLPY_FLASHMODE + +choice ESPTOOLPY_FLASH_SAMPLE_MODE + prompt "Flash Sampling Mode" + default ESPTOOLPY_FLASH_SAMPLE_MODE_DTR if ESPTOOLPY_OCT_FLASH + default ESPTOOLPY_FLASH_SAMPLE_MODE_STR if !ESPTOOLPY_OCT_FLASH + +config ESPTOOLPY_FLASH_SAMPLE_MODE_STR + bool "STR Mode" +config ESPTOOLPY_FLASH_SAMPLE_MODE_DTR + bool "DTR Mode" + depends on ESPTOOLPY_OCT_FLASH + +endchoice # ESPTOOLPY_FLASH_SAMPLE_MODE + +config ESPTOOLPY_FLASHMODE + string + default "dio" if ESPTOOLPY_FLASHMODE_QIO + default "dio" if ESPTOOLPY_FLASHMODE_QOUT + default "dio" if ESPTOOLPY_FLASHMODE_DIO + default "dout" if ESPTOOLPY_FLASHMODE_DOUT + # The 1st and 2nd bootloader doesn't support opi mode, + # using fastrd instead. For now the ESPTOOL doesn't support + # fasted (see ESPTOOL-274), using dout instead. In ROM the flash mode + # information get from efuse, so don't care this dout choice. + default "dout" if ESPTOOLPY_FLASHMODE_OPI + +choice ESPTOOLPY_FLASHFREQ + prompt "Flash SPI speed" + default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32 + default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT + +config ESPTOOLPY_FLASHFREQ_120M + bool "120 MHz" + select SPI_FLASH_HPM_ENABLE + depends on SOC_SERIES_ESP32S3 && ESPTOOLPY_FLASH_SAMPLE_MODE_STR + help + - Flash 120 MHz SDR mode is stable. + - Flash 120 MHz DDR mode is an experimental feature, it works when + the temperature is stable. + + Risks: + If your chip powers on at a certain temperature, then after the temperature + increases or decreases by approximately 20 Celsius degrees (depending on the + chip), the program will crash randomly. + +config ESPTOOLPY_FLASHFREQ_80M + bool "80 MHz" +config ESPTOOLPY_FLASHFREQ_40M + bool "40 MHz" +config ESPTOOLPY_FLASHFREQ_26M + bool "26 MHz" + depends on !SOC_SERIES_ESP32S3 +config ESPTOOLPY_FLASHFREQ_20M + bool "20 MHz" + +endchoice # ESPTOOLPY_FLASHFREQ + +config ESPTOOLPY_FLASHFREQ_80M_DEFAULT + bool + default y if SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3 + help + This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed. + +config ESPTOOLPY_FLASHFREQ + string + # On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m. + # We currently define this to `80m`. + default '80m' if ESPTOOLPY_FLASHFREQ_120M + default '80m' if ESPTOOLPY_FLASHFREQ_80M + default '40m' if ESPTOOLPY_FLASHFREQ_40M + default '26m' if ESPTOOLPY_FLASHFREQ_26M + default '20m' if ESPTOOLPY_FLASHFREQ_20M + default '20m' # if no clock can match in bin headers, go with minimal. + +choice ESPTOOLPY_FLASHSIZE + prompt "Flash size" + default ESPTOOLPY_FLASHSIZE_2MB + help + SPI flash size, in megabytes + + config ESPTOOLPY_FLASHSIZE_1MB + bool "1 MB" + config ESPTOOLPY_FLASHSIZE_2MB + bool "2 MB" + config ESPTOOLPY_FLASHSIZE_4MB + bool "4 MB" + config ESPTOOLPY_FLASHSIZE_8MB + bool "8 MB" + config ESPTOOLPY_FLASHSIZE_16MB + bool "16 MB" + config ESPTOOLPY_FLASHSIZE_32MB + bool "32 MB" + config ESPTOOLPY_FLASHSIZE_64MB + bool "64 MB" + config ESPTOOLPY_FLASHSIZE_128MB + bool "128 MB" +endchoice + +config ESPTOOLPY_FLASHSIZE + string + default "1MB" if ESPTOOLPY_FLASHSIZE_1MB + default "2MB" if ESPTOOLPY_FLASHSIZE_2MB + default "4MB" if ESPTOOLPY_FLASHSIZE_4MB + default "8MB" if ESPTOOLPY_FLASHSIZE_8MB + default "16MB" if ESPTOOLPY_FLASHSIZE_16MB + default "32MB" if ESPTOOLPY_FLASHSIZE_32MB + default "64MB" if ESPTOOLPY_FLASHSIZE_64MB + default "128MB" if ESPTOOLPY_FLASHSIZE_128MB + +config ESPTOOLPY_HEADER_FLASHSIZE_UPDATE + bool "Detect flash size when flashing bootloader" + default n + help + If this option is set, flashing the project will automatically detect + the flash size of the target chip and update the bootloader image + before it is flashed. + + Enabling this option turns off the image protection against corruption + by a SHA256 digest. Updating the bootloader image before flashing would + invalidate the digest. + +choice ESPTOOLPY_BEFORE + prompt "Before flashing" + default ESPTOOLPY_BEFORE_RESET + help + Configure whether esptool.py should reset the ESP32 before flashing. + + Automatic resetting depends on the RTS & DTR signals being + wired from the serial port to the ESP32. Most USB development + boards do this internally. + + config ESPTOOLPY_BEFORE_RESET + bool "Reset to bootloader" + config ESPTOOLPY_BEFORE_NORESET + bool "No reset" +endchoice # ESPTOOLPY_BEFORE + +config ESPTOOLPY_BEFORE + string + default "default_reset" if ESPTOOLPY_BEFORE_RESET + default "no_reset" if ESPTOOLPY_BEFORE_NORESET + +choice ESPTOOLPY_AFTER + prompt "After flashing" + default ESPTOOLPY_AFTER_RESET + help + Configure whether esptool.py should reset the ESP32 after flashing. + + Automatic resetting depends on the RTS & DTR signals being + wired from the serial port to the ESP32. Most USB development + boards do this internally. + + config ESPTOOLPY_AFTER_RESET + bool "Reset after flashing" + config ESPTOOLPY_AFTER_NORESET + bool "Stay in bootloader" +endchoice + +config ESPTOOLPY_AFTER + string + default "hard_reset" if ESPTOOLPY_AFTER_RESET + default "no_reset" if ESPTOOLPY_AFTER_NORESET + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/common/Kconfig.flash b/soc/espressif/common/Kconfig.flash new file mode 100644 index 00000000000..3dd465c6868 --- /dev/null +++ b/soc/espressif/common/Kconfig.flash @@ -0,0 +1,130 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +config MMU_PAGE_SIZE + hex + default 0x10000 + +config SPI_FLASH_VENDOR_MXIC_SUPPORTED + bool + default y + +config SPI_FLASH_SUPPORT_ISSI_CHIP + bool "ISSI" + default y + help + Enable this to support auto detection of ISSI chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_MXIC_CHIP + bool "MXIC" + default y + help + Enable this to support auto detection of MXIC chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_GD_CHIP + bool "GigaDevice" + default y + help + Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not + directly given by ``chip_drv`` member of the chip struct. If you are using Wrover + modules, please don't disable this, otherwise your flash may not work in 4-bit + mode. + + This adds support for variant chips, however will extend detecting time and image + size. Note that the default chip driver supports the GD chips with product ID + 60H. + +config SPI_FLASH_SUPPORT_WINBOND_CHIP + bool "Winbond" + default y + help + Enable this to support auto detection of Winbond chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_BOYA_CHIP + bool "BOYA" + default y if !SOC_SERIES_ESP32 + help + Enable this to support auto detection of BOYA chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_TH_CHIP + bool "TH" + default y if !SOC_SERIES_ESP32 + help + Enable this to support auto detection of TH chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_SUPPORT_MXIC_OPI_CHIP + bool "mxic (opi)" + depends on SOC_SERIES_ESP32S3 + default y + help + Enable this to support auto detection of Octal MXIC chips if chip vendor not directly + given by ``chip_drv`` member of the chip struct. This adds support for variant + chips, however will extend detecting time. + +config SPI_FLASH_ROM_DRIVER_PATCH + bool "SPI flash ROM driver patched functions" + default y + help + Enable this flag to use patched versions of SPI flash ROM driver functions. + This option should be enabled, if any one of the following is true: (1) need to write + to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main + SPI flash chip is manufactured by ISSI. + +config BOOTLOADER_FLASH_XMC_SUPPORT + bool "Support flash chips of XMC (READ HELP FIRST)" + default y + help + Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow. + XMC chips will be forbidden to be used, when this option is disabled. + + DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING. + +choice BOOTLOADER_VDDSDIO_BOOST + bool "VDDSDIO LDO voltage" + default BOOTLOADER_VDDSDIO_BOOST_1_9V + depends on !SOC_SERIES_ESP32C3 + help + If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse + or MTDI bootstrapping pin), bootloader will change LDO settings to + output 1.9V instead. This helps prevent flash chip from browning out + during flash programming operations. + + This option has no effect if VDDSDIO is set to 3.3V, or if the internal + VDDSDIO regulator is disabled via eFuse. + + config BOOTLOADER_VDDSDIO_BOOST_1_8V + bool "1.8V" + depends on !ESPTOOLPY_FLASHFREQ_80M + config BOOTLOADER_VDDSDIO_BOOST_1_9V + bool "1.9V" +endchoice + +config BOOTLOADER_REGION_PROTECTION_ENABLE + bool "Protect unmapped memory regions from unintended accesses" + default y + help + Protects the unmapped memory regions of the entire address space from unintended accesses. + This will ensure that an exception will be triggered whenever the CPU performs a memory + operation on unmapped regions of the address space. + +config SPI_FLASH_HPM_ENABLE + bool + depends on SOC_SERIES_ESP32S3 + default n + help + This option is invisible, and will be selected automatically + when ``ESPTOOLPY_FLASHFREQ_120M`` is selected. + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/common/Kconfig.spiram b/soc/espressif/common/Kconfig.spiram new file mode 100644 index 00000000000..0daad784aa9 --- /dev/null +++ b/soc/espressif/common/Kconfig.spiram @@ -0,0 +1,235 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +config ESP_SPIRAM + bool "Support for external, SPI-connected RAM" + default n if MCUBOOT + help + This enables support for an external SPI RAM chip, connected in + parallel with the main SPI flash chip. + +menu "SPI RAM config" + depends on ESP_SPIRAM + +config ESP_HEAP_MIN_EXTRAM_THRESHOLD + int "Minimum threshold for external RAM allocation" + default 8192 + range 1024 131072 + help + Threshold to decide if memory will be allocated from DRAM + or SPIRAM. If value of allocation size is less than this value, + memory will be allocated from internal RAM. + +config ESP_HEAP_SEARCH_ALL_REGIONS + bool "Search for all available heap regions" + default y + help + This configuration enables searching all available heap + regions. If the region of desired capability is exhausted, + memory will be allocated from other available region. + +config ESP_SPIRAM_HEAP_SIZE + int "Size of SPIRAM heap" + default 262134 if SYS_HEAP_SMALL_ONLY + default 1048576 if !SYS_HEAP_SMALL_ONLY + help + Specify size of SPIRAM heap. + +choice SPIRAM_MODE + prompt "Mode (QUAD/OCT) of SPI RAM chip in use" + default SPIRAM_MODE_QUAD + + config SPIRAM_MODE_QUAD + bool "Quad Mode PSRAM" + + config SPIRAM_MODE_OCT + bool "Octal Mode PSRAM" + depends on SOC_SERIES_ESP32S3 + +endchoice # SPIRAM_MODE + +choice SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default SPIRAM_TYPE_ESPPSRAM16 if SPIRAM_MODE_QUAD + default SPIRAM_TYPE_ESPPSRAM64 + +config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + depends on SPIRAM_MODE_QUAD + +config SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + depends on SPIRAM_MODE_QUAD + +config SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64, LY68L6400 or APS6408" + +endchoice # SPIRAM_TYPE + +config ESP_SPIRAM_SIZE + int "Size of SPIRAM part" + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + help + Specify size of SPIRAM part. + NOTE: If SPIRAM size is greater than 4MB, only + lower 4MB can be allocated using k_malloc(). + +choice SPIRAM_SPEED + prompt "Set RAM clock speed" + default SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + +config SPIRAM_SPEED_20M + bool "20MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_26M + bool "26MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config SPIRAM_SPEED_80M + bool "80MHz clock speed" + depends on ESPTOOLPY_FLASHFREQ_80M + +config SPIRAM_SPEED_120M + bool "120MHz clock speed" + depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 + +endchoice # SPIRAM_SPEED + +config SPIRAM_SPEED + int + default 120 if SPIRAM_SPEED_120M + default 80 if SPIRAM_SPEED_80M + default 40 if SPIRAM_SPEED_40M || SPIRAM_SPEED_26M || SPIRAM_SPEED_20M + +config SPIRAM_CLK_IO + int + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default 30 + +config SPIRAM_CS_IO + int + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default 26 + +config SPIRAM_FETCH_INSTRUCTIONS + bool "Move Instructions in Flash to PSRAM" + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default n + help + If enabled, instructions in flash will be moved into PSRAM on startup. + If SPIRAM_RODATA is also enabled, code that requires execution during an SPI1 Flash operation + can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation + for more details). + +config SPIRAM_RODATA + bool "Move Read-Only Data in Flash to PSRAM" + depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + default n + help + If enabled, rodata in flash will be moved into PSRAM on startup. + If SPIRAM_FETCH_INSTRUCTIONS is also enabled, code that requires execution during an SPI1 Flash operation + can forgo being placed in IRAM, thus optimizing RAM usage (see External RAM documentation + for more details). + +if SOC_SERIES_ESP32 + +menu "PSRAM clock and cs IO for ESP32-DOWD" + +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-DOWD + +menu "PSRAM clock and cs IO for ESP32-D2WD" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-D2WD + +menu "PSRAM clock and cs IO for ESP32-PICO" + +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + + For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock + IO For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endmenu # PSRAM clock and cs IO for ESP32-PICO + +config SPIRAM_CUSTOM_SPIWP_SD3_PIN + bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" + depends on ESPTOOLPY_FLASHMODE_DIO || ESPTOOLPY_FLASHMODE_DOUT + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI + mode, so a WP pin setting is necessary. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item + to Y and specify the GPIO number connected to the WP pin. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin + configured in the bootloader. + +config SPIRAM_SPIWP_SD3_PIN + int "Custom SPI PSRAM WP(SD3) Pin" + depends on SPIRAM_CUSTOM_SPIWP_SD3_PIN + range 0 33 + default 7 + help + The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored + + If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this + value to the GPIO number of the SPIRAM WP pin. + +endif # SOC_SERIES_ESP32 + +endmenu # ESP_SPIRAM + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c new file mode 100644 index 00000000000..6d1b7ecba0e --- /dev/null +++ b/soc/espressif/common/loader.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MMU_FLASH_MASK (~(CONFIG_MMU_PAGE_SIZE - 1)) + +#ifdef CONFIG_BOOTLOADER_MCUBOOT +#include +#include "esp_rom_uart.h" + +#define BOOT_LOG_INF(_fmt, ...) \ + ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) + +#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) + +void __start(void); + +static HDR_ATTR void (*_entry_point)(void) = &__start; + +extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; +extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; +#endif /* CONFIG_BOOTLOADER_MCUBOOT */ + +void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) +{ + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; + uint32_t actual_mapped_len = 0; + +#if CONFIG_SOC_SERIES_ESP32 + Cache_Read_Disable(0); + Cache_Flush(0); +#else + cache_hal_disable(CACHE_TYPE_ALL); +#endif + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ + mmu_hal_unmap_all(); + +#if CONFIG_SOC_SERIES_ESP32 + int rc = 0; + uint32_t drom_page_count = + (app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + + rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned, + app_drom_start_aligned, 64, drom_page_count); + rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned, + app_drom_start_aligned, 64, drom_page_count); + + uint32_t irom_page_count = + (app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE; + + rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned, + app_irom_start_aligned, 64, irom_page_count); + rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned, + app_irom_start_aligned, 64, irom_page_count); + if (rc != 0) { + esp_rom_printf("Failed to setup XIP, aborting\n"); + abort(); + } +#else + mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); +#endif + + /* ----------------------Enable corresponding buses---------------- */ + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size); + + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_MP_MAX_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ----------------------Enable Cache---------------- */ +#if CONFIG_SOC_SERIES_ESP32 + /* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */ + Cache_Read_Enable(0); +#else + cache_hal_enable(CACHE_TYPE_ALL); +#endif +} + +void __start(void) +{ +#ifdef CONFIG_BOOTLOADER_MCUBOOT + size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); + uint32_t _app_irom_start = (_partition_offset + (uint32_t)&_image_irom_start); + uint32_t _app_irom_size = (uint32_t)&_image_irom_size; + uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr); + + uint32_t _app_drom_start = (_partition_offset + (uint32_t)&_image_drom_start); + uint32_t _app_drom_size = (uint32_t)&_image_drom_size; + uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr); + uint32_t actual_mapped_len = 0; + + map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, + _app_irom_start, _app_irom_vaddr, _app_irom_size); + + /* Show map segments continue using same log format as during MCUboot phase */ + BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", + _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); + BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", + _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); + esp_rom_uart_tx_wait_idle(0); +#endif + __esp_platform_start(); +}