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boards: arm: s32z270dc2_r52: enable watchdog support

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Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
 s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.

Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
This commit is contained in:
Quang Bui Trong 2022-11-10 21:39:14 +07:00 • committed by Carles Cufí
commit e63d1389a9
5 changed files with 93 additions and 2 deletions
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21
boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
View file

@ -68,3 +68,24 @@
&stm3 { &stm3 {
clock-frequency = <133333333>; clock-frequency = <133333333>;
}; };
&swt0 {
clock-frequency = <48000000>;
status = "okay";
};
&swt1 {
clock-frequency = <48000000>;
};
&swt2 {
clock-frequency = <48000000>;
};
&swt3 {
clock-frequency = <48000000>;
};
&swt4 {
clock-frequency = <48000000>;
};

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml
View file

@ -11,3 +11,4 @@ toolchain:
supported: supported:
- uart - uart
- gpio - gpio
- watchdog

1
boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml
View file

@ -11,3 +11,4 @@ toolchain:
supported: supported:
- uart - uart
- gpio - gpio
- watchdog

36
dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi
View file

@ -43,6 +43,40 @@
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled"; status = "disabled";
}; };
};
swt0: watchdog@76000000 {
compatible = "nxp,s32-swt";
reg = <0x76000000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt1: watchdog@76010000 {
compatible = "nxp,s32-swt";
reg = <0x76010000 0x10000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt2: watchdog@76220000 {
compatible = "nxp,s32-swt";
reg = <0x76220000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt3: watchdog@76230000 {
compatible = "nxp,s32-swt";
reg = <0x76230000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt4: watchdog@76140000 {
compatible = "nxp,s32-swt";
reg = <0x76140000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
};
}; };

36
dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi
View file

@ -43,6 +43,40 @@
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled"; status = "disabled";
}; };
};
swt0: watchdog@76800000 {
compatible = "nxp,s32-swt";
reg = <0x76800000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt1: watchdog@76810000 {
compatible = "nxp,s32-swt";
reg = <0x76810000 0x10000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt2: watchdog@76a20000 {
compatible = "nxp,s32-swt";
reg = <0x76a20000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt3: watchdog@76a30000 {
compatible = "nxp,s32-swt";
reg = <0x76a30000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
swt4: watchdog@76940000 {
compatible = "nxp,s32-swt";
reg = <0x76940000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
};
}; };