From e63d1389a95c7b618c9764da71bf6a2ab77ad250 Mon Sep 17 00:00:00 2001
From: Quang Bui Trong <quang.buitrong@nxp.com>
Date: Thu, 10 Nov 2022 21:39:14 +0700
Subject: [PATCH] boards: arm: s32z270dc2_r52: enable watchdog support

 Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
 s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.

Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
---
 boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi | 21 +++++++++++
 .../s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml   |  1 +
 .../s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml   |  1 +
 dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi         | 36 ++++++++++++++++++-
 dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi         | 36 ++++++++++++++++++-
 5 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
index 021a70f69ec..a9d81c2da04 100644
--- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
+++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi
@@ -68,3 +68,24 @@
 &stm3 {
 	clock-frequency = <133333333>;
 };
+
+&swt0 {
+	clock-frequency = <48000000>;
+	status = "okay";
+};
+
+&swt1 {
+	clock-frequency = <48000000>;
+};
+
+&swt2 {
+	clock-frequency = <48000000>;
+};
+
+&swt3 {
+	clock-frequency = <48000000>;
+};
+
+&swt4 {
+	clock-frequency = <48000000>;
+};
diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml
index 732455e9325..45ca0c1bc48 100644
--- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml
+++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml
@@ -11,3 +11,4 @@ toolchain:
 supported:
   - uart
   - gpio
+  - watchdog
diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml
index 2c328f20e82..3bdfde7bf92 100644
--- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml
+++ b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml
@@ -11,3 +11,4 @@ toolchain:
 supported:
   - uart
   - gpio
+  - watchdog
diff --git a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi
index 9551bbfc858..4c429b535e9 100644
--- a/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi
@@ -43,6 +43,40 @@
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 			status = "disabled";
 		};
-	};
 
+		swt0: watchdog@76000000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76000000 0x10000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt1: watchdog@76010000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76010000 0x10000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt2: watchdog@76220000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76220000 0x10000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt3: watchdog@76230000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76230000 0x10000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt4: watchdog@76140000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76140000 0x10000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+	};
 };
diff --git a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi
index 9401e088215..a399f1b1e00 100644
--- a/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi
@@ -43,6 +43,40 @@
 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 			status = "disabled";
 		};
-	};
 
+		swt0: watchdog@76800000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76800000 0x10000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt1: watchdog@76810000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76810000 0x10000>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt2: watchdog@76a20000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76a20000 0x10000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt3: watchdog@76a30000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76a30000 0x10000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		swt4: watchdog@76940000 {
+			compatible = "nxp,s32-swt";
+			reg = <0x76940000 0x10000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+	};
 };