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include/dt-bindings/clock: stm32: Factorize Clock source binding accessors

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Rename and factorize clock source bindings accessors by moving them
in common header file stm32_clock_control and remove them from
include/dt-bindings/clock/stm32XY_clock.h files

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-31 15:42:59 +02:00 • committed by Carles Cufí
commit e579027d20
5 changed files with 124 additions and 163 deletions
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6
drivers/clock_control/clock_stm32_ll_h7.c
View file

@ -417,10 +417,10 @@ static inline int stm32_clock_control_configure(const struct device *dev,
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
dt_val = STM32H7_CLOCK_VAL_GET(pclken->enr) << dt_val = STM32_CLOCK_VAL_GET(pclken->enr) <<
STM32H7_CLOCK_SHIFT_GET(pclken->enr); STM32_CLOCK_SHIFT_GET(pclken->enr);
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) +
STM32H7_CLOCK_REG_GET(pclken->enr)); STM32_CLOCK_REG_GET(pclken->enr));
reg_val = *reg; reg_val = *reg;
reg_val &= ~dt_val; reg_val &= ~dt_val;
reg_val |= dt_val; reg_val |= dt_val;

6
drivers/clock_control/clock_stm32_ll_u5.c
View file

@ -184,10 +184,10 @@ static inline int stm32_clock_control_configure(const struct device *dev,
return err; return err;
} }
dt_val = STM32U5_CLOCK_VAL_GET(pclken->enr) << dt_val = STM32_CLOCK_VAL_GET(pclken->enr) <<
STM32U5_CLOCK_SHIFT_GET(pclken->enr); STM32_CLOCK_SHIFT_GET(pclken->enr);
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) +
STM32U5_CLOCK_REG_GET(pclken->enr)); STM32_CLOCK_REG_GET(pclken->enr));
reg_val = *reg; reg_val = *reg;
reg_val |= dt_val; reg_val |= dt_val;
*reg = reg_val; *reg = reg_val;

34
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -307,4 +307,38 @@ struct stm32_pclken {
#define STM32_DT_DEV_OPT_CLOCK_SUPPORT \ #define STM32_DT_DEV_OPT_CLOCK_SUPPORT \
(DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0) (DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0)
/** Clock source binding accessors */
/**
* @brief Obtain register field from clock configuration.
*
* @param clock clock bit field value.
*/
#define STM32_CLOCK_REG_GET(clock) \
(((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
/**
* @brief Obtain position field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32_CLOCK_SHIFT_GET(clock) \
(((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
/**
* @brief Obtain mask field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32_CLOCK_MASK_GET(clock) \
(((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
/**
* @brief Obtain value field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32_CLOCK_VAL_GET(clock) \
(((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */

120
include/zephyr/dt-bindings/clock/stm32h7_clock.h
View file

@ -74,55 +74,20 @@
* @param val Clock value (0, 1, 2 or 3). * @param val Clock value (0, 1, 2 or 3).
*/ */
#define STM32H7_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_MASK 0xFFU
#define STM32H7_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_REG_SHIFT 0U
#define STM32H7_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_MASK 0x1FU
#define STM32H7_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_SHIFT_SHIFT 8U
#define STM32H7_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_MASK 0x7U
#define STM32H7_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_MASK_SHIFT 13U
#define STM32H7_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_MASK 0x7U
#define STM32H7_CLOCK_VAL_SHIFT 16U #define STM32_CLOCK_VAL_SHIFT 16U
#define STM32H7_CLOCK(val, mask, shift, reg) \ #define STM32_CLOCK(val, mask, shift, reg) \
((((reg) & STM32H7_CLOCK_REG_MASK) << STM32H7_CLOCK_REG_SHIFT) | \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
(((shift) & STM32H7_CLOCK_SHIFT_MASK) << STM32H7_CLOCK_SHIFT_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
(((mask) & STM32H7_CLOCK_MASK_MASK) << STM32H7_CLOCK_MASK_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
(((val) & STM32H7_CLOCK_VAL_MASK) << STM32H7_CLOCK_VAL_SHIFT)) (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
/* Accessors for clock value */
/**
* @brief Obtain register field from clock configuration.
*
* @param clock clock bit field value.
*/
#define STM32H7_CLOCK_REG_GET(clock) \
(((clock) >> STM32H7_CLOCK_REG_SHIFT) & STM32H7_CLOCK_REG_MASK)
/**
* @brief Obtain position field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32H7_CLOCK_SHIFT_GET(clock) \
(((clock) >> STM32H7_CLOCK_SHIFT_SHIFT) & STM32H7_CLOCK_SHIFT_MASK)
/**
* @brief Obtain mask field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32H7_CLOCK_MASK_GET(clock) \
(((clock) >> STM32H7_CLOCK_MASK_SHIFT) & STM32H7_CLOCK_MASK_MASK)
/**
* @brief Obtain value field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32H7_CLOCK_VAL_GET(clock) \
(((clock) >> STM32H7_CLOCK_VAL_SHIFT) & STM32H7_CLOCK_VAL_MASK)
/** @brief RCC_DxCCIP register offset (RM0399.pdf) */ /** @brief RCC_DxCCIP register offset (RM0399.pdf) */
#define D1CCIPR_REG 0x4C #define D1CCIPR_REG 0x4C
@ -132,39 +97,36 @@
/** @brief Device clk sources selection helpers (RM0399.pdf) */ /** @brief Device clk sources selection helpers (RM0399.pdf) */
/** D1CCIPR devices */ /** D1CCIPR devices */
#define FMC_SEL(val) STM32H7_CLOCK(val, 3, 0, D1CCIPR_REG) #define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG)
#define QSPI_SEL(val) STM32H7_CLOCK(val, 3, 4, D1CCIPR_REG) #define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG)
#define DSI_SEL(val) STM32H7_CLOCK(val, 1, 8, D1CCIPR_REG) #define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG)
#define SDMMC_SEL(val) STM32H7_CLOCK(val, 1, 16, D1CCIPR_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG)
#define CKPER_SEL(val) STM32H7_CLOCK(val, 3, 28, D1CCIPR_REG) #define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG)
/** D2CCIP1R devices */ /** D2CCIP1R devices */
#define SAI1_SEL(val) STM32H7_CLOCK(val, 7, 0, D2CCIP1R_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG)
#define SAI23_SEL(val) STM32H7_CLOCK(val, 7, 6, D2CCIP1R_REG) #define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG)
#define SPI123_SEL(val) STM32H7_CLOCK(val, 7, 12, D2CCIP1R_REG) #define SPI123_SEL(val) STM32_CLOCK(val, 7, 12, D2CCIP1R_REG)
#define SPI45_SEL(val) STM32H7_CLOCK(val, 7, 16, D2CCIP1R_REG) #define SPI45_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIP1R_REG)
#define SPDIF_SEL(val) STM32H7_CLOCK(val, 3, 20, D2CCIP1R_REG) #define SPDIF_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP1R_REG)
#define DFSDM1_SEL(val) STM32H7_CLOCK(val, 1, 24, D2CCIP1R_REG) #define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 24, D2CCIP1R_REG)
#define FDCAN_SEL(val) STM32H7_CLOCK(val, 3, 28, D2CCIP1R_REG) #define FDCAN_SEL(val) STM32_CLOCK(val, 3, 28, D2CCIP1R_REG)
#define SWP_SEL(val) STM32H7_CLOCK(val, 1, 31, D2CCIP1R_REG) #define SWP_SEL(val) STM32_CLOCK(val, 1, 31, D2CCIP1R_REG)
/** D2CCIP2R devices */ /** D2CCIP2R devices */
#define USART2345678_SEL(val) STM32H7_CLOCK(val, 7, 0, D2CCIP2R_REG) #define USART2345678_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP2R_REG)
#define USART16_SEL(val) STM32H7_CLOCK(val, 7, 3, D2CCIP2R_REG) #define USART16_SEL(val) STM32_CLOCK(val, 7, 3, D2CCIP2R_REG)
#define RNG_SEL(val) STM32H7_CLOCK(val, 3, 8, D2CCIP2R_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIP2R_REG)
#define I2C123_SEL(val) STM32H7_CLOCK(val, 3, 12, D2CCIP2R_REG) #define I2C123_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIP2R_REG)
#define USB_SEL(val) STM32H7_CLOCK(val, 3, 20, D2CCIP2R_REG) #define USB_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP2R_REG)
#define CEC_SEL(val) STM32H7_CLOCK(val, 3, 22, D2CCIP2R_REG) #define CEC_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIP2R_REG)
#define LPTIM1_SEL(val) STM32H7_CLOCK(val, 7, 28, D2CCIP2R_REG) #define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 28, D2CCIP2R_REG)
/** D3CCIPR devices */ /** D3CCIPR devices */
#define LPUART1_SEL(val) STM32H7_CLOCK(val, 7, 0, D3CCIPR_REG) #define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG)
#define I2C4_SEL(val) STM32H7_CLOCK(val, 3, 8, D3CCIPR_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 8, D3CCIPR_REG)
#define LPTIM2_SEL(val) STM32H7_CLOCK(val, 7, 10, D3CCIPR_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 10, D3CCIPR_REG)
#define LPTIM345_SEL(val) STM32H7_CLOCK(val, 7, 13, D3CCIPR_REG) #define LPTIM345_SEL(val) STM32_CLOCK(val, 7, 13, D3CCIPR_REG)
#define ADC_SEL(val) STM32H7_CLOCK(val, 3, 16, D3CCIPR_REG) #define ADC_SEL(val) STM32_CLOCK(val, 3, 16, D3CCIPR_REG)
#define SAI4A_SEL(val) STM32H7_CLOCK(val, 7, 21, D3CCIPR_REG) #define SAI4A_SEL(val) STM32_CLOCK(val, 7, 21, D3CCIPR_REG)
#define SAI4B_SEL(val) STM32H7_CLOCK(val, 7, 24, D3CCIPR_REG) #define SAI4B_SEL(val) STM32_CLOCK(val, 7, 24, D3CCIPR_REG)
#define SPI6_SEL(val) STM32H7_CLOCK(val, 7, 28, D3CCIPR_REG) #define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG)
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB3
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB4
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */

121
include/zephyr/dt-bindings/clock/stm32u5_clock.h
View file

@ -64,55 +64,20 @@
* @param val Clock value (0, 1, ... 7). * @param val Clock value (0, 1, ... 7).
*/ */
#define STM32U5_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_MASK 0xFFU
#define STM32U5_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_REG_SHIFT 0U
#define STM32U5_CLOCK_SHIFT_MASK 0x1FU #define STM32_CLOCK_SHIFT_MASK 0x1FU
#define STM32U5_CLOCK_SHIFT_SHIFT 8U #define STM32_CLOCK_SHIFT_SHIFT 8U
#define STM32U5_CLOCK_MASK_MASK 0x7U #define STM32_CLOCK_MASK_MASK 0x7U
#define STM32U5_CLOCK_MASK_SHIFT 13U #define STM32_CLOCK_MASK_SHIFT 13U
#define STM32U5_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_MASK 0x7U
#define STM32U5_CLOCK_VAL_SHIFT 16U #define STM32_CLOCK_VAL_SHIFT 16U
#define STM32U5_CLOCK(val, mask, shift, reg) \ #define STM32_CLOCK(val, mask, shift, reg) \
((((reg) & STM32U5_CLOCK_REG_MASK) << STM32U5_CLOCK_REG_SHIFT) | \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
(((shift) & STM32U5_CLOCK_SHIFT_MASK) << STM32U5_CLOCK_SHIFT_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
(((mask) & STM32U5_CLOCK_MASK_MASK) << STM32U5_CLOCK_MASK_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
(((val) & STM32U5_CLOCK_VAL_MASK) << STM32U5_CLOCK_VAL_SHIFT)) (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
/* Accessors for clock value */
/**
* @brief Obtain register field from clock configuration.
*
* @param clock clock bit field value.
*/
#define STM32U5_CLOCK_REG_GET(clock) \
(((clock) >> STM32U5_CLOCK_REG_SHIFT) & STM32U5_CLOCK_REG_MASK)
/**
* @brief Obtain position field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32U5_CLOCK_SHIFT_GET(clock) \
(((clock) >> STM32U5_CLOCK_SHIFT_SHIFT) & STM32U5_CLOCK_SHIFT_MASK)
/**
* @brief Obtain mask field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32U5_CLOCK_MASK_GET(clock) \
(((clock) >> STM32U5_CLOCK_MASK_SHIFT) & STM32U5_CLOCK_MASK_MASK)
/**
* @brief Obtain value field from clock configuration.
*
* @param clock Clock bit field value.
*/
#define STM32U5_CLOCK_VAL_GET(clock) \
(((clock) >> STM32U5_CLOCK_VAL_SHIFT) & STM32U5_CLOCK_VAL_MASK)
/** @brief RCC_CCIPRx register offset (RM0456.pdf) */ /** @brief RCC_CCIPRx register offset (RM0456.pdf) */
#define CCIPR1_REG 0xE0 #define CCIPR1_REG 0xE0
@ -121,37 +86,37 @@
/** @brief Device clk sources selection helpers (RM0399.pdf) */ /** @brief Device clk sources selection helpers (RM0399.pdf) */
/** CCIPR1 devices */ /** CCIPR1 devices */
#define USART1_SEL(val) STM32U5_CLOCK(val, 3, 0, CCIPR1_REG) #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG)
#define USART2_SEL(val) STM32U5_CLOCK(val, 3, 2, CCIPR1_REG) #define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG)
#define USART3_SEL(val) STM32U5_CLOCK(val, 3, 4, CCIPR1_REG) #define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG)
#define USART4_SEL(val) STM32U5_CLOCK(val, 3, 6, CCIPR1_REG) #define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG)
#define USART5_SEL(val) STM32U5_CLOCK(val, 3, 8, CCIPR1_REG) #define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG)
#define I2C1_SEL(val) STM32U5_CLOCK(val, 3, 10, CCIPR1_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG)
#define I2C2_SEL(val) STM32U5_CLOCK(val, 3, 12, CCIPR1_REG) #define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG)
#define I2C4_SEL(val) STM32U5_CLOCK(val, 3, 14, CCIPR1_REG) #define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG)
#define SPI2_SEL(val) STM32U5_CLOCK(val, 3, 16, CCIPR1_REG) #define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG)
#define LPTIM2_SEL(val) STM32U5_CLOCK(val, 3, 18, CCIPR1_REG) #define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG)
#define SPI1_SEL(val) STM32U5_CLOCK(val, 3, 20, CCIPR1_REG) #define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG)
#define SYSTICK_SEL(val) STM32U5_CLOCK(val, 3, 22, CCIPR1_REG) #define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG)
#define FDCAN1_SEL(val) STM32U5_CLOCK(val, 3, 24, CCIPR1_REG) #define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG)
#define ICKLK_SEL(val) STM32U5_CLOCK(val, 3, 26, CCIPR1_REG) #define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG)
#define TIMIC_SEL(val) STM32U5_CLOCK(val, 7, 29, CCIPR1_REG) #define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG)
/** CCIPR2 devices */ /** CCIPR2 devices */
#define MDF1_SEL(val) STM32U5_CLOCK(val, 7, 0, CCIPR2_REG) #define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG)
#define SAI1_SEL(val) STM32U5_CLOCK(val, 7, 5, CCIPR2_REG) #define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG)
#define SAI2_SEL(val) STM32U5_CLOCK(val, 7, 8, CCIPR2_REG) #define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG)
#define SAE_SEL(val) STM32U5_CLOCK(val, 1, 11, CCIPR2_REG) #define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG)
#define RNG_SEL(val) STM32U5_CLOCK(val, 3, 12, CCIPR2_REG) #define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
#define SDMMC_SEL(val) STM32U5_CLOCK(val, 1, 14, CCIPR2_REG) #define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG)
#define OCTOSPI_SEL(val) STM32U5_CLOCK(val, 3, 20, CCIPR2_REG) #define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG)
/** CCIPR3 devices */ /** CCIPR3 devices */
#define LPUART1_SEL(val) STM32U5_CLOCK(val, 7, 0, CCIPR3_REG)
#define SPI3_SEL(val) STM32U5_CLOCK(val, 3, 3, CCIPR3_REG)
#define I2C3_SEL(val) STM32U5_CLOCK(val, 3, 6, CCIPR3_REG)
#define LPTIM34_SEL(val) STM32U5_CLOCK(val, 3, 8, CCIPR3_REG)
#define LPTIM1_SEL(val) STM32U5_CLOCK(val, 3, 10, CCIPR3_REG)
#define ADCDAC_SEL(val) STM32U5_CLOCK(val, 7, 12, CCIPR3_REG)
#define DAC1_SEL(val) STM32U5_CLOCK(val, 1, 15, CCIPR3_REG)
#define ADF1_SEL(val) STM32U5_CLOCK(val, 7, 16, CCIPR3_REG)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */
#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG)
#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG)
#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG)
#define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG)
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG)
#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG)
#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG)
#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG)