diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index db17bdd6c61..fff8c698894 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -153,6 +153,14 @@
 #endif
 #endif /* CONFIG_CPU_CORTEX_M7 */
 
+#if defined(CONFIG_CPU_CORTEX_M7)
+/* Offset to access bus clock registers from M7 (or only) core */
+#define STM32H7_BUS_CLK_REG	DT_REG_ADDR(DT_NODELABEL(rcc))
+#elif defined(CONFIG_CPU_CORTEX_M4)
+/* Offset to access bus clock registers from M4 core */
+#define STM32H7_BUS_CLK_REG	DT_REG_ADDR(DT_NODELABEL(rcc)) + 0x60
+#endif
+
 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
 {
 	return clock / prescaler;
@@ -329,7 +337,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
 
 	z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 
-	reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
+	reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
 	reg_val = *reg;
 	reg_val |= pclken->enr;
 	*reg = reg_val;
@@ -355,7 +363,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
 
 	z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 
-	reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
+	reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
 	reg_val = *reg;
 	reg_val &= ~pclken->enr;
 	*reg = reg_val;
diff --git a/include/dt-bindings/clock/stm32h7_clock.h b/include/dt-bindings/clock/stm32h7_clock.h
index 8c6a3e6a579..608bc218281 100644
--- a/include/dt-bindings/clock/stm32h7_clock.h
+++ b/include/dt-bindings/clock/stm32h7_clock.h
@@ -7,15 +7,15 @@
 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_
 
 /* clock bus references */
-#define STM32_CLOCK_BUS_AHB3    0x0D4
-#define STM32_CLOCK_BUS_AHB1    0x0D8
-#define STM32_CLOCK_BUS_AHB2    0x0DC
-#define STM32_CLOCK_BUS_AHB4    0x0E0
-#define STM32_CLOCK_BUS_APB3    0x0E4
-#define STM32_CLOCK_BUS_APB1    0x0E8
-#define STM32_CLOCK_BUS_APB1_2  0x0EC
-#define STM32_CLOCK_BUS_APB2    0x0F0
-#define STM32_CLOCK_BUS_APB4    0x0F4
+#define STM32_CLOCK_BUS_AHB3    0x134
+#define STM32_CLOCK_BUS_AHB1    0x138
+#define STM32_CLOCK_BUS_AHB2    0x13c
+#define STM32_CLOCK_BUS_AHB4    0x140
+#define STM32_CLOCK_BUS_APB3    0x144
+#define STM32_CLOCK_BUS_APB1    0x148
+#define STM32_CLOCK_BUS_APB1_2  0x14c
+#define STM32_CLOCK_BUS_APB2    0x150
+#define STM32_CLOCK_BUS_APB4    0x154
 
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB3
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB4