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gpio: Add ARM CMSDK (Cortex-M System Design Kit) AHB GPIO driver

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The driver is currently used only by the ARM Beetle platform.

Jira: ZEP-1245
Change-Id: I6611edd7486a3c6d82d66a9a96c5d4860dad1539
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Vincenzo Frascino 2016-09-12 15:55:40 +01:00 • committed by Kumar Gala
commit e36c04afe1
5 changed files with 605 additions and 0 deletions
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2
drivers/gpio/Kconfig
View file

@ -61,4 +61,6 @@ source "drivers/gpio/Kconfig.stm32"
source "drivers/gpio/Kconfig.nrf5"
source "drivers/gpio/Kconfig.cmsdk_ahb"
endif # GPIO

122
drivers/gpio/Kconfig.cmsdk_ahb Normal file
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@ -0,0 +1,122 @@
# Kconfig.cmsdk_ahb - ARM CMSDK (Cortex-M System Design Kit) AHB GPIO cfg
#
#
# Copyright (c) 2016 Linaro Limited
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
menuconfig GPIO_CMSDK_AHB
bool "ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers"
depends on GPIO && SOC_SERIES_BEETLE
default n
help
Enable config options to support the ARM CMSDK GPIO controllers.
Says n if not sure.
if GPIO_CMSDK_AHB
# ---------- Port 0 ----------
config GPIO_CMSDK_AHB_PORT0
bool "Enable driver for GPIO Port 0"
depends on GPIO_CMSDK_AHB
default n
help
Build the driver to utilize GPIO controller Port 0.
config GPIO_CMSDK_AHB_PORT0_DEV_NAME
string "Device name for Port 0"
depends on GPIO_CMSDK_AHB_PORT0
default "GPIO_0"
help
Device name for Port 0.
config GPIO_CMSDK_AHB_PORT0_IRQ_PRI
int "Interrupt Priority for Port 0"
depends on GPIO_CMSDK_AHB_PORT0
default 3
help
Interrupt priority for Port 0.
# ---------- Port 1 ----------
config GPIO_CMSDK_AHB_PORT1
bool "Enable driver for GPIO Port 1"
depends on GPIO_CMSDK_AHB
default n
help
Build the driver to utilize GPIO controller Port 1.
config GPIO_CMSDK_AHB_PORT1_DEV_NAME
string "Device name for Port 1"
depends on GPIO_CMSDK_AHB_PORT1
default "GPIO_1"
help
Device name for Port 1.
config GPIO_CMSDK_AHB_PORT1_IRQ_PRI
int "Interrupt Priority for Port 1"
depends on GPIO_CMSDK_AHB_PORT1
default 3
help
Interrupt priority for Port 1.
# ---------- Port 2 ----------
config GPIO_CMSDK_AHB_PORT2
bool "Enable driver for GPIO Port 2"
depends on GPIO_CMSDK_AHB
default n
help
Build the driver to utilize GPIO controller Port 2.
config GPIO_CMSDK_AHB_PORT2_DEV_NAME
string "Device name for Port 2"
depends on GPIO_CMSDK_AHB_PORT2
default "GPIO_2"
help
Device name for Port 2.
config GPIO_CMSDK_AHB_PORT2_IRQ_PRI
int "Interrupt Priority for Port 2"
depends on GPIO_CMSDK_AHB_PORT2
default 3
help
Interrupt priority for Port 2.
# ---------- Port 3 ----------
config GPIO_CMSDK_AHB_PORT3
bool "Enable driver for GPIO Port 3"
depends on GPIO_CMSDK_AHB
default n
help
Build the driver to utilize GPIO controller Port 3.
config GPIO_CMSDK_AHB_PORT3_DEV_NAME
string "Device name for Port 3"
depends on GPIO_CMSDK_AHB_PORT3
default "GPIO_3"
help
Device name for Port 3.
config GPIO_CMSDK_AHB_PORT3_IRQ_PRI
int "Interrupt Priority for Port 3"
depends on GPIO_CMSDK_AHB_PORT3
default 3
help
Interrupt priority for Port 3.
endif # GPIO_CMSDK_AHB

1
drivers/gpio/Makefile
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@ -9,3 +9,4 @@ obj-$(CONFIG_GPIO_ATMEL_SAM3) += gpio_atmel_sam3.o
obj-$(CONFIG_GPIO_K64) += gpio_k64.o
obj-$(CONFIG_GPIO_STM32) += gpio_stm32.o
obj-$(CONFIG_GPIO_NRF5) += gpio_nrf5.o
obj-$(CONFIG_GPIO_CMSDK_AHB) += gpio_cmsdk_ahb.o

411
drivers/gpio/gpio_cmsdk_ahb.c Normal file
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@ -0,0 +1,411 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <nanokernel.h>
#include <device.h>
#include <errno.h>
#include <gpio.h>
#include <init.h>
#include <soc.h>
#include "gpio_cmsdk_ahb.h"
#include "gpio_utils.h"
/**
* @brief GPIO driver for ARM CMSDK AHB GPIO
*/
typedef void (*gpio_config_func_t)(struct device *port);
struct gpio_cmsdk_ahb_cfg {
volatile struct gpio_cmsdk_ahb *port;
gpio_config_func_t gpio_config_func;
};
struct gpio_cmsdk_ahb_dev_data {
/* list of callbacks */
sys_slist_t gpio_cb;
};
static void cmsdk_ahb_gpio_config(struct device *dev, uint32_t mask, int flags)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
/* Disable the pin and return as setup is meaningless now */
if (flags & GPIO_PIN_DISABLE) {
cfg->port->altfuncset = mask;
return;
}
/*
* Setup the pin direction
* Output Enable:
* 0 - Input
* 1 - Output
*/
if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
cfg->port->outenableset = mask;
} else {
cfg->port->outenableclr = mask;
}
/* Setup interrupt config */
if (flags & GPIO_INT) {
if (flags & GPIO_INT_DOUBLE_EDGE) {
/* FIXME: Not supported in this iteration */
} else {
/*
* Interrupt type:
* 0 - LOW or HIGH level
* 1 - For falling or rising
*/
if (flags & GPIO_INT_EDGE) {
cfg->port->inttypeclr = mask;
} else if (flags & GPIO_INT_LEVEL) {
cfg->port->inttypeset = mask;
}
/*
* Interrupt polarity:
* 0 - Low level or falling edge
* 1 - High level or rising edge
*/
if (flags & GPIO_INT_ACTIVE_LOW) {
cfg->port->intpolclr = mask;
} else if (flags & GPIO_INT_ACTIVE_HIGH) {
cfg->port->intpolset = mask;
}
}
}
/* Enable the pin last after pin setup */
if (flags & GPIO_PIN_ENABLE) {
cfg->port->altfuncclr = mask;
}
}
/**
* @brief Configure pin or port
*
* @param dev Device struct
* @param access_op Access operation (pin or port)
* @param pin The pin number
* @param flags Flags of pin or port
*
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_config(struct device *dev, int access_op,
uint32_t pin, int flags)
{
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
break;
case GPIO_ACCESS_BY_PORT:
cmsdk_ahb_gpio_config(dev, (0xFFFF), flags);
break;
default:
return -ENOTSUP;
}
return 0;
}
/**
* @brief Set the pin or port output
*
* @param dev Device struct
* @param access_op Access operation (pin or port)
* @param pin The pin number
* @param value Value to set (0 or 1)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_write(struct device *dev, int access_op,
uint32_t pin, uint32_t value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t key;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
if (value) {
/*
* The irq_lock() here is required to prevent concurrent
* callers to corrupt the pin states.
*/
key = irq_lock();
/* set the pin */
cfg->port->dataout |= BIT(pin);
irq_unlock(key);
} else {
/*
* The irq_lock() here is required to prevent concurrent
* callers to corrupt the pin states.
*/
key = irq_lock();
/* clear the pin */
cfg->port->dataout &= ~(BIT(pin));
irq_unlock(key);
}
break;
case GPIO_ACCESS_BY_PORT:
if (value) {
/* set all pins */
cfg->port->dataout = 0xFFFF;
} else {
/* clear all pins */
cfg->port->dataout = 0x0;
}
break;
default:
return -ENOTSUP;
}
return 0;
}
/**
* @brief Read the pin or port status
*
* @param dev Device struct
* @param access_op Access operation (pin or port)
* @param pin The pin number
* @param value Value of input pin(s)
*
* @return 0 if successful, failed otherwise
*/
static int gpio_cmsdk_ahb_read(struct device *dev, int access_op,
uint32_t pin, uint32_t *value)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
*value = cfg->port->data;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
*value = (*value >> pin) & 0x1;
break;
case GPIO_ACCESS_BY_PORT:
break;
default:
return -ENOTSUP;
}
return 0;
}
static void gpio_cmsdk_ahb_isr(void *arg)
{
struct device *dev = (struct device *)arg;
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
uint32_t int_stat;
int_stat = cfg->port->intstatus;
_gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);
/* clear the port interrupts */
cfg->port->intclear = 0xFFFFFFFF;
}
static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
struct gpio_callback *callback,
bool set)
{
struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
_gpio_manage_callback(&data->gpio_cb, callback, set);
return 0;
}
static int gpio_cmsdk_ahb_enable_callback(struct device *dev,
int access_op, uint32_t pin)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
mask = BIT(pin);
break;
case GPIO_ACCESS_BY_PORT:
mask = 0xFFFF;
break;
default:
return -ENOTSUP;
}
cfg->port->intenset |= mask;
return 0;
}
static int gpio_cmsdk_ahb_disable_callback(struct device *dev,
int access_op, uint32_t pin)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
uint32_t mask;
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
mask = BIT(pin);
break;
case GPIO_ACCESS_BY_PORT:
mask = 0xFFFF;
break;
default:
return -ENOTSUP;
}
cfg->port->intenclr |= mask;
return 0;
}
static const struct gpio_driver_api gpio_cmsdk_ahb_drv_api_funcs = {
.config = gpio_cmsdk_ahb_config,
.write = gpio_cmsdk_ahb_write,
.read = gpio_cmsdk_ahb_read,
.manage_callback = gpio_cmsdk_ahb_manage_callback,
.enable_callback = gpio_cmsdk_ahb_enable_callback,
.disable_callback = gpio_cmsdk_ahb_disable_callback,
};
/**
* @brief Initialization function of GPIO
*
* @param dev Device struct
* @return 0 if successful, failed otherwise.
*/
static int gpio_cmsdk_ahb_init(struct device *dev)
{
const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
cfg->gpio_config_func(dev);
return 0;
}
/* Port 0 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT0
static void gpio_cmsdk_ahb_config_0(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0),
.gpio_config_func = gpio_cmsdk_ahb_config_0,
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0,
CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_0_data,
&gpio_cmsdk_ahb_0_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_0(struct device *dev)
{
IRQ_CONNECT(IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_0), 0);
irq_enable(IRQ_PORT0_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */
/* Port 1 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT1
static void gpio_cmsdk_ahb_config_1(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1),
.gpio_config_func = gpio_cmsdk_ahb_config_1,
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1,
CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_1_data,
&gpio_cmsdk_ahb_1_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_1(struct device *dev)
{
IRQ_CONNECT(IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_1), 0);
irq_enable(IRQ_PORT1_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */
/* Port 2 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT2
static void gpio_cmsdk_ahb_config_2(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2),
.gpio_config_func = gpio_cmsdk_ahb_config_2,
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2,
CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_2_data,
&gpio_cmsdk_ahb_2_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_2(struct device *dev)
{
IRQ_CONNECT(IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_2), 0);
irq_enable(IRQ_PORT2_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */
/* Port 3 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT3
static void gpio_cmsdk_ahb_config_3(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3),
.gpio_config_func = gpio_cmsdk_ahb_config_3,
};
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data;
DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3,
CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME,
gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_3_data,
&gpio_cmsdk_ahb_3_cfg, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&gpio_cmsdk_ahb_drv_api_funcs);
static void gpio_cmsdk_ahb_config_3(struct device *dev)
{
IRQ_CONNECT(IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI,
gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_3), 0);
irq_enable(IRQ_PORT3_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */

69
drivers/gpio/gpio_cmsdk_ahb.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _DRIVERS_GPIO_CMSDK_AHB_
#define _DRIVERS_GPIO_CMSDK_AHB_
#include <gpio.h>
#ifdef __cplusplus
extern "C" {
#endif
/* ARM LTD CMSDK AHB General Purpose Input/Output (GPIO) */
struct gpio_cmsdk_ahb {
/* Offset: 0x000 (r/w) data register */
volatile uint32_t data;
/* Offset: 0x004 (r/w) data output latch register */
volatile uint32_t dataout;
volatile uint32_t reserved0[2];
/* Offset: 0x010 (r/w) output enable set register */
volatile uint32_t outenableset;
/* Offset: 0x014 (r/w) output enable clear register */
volatile uint32_t outenableclr;
/* Offset: 0x018 (r/w) alternate function set register */
volatile uint32_t altfuncset;
/* Offset: 0x01c (r/w) alternate function clear register */
volatile uint32_t altfuncclr;
/* Offset: 0x020 (r/w) interrupt enable set register */
volatile uint32_t intenset;
/* Offset: 0x024 (r/w) interrupt enable clear register */
volatile uint32_t intenclr;
/* Offset: 0x028 (r/w) interrupt type set register */
volatile uint32_t inttypeset;
/* Offset: 0x02c (r/w) interrupt type clear register */
volatile uint32_t inttypeclr;
/* Offset: 0x030 (r/w) interrupt polarity set register */
volatile uint32_t intpolset;
/* Offset: 0x034 (r/w) interrupt polarity clear register */
volatile uint32_t intpolclr;
union {
/* Offset: 0x038 (r/ ) interrupt status register */
volatile uint32_t intstatus;
/* Offset: 0x038 ( /w) interrupt clear register */
volatile uint32_t intclear;
};
volatile uint32_t reserved1[241];
/* Offset: 0x400 - 0x7fc lower byte masked access register (r/w) */
volatile uint32_t lb_masked[256];
/* Offset: 0x800 - 0xbfc upper byte masked access register (r/w) */
volatile uint32_t ub_masked[256];
};
#ifdef __cplusplus
}
#endif
#endif /* _DRIVERS_GPIO_CMSDK_AHB_ */