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arm: Restructure ARM cpu related preprocessor conditionals.

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The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices.  M0_M0PLUS,
M3_M4 and M7.  Throughout the code base we have conditional
compilation gated around these three choices.  Adjust the form of this
conditional compilation to adopt a uniform structure.  The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.

Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.

Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for.  This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.

This change is mechanical in nature involving two transforms:

1)

  #if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...

2)

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #else
  ...
  #endif

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...
  #else
  #error Unknown ARM architecture
  #endif

Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 13:18:25 +00:00 • committed by Kumar Gala
commit e2d3cc4b81
15 changed files with 166 additions and 64 deletions
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34
arch/arm/core/swap.S
View file

@ -32,9 +32,12 @@
_ASM_FILE_PROLOGUE
GTEXT(_Swap)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__svc)
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
GTEXT(__pendsv)
GDATA(_k_neg_eagain)
@ -85,12 +88,14 @@ SECTION_FUNC(TEXT, __pendsv)
mov r7, ip
/* store r8-12 */
stmea r0!, {r3-r7}
#else
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
stmia r0, {v1-v8, ip}
#ifdef CONFIG_FP_SHARING
add r0, r2, #_thread_offset_to_preempt_float
vstmia r0, {s16-s31}
#endif /* CONFIG_FP_SHARING */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
/*
@ -106,10 +111,12 @@ SECTION_FUNC(TEXT, __pendsv)
/* protect the kernel state while we play with the thread lists */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
cpsid i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
/* _kernel is still in r1 */
@ -163,7 +170,7 @@ _thread_irq_disabled:
/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
subs r0, #36
ldmia r0!, {r4-r7}
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/* restore BASEPRI for the incoming thread */
msr BASEPRI, r0
@ -175,6 +182,8 @@ _thread_irq_disabled:
/* load callee-saved + psp from TCS */
add r0, r2, #_thread_offset_to_callee_saved
ldmia r0, {v1-v8, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
msr PSP, ip
@ -182,7 +191,8 @@ _thread_irq_disabled:
/* exc return */
bx lr
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Service call handler
@ -237,7 +247,9 @@ _context_switch:
/* handler mode exit, to PendSV */
bx lr
#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
/**
*
@ -304,9 +316,11 @@ SECTION_FUNC(TEXT, _Swap)
* of a higher priority pending.
*/
cpsie i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
svc #0
#endif
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
/* coming back from exception, r2 still holds the pointer to _current */
ldr r0, [r2, #_thread_offset_to_swap_return_value]