diff --git a/arch/arm/core/cortex_m/reset.S b/arch/arm/core/cortex_m/reset.S index 631b1076639..327e4208b08 100644 --- a/arch/arm/core/cortex_m/reset.S +++ b/arch/arm/core/cortex_m/reset.S @@ -74,10 +74,12 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) /* lock interrupts: will get unlocked when switch to main task */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) cpsid i -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #ifdef CONFIG_WDOG_INIT /* board-specific watchdog initialization is necessary */ diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index 0c5390406b9..6491d65076a 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -90,7 +90,8 @@ void sys_arch_reboot(int type) DO_REBOOT(); } -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Set the number of priority groups based on the number of exception @@ -135,4 +136,6 @@ void _ScbNumPriGroupSet(unsigned int n) __scs.scb.aircr.val = reg.val; } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ diff --git a/arch/arm/core/cortex_m/vector_table.S b/arch/arm/core/cortex_m/vector_table.S index b288b3debc8..458b5c00e3f 100644 --- a/arch/arm/core/cortex_m/vector_table.S +++ b/arch/arm/core/cortex_m/vector_table.S @@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start) .word __reserved .word __reserved /* SVC not used for now (PendSV used instead) */ .word __reserved -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) .word __mpu_fault .word __bus_fault .word __usage_fault @@ -76,7 +76,9 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start) .word __reserved .word __svc .word __debug_monitor -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ .word __reserved .word __pendsv #if defined(CONFIG_CORTEX_M_SYSTICK) diff --git a/arch/arm/core/cortex_m/vector_table.h b/arch/arm/core/cortex_m/vector_table.h index 9627143b2ed..b198ea9ee39 100644 --- a/arch/arm/core/cortex_m/vector_table.h +++ b/arch/arm/core/cortex_m/vector_table.h @@ -48,13 +48,16 @@ GTEXT(_vector_table) GTEXT(__reset) GTEXT(__nmi) GTEXT(__hard_fault) -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) GTEXT(__svc) GTEXT(__debug_monitor) -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ GTEXT(__pendsv) GTEXT(__reserved) diff --git a/arch/arm/core/cpu_idle.S b/arch/arm/core/cpu_idle.S index 9a2f6aa657f..41746551b09 100644 --- a/arch/arm/core/cpu_idle.S +++ b/arch/arm/core/cpu_idle.S @@ -129,10 +129,12 @@ SECTION_FUNC(TEXT, k_cpu_idle) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) cpsie i -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* clear BASEPRI so wfi is awakened by incoming interrupts */ eors.n r0, r0 msr BASEPRI, r0 +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ wfi @@ -191,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle) cpsie i _irq_disabled: -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* r1: zero, for setting BASEPRI (needs a register) */ eors.n r1, r1 @@ -202,5 +204,7 @@ _irq_disabled: msr BASEPRI, r0 cpsie i +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ bx lr diff --git a/arch/arm/core/fault.c b/arch/arm/core/fault.c index b469cc30806..05fac4767c0 100644 --- a/arch/arm/core/fault.c +++ b/arch/arm/core/fault.c @@ -69,7 +69,8 @@ void _FaultDump(const NANO_ESF *esf, int fault) k_current_get(), esf->pc); -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) int escalation = 0; if (3 == fault) { /* hard fault */ @@ -100,7 +101,9 @@ void _FaultDump(const NANO_ESF *esf, int fault) /* clear USFR sticky bits */ _ScbUsageFaultAllFaultsReset(); -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } #endif @@ -120,7 +123,8 @@ static void _FaultThreadShow(const NANO_ESF *esf) k_current_get(), esf->pc); } -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * @@ -244,7 +248,9 @@ static void _DebugMonitor(const NANO_ESF *esf) PR_EXC("***** Debug monitor exception (not implemented) *****\n"); } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /** * @@ -260,7 +266,7 @@ static void _HardFault(const NANO_ESF *esf) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) _FaultThreadShow(esf); -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) if (_ScbHardFaultIsBusErrOnVectorRead()) { PR_EXC(" Bus fault on vector table read\n"); } else if (_ScbHardFaultIsForced()) { @@ -273,7 +279,9 @@ static void _HardFault(const NANO_ESF *esf) _UsageFault(esf); } } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } /** @@ -318,7 +326,8 @@ static void _FaultDump(const NANO_ESF *esf, int fault) case 3: _HardFault(esf); break; -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) case 4: _MpuFault(esf, 0); break; @@ -331,7 +340,9 @@ static void _FaultDump(const NANO_ESF *esf, int fault) case 12: _DebugMonitor(esf); break; -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ default: _ReservedException(esf, fault); break; @@ -376,7 +387,10 @@ void _Fault(const NANO_ESF *esf) */ void _FaultInit(void) { -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) _ScbDivByZeroFaultEnable(); -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } diff --git a/arch/arm/core/fault_s.S b/arch/arm/core/fault_s.S index 773a1d59026..4595e668ad8 100644 --- a/arch/arm/core/fault_s.S +++ b/arch/arm/core/fault_s.S @@ -32,12 +32,15 @@ _ASM_FILE_PROLOGUE GTEXT(_Fault) GTEXT(__hard_fault) -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__mpu_fault) GTEXT(__bus_fault) GTEXT(__usage_fault) GTEXT(__debug_monitor) -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ GTEXT(__reserved) /** @@ -64,12 +67,15 @@ GTEXT(__reserved) */ SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault) -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault) SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor) -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) @@ -89,7 +95,7 @@ _stack_frame_msp: mrs r0, MSP _stack_frame_endif: -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* force unlock interrupts */ eors.n r0, r0 msr BASEPRI, r0 @@ -106,6 +112,8 @@ _stack_frame_endif: mrsne r0, PSP /* if not, we are returning to thread mode, thus * this is not a nested exception: the stack * frame is on the PSP */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ push {lr} diff --git a/arch/arm/core/isr_wrapper.S b/arch/arm/core/isr_wrapper.S index 13cb69493c2..75c666d1a9d 100644 --- a/arch/arm/core/isr_wrapper.S +++ b/arch/arm/core/isr_wrapper.S @@ -88,12 +88,14 @@ SECTION_FUNC(TEXT, _isr_wrapper) blx _sys_power_save_idle_exit _idle_state_cleared: -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) ittt ne movne r1, #0 /* clear kernel idle state */ strne r1, [r2, #_kernel_offset_to_idle] blxne _sys_power_save_idle_exit +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ cpsie i /* re-enable interrupts (PRIMASK = 0) */ @@ -104,9 +106,11 @@ _idle_state_cleared: ldr r1, =16 subs r0, r1 /* get IRQ number */ lsls r0, #3 /* table is 8-byte wide */ -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) sub r0, r0, #16 /* get IRQ number */ lsl r0, r0, #3 /* table is 8-byte wide */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ ldr r1, =_sw_isr_table add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay @@ -118,8 +122,10 @@ _idle_state_cleared: #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) pop {r3} mov lr, r3 -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) pop {lr} +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* exception return is done in _IntExit() */ diff --git a/arch/arm/core/swap.S b/arch/arm/core/swap.S index 03002b5f081..1a73316c640 100644 --- a/arch/arm/core/swap.S +++ b/arch/arm/core/swap.S @@ -32,9 +32,12 @@ _ASM_FILE_PROLOGUE GTEXT(_Swap) -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) GTEXT(__svc) -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ GTEXT(__pendsv) GDATA(_k_neg_eagain) @@ -85,12 +88,14 @@ SECTION_FUNC(TEXT, __pendsv) mov r7, ip /* store r8-12 */ stmea r0!, {r3-r7} -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) stmia r0, {v1-v8, ip} #ifdef CONFIG_FP_SHARING add r0, r2, #_thread_offset_to_preempt_float vstmia r0, {s16-s31} #endif /* CONFIG_FP_SHARING */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* @@ -106,10 +111,12 @@ SECTION_FUNC(TEXT, __pendsv) /* protect the kernel state while we play with the thread lists */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) cpsid i -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) movs.n r0, #_EXC_IRQ_DEFAULT_PRIO msr BASEPRI, r0 -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* _kernel is still in r1 */ @@ -163,7 +170,7 @@ _thread_irq_disabled: /* restore r4-r7, go back 9*4 bytes to the start of the stored block */ subs r0, #36 ldmia r0!, {r4-r7} -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* restore BASEPRI for the incoming thread */ msr BASEPRI, r0 @@ -175,6 +182,8 @@ _thread_irq_disabled: /* load callee-saved + psp from TCS */ add r0, r2, #_thread_offset_to_callee_saved ldmia r0, {v1-v8, ip} +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ msr PSP, ip @@ -182,7 +191,8 @@ _thread_irq_disabled: /* exc return */ bx lr -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Service call handler @@ -237,7 +247,9 @@ _context_switch: /* handler mode exit, to PendSV */ bx lr -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /** * @@ -304,9 +316,11 @@ SECTION_FUNC(TEXT, _Swap) * of a higher priority pending. */ cpsie i -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) svc #0 -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* coming back from exception, r2 still holds the pointer to _current */ ldr r0, [r2, #_thread_offset_to_swap_return_value] diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h index 07ecfc0f1c9..df4f7d0b513 100644 --- a/arch/arm/include/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -60,8 +60,10 @@ static ALWAYS_INLINE int _IsInIsr(void) */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) return (vector > 10) || (vector == 3); -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) return (vector > 10) || (vector && _ScbIsNestedExc()); +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } diff --git a/arch/arm/include/kernel_arch_func.h b/arch/arm/include/kernel_arch_func.h index 784f1c8617e..2a4f07bff49 100644 --- a/arch/arm/include/kernel_arch_func.h +++ b/arch/arm/include/kernel_arch_func.h @@ -69,10 +69,12 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size, /* unlock interrupts */ #ifdef CONFIG_CPU_CORTEX_M0_M0PLUS "cpsie i \t\n" -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) "movs %%r1, #0 \n\t" "msr BASEPRI, %%r1 \n\t" -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* branch to _thread_entry(_main, 0, 0, 0) */ "mov %%r0, %1 \n\t" diff --git a/include/arch/arm/cortex_m/asm_inline_gcc.h b/include/arch/arm/cortex_m/asm_inline_gcc.h index e14aec0c34f..e16ee8bc28a 100644 --- a/include/arch/arm/cortex_m/asm_inline_gcc.h +++ b/include/arch/arm/cortex_m/asm_inline_gcc.h @@ -134,7 +134,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void) : "=r" (key) : : "memory"); -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) unsigned int tmp; __asm__ volatile( @@ -144,7 +144,9 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void) : "=r"(key), "=r"(tmp) : "i"(_EXC_IRQ_DEFAULT_PRIO) : "memory"); -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ return key; } @@ -176,9 +178,11 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key) return; } __asm__ volatile("cpsie i" : : : "memory"); -#else /* CONFIG_CPU_CORTEX_M3_M4 */ +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) __asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory"); -#endif +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } diff --git a/include/arch/arm/cortex_m/nvic.h b/include/arch/arm/cortex_m/nvic.h index fde98aa88c5..9d4c5c36177 100644 --- a/include/arch/arm/cortex_m/nvic.h +++ b/include/arch/arm/cortex_m/nvic.h @@ -205,8 +205,10 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio) volatile uint32_t * const ipr = &__scs.nvic.ipr[_PRIO_IP_IDX(irq)]; *ipr = ((*ipr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(irq))) | ((uint32_t)prio << _PRIO_BIT_SHIFT(irq))); -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) __scs.nvic.ipr[irq] = prio; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } @@ -225,12 +227,15 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq) { #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) return (__scs.nvic.ipr[_PRIO_IP_IDX(irq)] >> _PRIO_BIT_SHIFT(irq)); -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) return __scs.nvic.ipr[irq]; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Trigger an interrupt via software @@ -251,7 +256,9 @@ static inline void _NvicSwInterruptTrigger(unsigned int irq) __scs.stir = irq; #endif } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* !_ASMLANGUAGE */ diff --git a/include/arch/arm/cortex_m/scb.h b/include/arch/arm/cortex_m/scb.h index 1d91fc41e09..d29a19ae937 100644 --- a/include/arch/arm/cortex_m/scb.h +++ b/include/arch/arm/cortex_m/scb.h @@ -442,10 +442,12 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) __ASSERT((exc > 10) && (exc < 16), ""); return (__scs.scb.shpr[_PRIO_SHP_IDX(exc)] >> _PRIO_BIT_SHIFT(exc)); -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* For priority exception handler 4-15 */ __ASSERT((exc > 3) && (exc < 16), ""); return __scs.scb.shpr[exc - 4]; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } @@ -475,14 +477,17 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri) __ASSERT((exc > 10) && (exc < 16), ""); *shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) | ((uint32_t)pri << _PRIO_BIT_SHIFT(exc))); -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /* For priority exception handler 4-15 */ __ASSERT((exc > 3) && (exc < 16), ""); __scs.scb.shpr[exc - 4] = pri; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Find out if the currently executing exception is nested @@ -1222,7 +1227,9 @@ static inline void _ScbUsageFaultAllFaultsReset(void) __scs.scb.cfsr.byte.ufsr.val = 0xffff; } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* _ASMLANGUAGE */ diff --git a/include/arch/arm/cortex_m/scs.h b/include/arch/arm/cortex_m/scs.h index f6109766a8b..d70f21309fe 100644 --- a/include/arch/arm/cortex_m/scs.h +++ b/include/arch/arm/cortex_m/scs.h @@ -120,11 +120,13 @@ union __icsr { uint32_t rsvd__9_10_11 : 3 __packed; uint32_t vectpending : 9 __packed; uint32_t rsvd__21 : 1 __packed; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint32_t vectactive : 10 __packed; uint32_t rsvd__10 : 1 __packed; uint32_t rettobase : 1 __packed; uint32_t vectpending : 10 __packed; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ uint32_t isrpending : 1 __packed; uint32_t rsvd__23 : 1 __packed; @@ -153,17 +155,21 @@ union __aircr { struct { #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd__0 : 1 __packed; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint32_t vecreset : 1 __packed; /* WO */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ uint32_t vectclractive : 1 __packed; /* WO */ uint32_t sysresetreq : 1 __packed; /* WO */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd__3_14 : 12 __packed; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint32_t rsvd__3_7 : 5 __packed; uint32_t prigroup : 3 __packed; uint32_t rsvd__11_14 : 4 __packed; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ uint32_t endianness : 1 __packed; /* RO */ uint32_t vectkey : 16 __packed; @@ -189,18 +195,22 @@ union __ccr { struct { #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd_0_2 : 3 __packed; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint32_t nonbasethrdena : 1 __packed; uint32_t usersetmpend : 1 __packed; uint32_t rsvd__2 : 1 __packed; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ uint32_t unalign_trp : 1 __packed; #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd_4_8 : 5 __packed; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint32_t div_0_trp : 1 __packed; uint32_t rsvd__5_7 : 3 __packed; uint32_t bfhfnmign : 1 __packed; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ uint32_t stkalign : 1 __packed; uint32_t rsvd__10_31 : 22 __packed; @@ -480,9 +490,11 @@ struct __scs { #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t ipr[8]; uint32_t rsvd__420_4ff[56]; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint8_t ipr[240]; /* 0x400 Interrupt Priority Registers */ uint32_t rsvd__4f0_4ff[4]; +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } nvic; /* offset: 0x100, size 0x400 */ @@ -494,8 +506,10 @@ struct __scs { union __icsr icsr; /* 0xd04 IRQ Control and Start Register */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd_9_12; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) union __vtor vtor; /* 0xd08 Vector Table Offset Register */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ union __aircr aircr; /* 0xd0c App IRQ and Reset Control Register */ @@ -504,17 +518,19 @@ struct __scs { #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd_24_27; uint32_t shpr[2]; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers * Use ('exception number' - 4) to * get index into array */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ union __shcsr shcsr; /* 0xd24 Sys Handler Control and State Reg */ #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) uint32_t rsvd_40_63[6]; -#else +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register */ union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */ @@ -522,6 +538,8 @@ struct __scs { uint32_t mmfar; /* 0xd34 MemManage Fault Address Register */ uint32_t bfar; /* 0xd38 BusFault Address Register */ uint32_t afsr; /* 0xd3C Aux Fault Status Register */ +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ } scb; /* offset: 0xd00, size 0x040 */ @@ -576,10 +594,14 @@ extern volatile struct __scs __scs; #define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL) #define _PRIO_SHP_IDX(IRQn) ((((((uint32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL)) #define _PRIO_IP_IDX(IRQn) ((((uint32_t)(IRQn)) >> 2UL)) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) +#else +#error Unknown ARM architecture #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ /* API */ -#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) +#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7) /** * * @brief Obtain the number of interrupt lines on the target @@ -715,7 +737,9 @@ static inline void _scs_relocate_vector_table(void *new_addr) "isb\n\t" :::); } -#endif /* !CONFIG_CPU_CORTEX_M0_M0PLUS */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* _ASMLANGUAGE */