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arm: Restructure ARM cpu related preprocessor conditionals.

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The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices.  M0_M0PLUS,
M3_M4 and M7.  Throughout the code base we have conditional
compilation gated around these three choices.  Adjust the form of this
conditional compilation to adopt a uniform structure.  The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.

Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.

Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for.  This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.

This change is mechanical in nature involving two transforms:

1)

  #if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...

2)

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #else
  ...
  #endif

is transformed to:

  #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
  ...
  #elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
  ...
  #else
  #error Unknown ARM architecture
  #endif

Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 13:18:25 +00:00 • committed by Kumar Gala
commit e2d3cc4b81
15 changed files with 166 additions and 64 deletions
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8
arch/arm/core/cpu_idle.S
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@ -129,10 +129,12 @@ SECTION_FUNC(TEXT, k_cpu_idle)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
cpsie i
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
wfi
@ -191,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
cpsie i
_irq_disabled:
#else /* CONFIG_CPU_CORTEX_M3_M4 */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1
@ -202,5 +204,7 @@ _irq_disabled:
msr BASEPRI, r0
cpsie i
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
bx lr