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imx: Add EPIT peripheral support for i.MX6SoloX soc

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Add EPIT (Enhanced Periodic Interrupt Timer) peripheral support
for i.MX6SoloX soc.

Origin: Original

Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This commit is contained in:
Stanislav Poboril 2018-11-16 16:40:00 +01:00 • committed by Anas Nashif
commit e2904c8c5f
5 changed files with 72 additions and 1 deletions
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26
dts/arm/nxp/nxp_imx6sx_m4.dtsi
View file

@ -251,6 +251,32 @@
label = "MU_B"; label = "MU_B";
status = "disabled"; status = "disabled";
}; };
epit1:epit@420d0000 {
compatible = "nxp,imx-epit";
reg = <0x420d0000 0x4000>;
interrupts = <56 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "EPIT_1";
status = "disabled";
};
epit2:epit@420d4000 {
compatible = "nxp,imx-epit";
reg = <0x420d4000 0x4000>;
interrupts = <57 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "EPIT_2";
status = "disabled";
};
}; };
}; };

7
soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4
View file

@ -39,4 +39,11 @@ config IPM_IMX
endif # IPM endif # IPM
if COUNTER
config COUNTER_IMX_EPIT
default y
endif # COUNTER
endif # SOC_MCIMX6X_M4 endif # SOC_MCIMX6X_M4

1
soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc
View file

@ -13,6 +13,7 @@ config SOC_MCIMX6X_M4
bool "SOC_MCIMX6X_M4" bool "SOC_MCIMX6X_M4"
select HAS_IMX_HAL select HAS_IMX_HAL
select HAS_IMX_GPIO select HAS_IMX_GPIO
select HAS_IMX_EPIT
endchoice endchoice

12
soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h
View file

@ -101,3 +101,15 @@
#define DT_IPM_IMX_MU_B_IRQ DT_NXP_IMX_MU_4229C000_IRQ_0 #define DT_IPM_IMX_MU_B_IRQ DT_NXP_IMX_MU_4229C000_IRQ_0
#define DT_IPM_IMX_MU_B_IRQ_PRI DT_NXP_IMX_MU_4229C000_IRQ_0_PRIORITY #define DT_IPM_IMX_MU_B_IRQ_PRI DT_NXP_IMX_MU_4229C000_IRQ_0_PRIORITY
#define DT_IPM_IMX_MU_B_NAME DT_NXP_IMX_MU_4229C000_LABEL #define DT_IPM_IMX_MU_B_NAME DT_NXP_IMX_MU_4229C000_LABEL
#define DT_COUNTER_IMX_EPIT_1_BASE_ADDRESS DT_NXP_IMX_EPIT_420D0000_BASE_ADDRESS
#define DT_COUNTER_IMX_EPIT_1_IRQ DT_NXP_IMX_EPIT_420D0000_IRQ_0
#define DT_COUNTER_IMX_EPIT_1_IRQ_PRI DT_NXP_IMX_EPIT_420D0000_IRQ_0_PRIORITY
#define DT_COUNTER_IMX_EPIT_1_LABEL DT_NXP_IMX_EPIT_420D0000_LABEL
#define DT_COUNTER_IMX_EPIT_1_PRESCALER DT_NXP_IMX_EPIT_420D0000_PRESCALER
#define DT_COUNTER_IMX_EPIT_2_BASE_ADDRESS DT_NXP_IMX_EPIT_420D4000_BASE_ADDRESS
#define DT_COUNTER_IMX_EPIT_2_IRQ DT_NXP_IMX_EPIT_420D4000_IRQ_0
#define DT_COUNTER_IMX_EPIT_2_IRQ_PRI DT_NXP_IMX_EPIT_420D4000_IRQ_0_PRIORITY
#define DT_COUNTER_IMX_EPIT_2_LABEL DT_NXP_IMX_EPIT_420D4000_LABEL
#define DT_COUNTER_IMX_EPIT_2_PRESCALER DT_NXP_IMX_EPIT_420D4000_PRESCALER

27
soc/arm/nxp_imx/mcimx6x_m4/soc.c
View file

@ -78,6 +78,15 @@ static void SOC_RdcInit(void)
/* Set access to MU B for M4 core */ /* Set access to MU B for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapMuB, MU_B_RDC, false, false); RDC_SetPdapAccess(RDC, rdcPdapMuB, MU_B_RDC, false, false);
#endif /* CONFIG_IPM_IMX */ #endif /* CONFIG_IPM_IMX */
#ifdef CONFIG_COUNTER_IMX_EPIT_1
/* Set access to EPIT_1 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapEpit1, EPIT_1_RDC, false, false);
#endif /* CONFIG_COUNTER_IMX_EPIT_1 */
#ifdef CONFIG_COUNTER_IMX_EPIT_2
/* Set access to EPIT_2 for M4 core */
RDC_SetPdapAccess(RDC, rdcPdapEpit2, EPIT_2_RDC, false, false);
#endif /* CONFIG_COUNTER_IMX_EPIT_2 */
} }
/* Initialize cache. */ /* Initialize cache. */
@ -133,6 +142,22 @@ static void SOC_ClockInit(void)
CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll); CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll);
CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll); CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll);
#endif /* CONFIG_UART_IMX */ #endif /* CONFIG_UART_IMX */
#ifdef CONFIG_COUNTER_IMX_EPIT
/* Select EPIT clock is derived from OSC (24M) */
CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m);
/* Configure EPIT divider */
CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0);
/* Enable EPIT clocks */
#ifdef CONFIG_COUNTER_IMX_EPIT_1
CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll);
#endif /* CONFIG_COUNTER_IMX_EPIT_1 */
#ifdef CONFIG_COUNTER_IMX_EPIT_2
CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll);
#endif /* CONFIG_COUNTER_IMX_EPIT_2 */
#endif /* CONFIG_COUNTER_IMX_EPIT */
} }
/** /**
@ -140,7 +165,7 @@ static void SOC_ClockInit(void)
* @brief Perform basic hardware initialization * @brief Perform basic hardware initialization
* *
* Initialize the interrupt controller device drivers. * Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required. * Also initialize the counter device driver, if required.
* *
* @return 0 * @return 0
*/ */