From e2904c8c5fc0ef773a941af939444127c16c2f74 Mon Sep 17 00:00:00 2001 From: Stanislav Poboril Date: Fri, 16 Nov 2018 16:40:00 +0100 Subject: [PATCH] imx: Add EPIT peripheral support for i.MX6SoloX soc Add EPIT (Enhanced Periodic Interrupt Timer) peripheral support for i.MX6SoloX soc. Origin: Original Signed-off-by: Stanislav Poboril --- dts/arm/nxp/nxp_imx6sx_m4.dtsi | 26 ++++++++++++++++++ .../mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 | 7 +++++ soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc | 1 + soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h | 12 +++++++++ soc/arm/nxp_imx/mcimx6x_m4/soc.c | 27 ++++++++++++++++++- 5 files changed, 72 insertions(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi index b0ef2682e9a..bc7dba14218 100644 --- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi +++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi @@ -251,6 +251,32 @@ label = "MU_B"; status = "disabled"; }; + + epit1:epit@420d0000 { + compatible = "nxp,imx-epit"; + reg = <0x420d0000 0x4000>; + interrupts = <56 0>; + prescaler = <0>; + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ + RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + RDC_DOMAIN_PERM_RW))>; + label = "EPIT_1"; + status = "disabled"; + }; + + epit2:epit@420d4000 { + compatible = "nxp,imx-epit"; + reg = <0x420d4000 0x4000>; + interrupts = <57 0>; + prescaler = <0>; + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ + RDC_DOMAIN_PERM_RW)|\ + RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + RDC_DOMAIN_PERM_RW))>; + label = "EPIT_2"; + status = "disabled"; + }; }; }; diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 index f4e184e5e88..1c461699995 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 +++ b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 @@ -39,4 +39,11 @@ config IPM_IMX endif # IPM +if COUNTER + +config COUNTER_IMX_EPIT + default y + +endif # COUNTER + endif # SOC_MCIMX6X_M4 diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc index 61467e4f52e..411b4e4cf03 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc +++ b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc @@ -13,6 +13,7 @@ config SOC_MCIMX6X_M4 bool "SOC_MCIMX6X_M4" select HAS_IMX_HAL select HAS_IMX_GPIO + select HAS_IMX_EPIT endchoice diff --git a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h index 9b033a7ded5..c753441c4ed 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h +++ b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h @@ -101,3 +101,15 @@ #define DT_IPM_IMX_MU_B_IRQ DT_NXP_IMX_MU_4229C000_IRQ_0 #define DT_IPM_IMX_MU_B_IRQ_PRI DT_NXP_IMX_MU_4229C000_IRQ_0_PRIORITY #define DT_IPM_IMX_MU_B_NAME DT_NXP_IMX_MU_4229C000_LABEL + +#define DT_COUNTER_IMX_EPIT_1_BASE_ADDRESS DT_NXP_IMX_EPIT_420D0000_BASE_ADDRESS +#define DT_COUNTER_IMX_EPIT_1_IRQ DT_NXP_IMX_EPIT_420D0000_IRQ_0 +#define DT_COUNTER_IMX_EPIT_1_IRQ_PRI DT_NXP_IMX_EPIT_420D0000_IRQ_0_PRIORITY +#define DT_COUNTER_IMX_EPIT_1_LABEL DT_NXP_IMX_EPIT_420D0000_LABEL +#define DT_COUNTER_IMX_EPIT_1_PRESCALER DT_NXP_IMX_EPIT_420D0000_PRESCALER + +#define DT_COUNTER_IMX_EPIT_2_BASE_ADDRESS DT_NXP_IMX_EPIT_420D4000_BASE_ADDRESS +#define DT_COUNTER_IMX_EPIT_2_IRQ DT_NXP_IMX_EPIT_420D4000_IRQ_0 +#define DT_COUNTER_IMX_EPIT_2_IRQ_PRI DT_NXP_IMX_EPIT_420D4000_IRQ_0_PRIORITY +#define DT_COUNTER_IMX_EPIT_2_LABEL DT_NXP_IMX_EPIT_420D4000_LABEL +#define DT_COUNTER_IMX_EPIT_2_PRESCALER DT_NXP_IMX_EPIT_420D4000_PRESCALER diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/arm/nxp_imx/mcimx6x_m4/soc.c index f744aaeed6b..882b8f6ef81 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/soc.c +++ b/soc/arm/nxp_imx/mcimx6x_m4/soc.c @@ -78,6 +78,15 @@ static void SOC_RdcInit(void) /* Set access to MU B for M4 core */ RDC_SetPdapAccess(RDC, rdcPdapMuB, MU_B_RDC, false, false); #endif /* CONFIG_IPM_IMX */ + +#ifdef CONFIG_COUNTER_IMX_EPIT_1 + /* Set access to EPIT_1 for M4 core */ + RDC_SetPdapAccess(RDC, rdcPdapEpit1, EPIT_1_RDC, false, false); +#endif /* CONFIG_COUNTER_IMX_EPIT_1 */ +#ifdef CONFIG_COUNTER_IMX_EPIT_2 + /* Set access to EPIT_2 for M4 core */ + RDC_SetPdapAccess(RDC, rdcPdapEpit2, EPIT_2_RDC, false, false); +#endif /* CONFIG_COUNTER_IMX_EPIT_2 */ } /* Initialize cache. */ @@ -133,6 +142,22 @@ static void SOC_ClockInit(void) CCM_ControlGate(CCM, ccmCcgrGateUartClk, ccmClockNeededAll); CCM_ControlGate(CCM, ccmCcgrGateUartSerialClk, ccmClockNeededAll); #endif /* CONFIG_UART_IMX */ + +#ifdef CONFIG_COUNTER_IMX_EPIT + /* Select EPIT clock is derived from OSC (24M) */ + CCM_SetRootMux(CCM, ccmRootPerclkClkSel, ccmRootmuxPerclkClkOsc24m); + + /* Configure EPIT divider */ + CCM_SetRootDivider(CCM, ccmRootPerclkPodf, 0); + + /* Enable EPIT clocks */ +#ifdef CONFIG_COUNTER_IMX_EPIT_1 + CCM_ControlGate(CCM, ccmCcgrGateEpit1Clk, ccmClockNeededAll); +#endif /* CONFIG_COUNTER_IMX_EPIT_1 */ +#ifdef CONFIG_COUNTER_IMX_EPIT_2 + CCM_ControlGate(CCM, ccmCcgrGateEpit2Clk, ccmClockNeededAll); +#endif /* CONFIG_COUNTER_IMX_EPIT_2 */ +#endif /* CONFIG_COUNTER_IMX_EPIT */ } /** @@ -140,7 +165,7 @@ static void SOC_ClockInit(void) * @brief Perform basic hardware initialization * * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. + * Also initialize the counter device driver, if required. * * @return 0 */