diff --git a/arch/Kconfig b/arch/Kconfig index 3f8a95ab8bb..91f4a4ee3e5 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -85,8 +85,6 @@ config 64BIT soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid modifying it. -if ARC || ARM || NIOS2 || X86 - # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_SRAM := zephyr,sram @@ -94,17 +92,19 @@ config SRAM_SIZE int "SRAM Size in kB" default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) help - This option specifies the size of the SRAM in kB. It is normally set by - the board's defconfig file and the user should generally avoid modifying - it via the menu configuration. + The SRAM size in kB. The default value comes from /chosen/zephyr,sram in + devicetree. The user should generally avoid changing it via menuconfig or + in configuration files. config SRAM_BASE_ADDRESS hex "SRAM Base Address" default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) help - This option specifies the base address of the SRAM on the board. It is - normally set by the board's defconfig file and the user should generally - avoid modifying it via the menu configuration. + The SRAM base address. The default value comes from from + /chosen/zephyr,sram in devicetree. The user should generally avoid + changing it via menuconfig or in configuration files. + +if ARC || ARM || NIOS2 || X86 # Workaround for not being able to have commas in macro arguments DT_CHOSEN_Z_FLASH := zephyr,flash diff --git a/boards/arm/udoo_neo_full_m4/doc/index.rst b/boards/arm/udoo_neo_full_m4/doc/index.rst index 1c8f02e6801..b3b22805973 100644 --- a/boards/arm/udoo_neo_full_m4/doc/index.rst +++ b/boards/arm/udoo_neo_full_m4/doc/index.rst @@ -209,9 +209,9 @@ DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine the address where the region begins. If you want to have the data placed in the subregion of a memory, which will -likely be the case when using DDR, select "zephyr,sram=&sram" and set the -DT_SRAM_SIZE macro to determine the region size and DT_SRAM_ADDR to determine -the address where the region begins. +likely be the case when using DDR, select "zephyr,sram = &sram", which sets the +CONFIG_SRAM_SIZE macro to determine the region size and +CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins. Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined regions: diff --git a/include/arch/riscv/common/linker.ld b/include/arch/riscv/common/linker.ld index 19bd463dc0c..445357b7b58 100644 --- a/include/arch/riscv/common/linker.ld +++ b/include/arch/riscv/common/linker.ld @@ -35,7 +35,7 @@ MEMORY #ifdef CONFIG_XIP ROM (rx) : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE) #endif - RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE) + RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE) /* Used by and documented in include/linker/intlist.ld */ IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K } diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py index 3415a09d7f4..405bb84637d 100755 --- a/scripts/dts/gen_defines.py +++ b/scripts/dts/gen_defines.py @@ -68,7 +68,6 @@ def main(): out("COMPAT_{}".format(str2ident(compat)), 1) # Derived from /chosen - write_addr_size(edt, "zephyr,sram", "SRAM") write_addr_size(edt, "zephyr,ccm", "CCM") write_addr_size(edt, "zephyr,dtcm", "DTCM") write_addr_size(edt, "zephyr,ipc_shm", "IPC_SHM") diff --git a/soc/riscv/openisa_rv32m1/linker.ld b/soc/riscv/openisa_rv32m1/linker.ld index 6c582b58892..ae8269b1f5a 100644 --- a/soc/riscv/openisa_rv32m1/linker.ld +++ b/soc/riscv/openisa_rv32m1/linker.ld @@ -56,8 +56,8 @@ #endif -#define RAM_BASE DT_SRAM_BASE_ADDRESS -#define RAM_SIZE KB(DT_SRAM_SIZE) +#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS +#define RAM_SIZE KB(CONFIG_SRAM_SIZE) MEMORY { diff --git a/soc/riscv/openisa_rv32m1/soc.h b/soc/riscv/openisa_rv32m1/soc.h index 50b9023add6..8a0474a49b9 100644 --- a/soc/riscv/openisa_rv32m1/soc.h +++ b/soc/riscv/openisa_rv32m1/soc.h @@ -105,7 +105,7 @@ void soc_interrupt_init(void); #endif /* Newlib hooks (and potentially other things) use these defines. */ -#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) -#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS +#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE) +#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS #endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_H_ */ diff --git a/soc/riscv/riscv-privilege/miv/soc.h b/soc/riscv/riscv-privilege/miv/soc.h index 9fd9ca32b23..c1933a32547 100644 --- a/soc/riscv/riscv-privilege/miv/soc.h +++ b/soc/riscv/riscv-privilege/miv/soc.h @@ -55,7 +55,7 @@ #define RISCV_MTIMECMP_BASE 0x44004000 /* lib-c hooks required RAM defined variables */ -#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS -#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) +#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS +#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE) #endif /* __RISCV32_MIV_SOC_H_ */ diff --git a/soc/riscv/riscv-privilege/sifive-freedom/soc.h b/soc/riscv/riscv-privilege/sifive-freedom/soc.h index 37be403c64f..de037f1f644 100644 --- a/soc/riscv/riscv-privilege/sifive-freedom/soc.h +++ b/soc/riscv/riscv-privilege/sifive-freedom/soc.h @@ -41,7 +41,7 @@ #define SIFIVE_BACKUP_REG_BASE 0x10000080 /* lib-c hooks required RAM defined variables */ -#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS -#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE) +#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS +#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE) #endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */ diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index bf767d7001e..34e9acbebad 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -12,8 +12,8 @@ #define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE #define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY -#define DT_L2_SRAM_BASE DT_SRAM_BASE_ADDRESS -#define DT_L2_SRAM_SIZE DT_SRAM_SIZE * 1024 +#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS +#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024 #define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS #define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE