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xtensa: ADSP: fix disabling the IDC interrupt

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To disable the IDC interrupt on the interrupt controller a bit
must be set in the MSD register instead of clearing the bit in
the MCD register, which has no effect.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2021-04-01 20:36:23 +02:00 • committed by Anas Nashif
commit deb57e3b85
1 changed files with 1 additions and 1 deletions
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2
soc/xtensa/intel_adsp/common/soc_mp.c
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@ -210,7 +210,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
idc_reg = idc_read(IPC_IDCCTL, cpu_num); idc_reg = idc_read(IPC_IDCCTL, cpu_num);
idc_reg &= ~IPC_IDCCTL_IDCTBIE(0); idc_reg &= ~IPC_IDCCTL_IDCTBIE(0);
idc_write(IPC_IDCCTL, cpu_num, idc_reg); idc_write(IPC_IDCCTL, cpu_num, idc_reg);
sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 + sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x00 +
CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8); CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8);
while (start_rec.alive == 0) { while (start_rec.alive == 0) {