From deb57e3b859861124706e0c9d00c74dcaabf2aa9 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 1 Apr 2021 20:36:23 +0200 Subject: [PATCH] xtensa: ADSP: fix disabling the IDC interrupt To disable the IDC interrupt on the interrupt controller a bit must be set in the MSD register instead of clearing the bit in the MCD register, which has no effect. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/common/soc_mp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/xtensa/intel_adsp/common/soc_mp.c b/soc/xtensa/intel_adsp/common/soc_mp.c index 6a019e1ea83..d18913998ab 100644 --- a/soc/xtensa/intel_adsp/common/soc_mp.c +++ b/soc/xtensa/intel_adsp/common/soc_mp.c @@ -210,7 +210,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, idc_reg = idc_read(IPC_IDCCTL, cpu_num); idc_reg &= ~IPC_IDCCTL_IDCTBIE(0); idc_write(IPC_IDCCTL, cpu_num, idc_reg); - sys_clear_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 + + sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x00 + CAVS_ICTL_INT_CPU_OFFSET(cpu_num), 8); while (start_rec.alive == 0) {