From dc9127e93addba1c9087e8b4b611443243b7de68 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Wed, 14 Oct 2020 14:42:48 -0400 Subject: [PATCH] ipm: cavs_idc: use the IPC/IDC definitions in SoC The SoC definitions have the necessary IPC/IDC bits so there is no need to define them separately. Originally-by: Daniel Leung Signed-off-by: Daniel Leung Signed-off-by: Anas Nashif --- drivers/ipm/Kconfig | 3 ++- drivers/ipm/ipm_cavs_idc.c | 37 +++++++++++++------------- drivers/ipm/ipm_cavs_idc.h | 10 +++++++ drivers/ipm/ipm_cavs_idc_priv.h | 46 --------------------------------- 4 files changed, 31 insertions(+), 65 deletions(-) delete mode 100644 drivers/ipm/ipm_cavs_idc_priv.h diff --git a/drivers/ipm/Kconfig b/drivers/ipm/Kconfig index 89827ac1ca0..ea7c263fc60 100644 --- a/drivers/ipm/Kconfig +++ b/drivers/ipm/Kconfig @@ -101,7 +101,8 @@ config IPM_STM32_IPCC_PROCID config IPM_CAVS_IDC bool "CAVS DSP Intra-DSP Communication (IDC) driver" - depends on SMP && CAVS_ICTL + depends on IPM && CAVS_ICTL + default y if MP_NUM_CPUS > 1 && SMP help Driver for the Intra-DSP Communication (IDC) channel for cross SoC communications. diff --git a/drivers/ipm/ipm_cavs_idc.c b/drivers/ipm/ipm_cavs_idc.c index 8a9a82f25ef..2366a27693d 100644 --- a/drivers/ipm/ipm_cavs_idc.c +++ b/drivers/ipm/ipm_cavs_idc.c @@ -13,9 +13,10 @@ #include #include +#include +#include #include "ipm_cavs_idc.h" -#include "ipm_cavs_idc_priv.h" #ifdef CONFIG_SCHED_IPI_SUPPORTED extern void z_sched_ipi(void); @@ -47,15 +48,15 @@ static void cavs_idc_isr(const struct device *dev) continue; } - idctfc = idc_read(REG_IDCTFC(i), curr_cpu_id); + idctfc = idc_read(IPC_IDCTFC(i), curr_cpu_id); - if ((idctfc & REG_IDCTFC_BUSY) == 0) { + if ((idctfc & IPC_IDCTFC_BUSY) == 0) { /* No message from this core */ continue; } /* Extract the message */ - id = idctfc & REG_IDCTFC_MSG_MASK; + id = idctfc & IPC_IDCTFC_MSG_MASK; switch (id) { #ifdef CONFIG_SCHED_IPI_SUPPORTED @@ -66,16 +67,16 @@ static void cavs_idc_isr(const struct device *dev) default: if (drv_data->cb != NULL) { ext = UINT_TO_POINTER( - idc_read(REG_IDCTEFC(i), curr_cpu_id) & - REG_IDCTEFC_MSG_MASK); - drv_data->cb(dev, drv_data->user_data, id, ext); + idc_read(IPC_IDCTEFC(i), curr_cpu_id) & + IPC_IDCTEFC_MSG_MASK); + drv_data->cb(dev, drv_data->user_data, id, ext); } break; } /* Reset busy bit by writing to it */ - idctfc |= REG_IDCTFC_BUSY; - idc_write(REG_IDCTFC(i), curr_cpu_id, idctfc); + idctfc |= IPC_IDCTFC_BUSY; + idc_write(IPC_IDCTFC(i), curr_cpu_id, idctfc); } #ifdef CONFIG_SCHED_IPI_SUPPORTED if (do_sched_ipi) { @@ -105,8 +106,8 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id, continue; } - reg = idc_read(REG_IDCITC(i), curr_cpu_id); - if ((reg & REG_IDCITC_BUSY) != 0) { + reg = idc_read(IPC_IDCITC(i), curr_cpu_id); + if ((reg & IPC_IDCITC_BUSY) != 0) { busy = true; break; } @@ -117,9 +118,9 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id, return -EBUSY; } - id &= REG_IDCITC_MSG_MASK; - ext &= REG_IDCIETC_MSG_MASK; - ext |= REG_IDCIETC_DONE; /* always clear DONE bit */ + id &= IPC_IDCITC_MSG_MASK; + ext &= IPC_IDCIETC_MSG_MASK; + ext |= IPC_IDCIETC_DONE; /* always clear DONE bit */ for (i = 0; i < CONFIG_MP_NUM_CPUS; i++) { if (i == curr_cpu_id) { @@ -127,8 +128,8 @@ static int cavs_idc_send(const struct device *dev, int wait, uint32_t id, continue; } - idc_write(REG_IDCIETC(i), curr_cpu_id, ext); - idc_write(REG_IDCITC(i), curr_cpu_id, id | REG_IDCITC_BUSY); + idc_write(IPC_IDCIETC(i), curr_cpu_id, ext); + idc_write(IPC_IDCITC(i), curr_cpu_id, id | IPC_IDCITC_BUSY); } return 0; @@ -187,11 +188,11 @@ static int cavs_idc_set_enabled(const struct device *dev, int enable) continue; } - mask |= REG_IDCCTL_IDCTBIE(j); + mask |= IPC_IDCCTL_IDCTBIE(j); } } - idc_write(REG_IDCCTL, i, mask); + idc_write(IPC_IDCCTL, i, mask); /* FIXME: when we have API to enable IRQ on specific core. */ sys_set_bit(DT_REG_ADDR(DT_NODELABEL(cavs0)) + 0x04 + diff --git a/drivers/ipm/ipm_cavs_idc.h b/drivers/ipm/ipm_cavs_idc.h index 44fda68b475..e88b8c32629 100644 --- a/drivers/ipm/ipm_cavs_idc.h +++ b/drivers/ipm/ipm_cavs_idc.h @@ -33,4 +33,14 @@ #define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \ (CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U)) +static inline uint32_t idc_read(uint32_t reg, uint32_t core_id) +{ + return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)); +} + +static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val) +{ + *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val; +} + #endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */ diff --git a/drivers/ipm/ipm_cavs_idc_priv.h b/drivers/ipm/ipm_cavs_idc_priv.h deleted file mode 100644 index fefa4a01092..00000000000 --- a/drivers/ipm/ipm_cavs_idc_priv.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2020 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ -#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ - -#define IDC_REG_SIZE DT_REG_SIZE(DT_INST(0, intel_cavs_idc)) -#define IDC_REG_BASE(x) \ - (DT_REG_ADDR(DT_INST(0, intel_cavs_idc)) + x * IDC_REG_SIZE) - -#define IDC_CPU_OFFSET 0x10 - -#define REG_IDCTFC(x) (0x0 + x * IDC_CPU_OFFSET) -#define REG_IDCTEFC(x) (0x4 + x * IDC_CPU_OFFSET) -#define REG_IDCITC(x) (0x8 + x * IDC_CPU_OFFSET) -#define REG_IDCIETC(x) (0xc + x * IDC_CPU_OFFSET) -#define REG_IDCCTL 0x50 - -#define REG_IDCTFC_BUSY (1 << 31) -#define REG_IDCTFC_MSG_MASK 0x7FFFFFFF - -#define REG_IDCTEFC_MSG_MASK 0x3FFFFFFF - -#define REG_IDCITC_BUSY (1 << 31) -#define REG_IDCITC_MSG_MASK 0x7FFFFFFF - -#define REG_IDCIETC_DONE (1 << 30) -#define REG_IDCIETC_MSG_MASK 0x3FFFFFFF - -#define REG_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define REG_IDCCTL_IDCTBIE(x) (0x1 << (x)) - -static inline uint32_t idc_read(uint32_t reg, uint32_t core_id) -{ - return sys_read32(IDC_REG_BASE(core_id) + reg); -} - -static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val) -{ - sys_write32(val, IDC_REG_BASE(core_id) + reg); -} - -#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ */