diff --git a/boards/arc/hsdk/Kconfig.board b/boards/arc/hsdk/Kconfig.board new file mode 100644 index 00000000000..62254cf6082 --- /dev/null +++ b/boards/arc/hsdk/Kconfig.board @@ -0,0 +1,14 @@ +# Kconfig - DesignWare ARC HS Development Kit board configuration +# +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +config BOARD_HSDK + bool "ARC HS Development Kit" + depends on SOC_ARC_HSDK + help + The DesignWare ARC HS Development Kit is a ready-to-use platform for + rapid software development on the ARC HS3x family of processors. It + supports single- and multi-core ARC HS34, HS36 and HS38 processors + and offers a wide range of interfaces diff --git a/boards/arc/hsdk/Kconfig.defconfig b/boards/arc/hsdk/Kconfig.defconfig new file mode 100644 index 00000000000..156a116a83c --- /dev/null +++ b/boards/arc/hsdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HSDK + +config BOARD + default "hsdk" + +endif # BOARD_HSDK diff --git a/boards/arc/hsdk/board.cmake b/boards/arc/hsdk/board.cmake new file mode 100644 index 00000000000..c5df901aa16 --- /dev/null +++ b/boards/arc/hsdk/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +# TODO: can this board just use the usual openocd runner? +set(BOARD_FLASH_RUNNER em-starterkit) +set(BOARD_DEBUG_RUNNER em-starterkit) +board_finalize_runner_args(em-starterkit) diff --git a/boards/arc/hsdk/doc/hsdk.jpg b/boards/arc/hsdk/doc/hsdk.jpg new file mode 100644 index 00000000000..ff2496ef90b Binary files /dev/null and b/boards/arc/hsdk/doc/hsdk.jpg differ diff --git a/boards/arc/hsdk/doc/index.rst b/boards/arc/hsdk/doc/index.rst new file mode 100644 index 00000000000..9e74b3a2985 --- /dev/null +++ b/boards/arc/hsdk/doc/index.rst @@ -0,0 +1,208 @@ +.. _hsdk: + +DesignWare(R) ARC(R) HS Development Kit +######################################## + +Overview +******** + +The DesignWare(R) ARC(R) HS Development Kit is a ready-to-use platform for +rapid software development on the ARC HS3x family of processors. It supports +single- and multi-core ARC HS34, HS36 and HS38 processors and offers a wide +range of interfaces including Ethernet, WiFi, Bluetooth, USB, SDIO, I2C, SPI, +UART, I2S, ADC, PWM and GPIO. A Vivante GPU is also contained in the ARC +Development System SoC. This allows developers to build and debug complex +software on a comprehensive hardware platform + +.. image:: ./hsdk.jpg + :width: 442px + :align: center + :alt: DesignWare(R) ARC(R) HS Development Kit (synopsys.com) + +For details about the board, see: `ARC HS Development Kit +(IoTDK) `__ + +Hardware +******** + +For hardware feature details, refer to : +`Designware HS Development Kit website`_. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the HS Development Kit board, a few +additional pieces of hardware are required. + +* A micro USB cable provides USB-JTAG debug and USB-UART communication + to the board + +* A universal switching power adaptor (110-240V + AC to 12V DC), provided in the package, provides power to the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC HS Development Kit +================================== + +To run Zephyr application on IoT Development Kit, you need to +set up the board correctly. + +* Connect the digilent USB cable from your host to the board. + +* Connect the 12V DC power supply to your board + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the :ref:`sample applications and demos +`. We'll use :ref:`hello_world`, found in +:zephyr_file:`samples/hello_world` as an example. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``hsdk`` as the board configuration, you can select the ARC HS Development +Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: hsdk + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: hsdk + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's HS Development Kit images support +serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.10), you can debug and +flash (run) HS Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: hsdk + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +:kbd:`c` to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: hsdk + :app: + :goals: debugserver + +Then connect to the debug server at the HS Development Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the HS Development Kit's DDR +and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: hsdk + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to +HS Development Kit, but it will load the application and immediately run. If +power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +The HS Development Kit also supports flashing the Zephyr application +with the U-Boot bootloader, a powerful and flexible tool for loading +an executable from different sources and running it on the target platform. + +The U-Boot implementation for the HS Development Kit was further extended with +additional functionality that allows users to better manage the broad +configurability of the HS Development Kit + +When you are ready to deploy the program so that it boots up automatically on +reset or power-up, you can follow the steps to place the program on SD card. + +For details, see: `Uboot-HSDK-Command-Reference +`__ + + +Release Notes +************* + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware HS Development Kit website: `_ + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org diff --git a/boards/arc/hsdk/hsdk.dts b/boards/arc/hsdk/hsdk.dts new file mode 100644 index 00000000000..b45acdf4093 --- /dev/null +++ b/boards/arc/hsdk/hsdk.dts @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2019, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "hsdk"; + compatible = "snps,hsdk"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/arc/hsdk/hsdk.yaml b/boards/arc/hsdk/hsdk.yaml new file mode 100644 index 00000000000..3f6d662b1cb --- /dev/null +++ b/boards/arc/hsdk/hsdk.yaml @@ -0,0 +1,11 @@ +identifier: hsdk +name: HS Development Kit +type: mcu +arch: arc +toolchain: + - zephyr + - xtools +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/arc/hsdk/hsdk_defconfig b/boards/arc/hsdk/hsdk_defconfig new file mode 100644 index 00000000000..e873865896b --- /dev/null +++ b/boards/arc/hsdk/hsdk_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC=y +CONFIG_CPU_ARCHS=y +CONFIG_SOC_ARC_HSDK=y +CONFIG_BOARD_HSDK=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_PRINTK=y +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/hsdk/support/openocd.cfg b/boards/arc/hsdk/support/openocd.cfg new file mode 100644 index 00000000000..2a849281025 --- /dev/null +++ b/boards/arc/hsdk/support/openocd.cfg @@ -0,0 +1,111 @@ +# Copyright (C) 2019 Synopsys, Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +# Configure JTAG cable +# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that +# it uses channgel B for JTAG, instead of channel A. +interface ftdi +ftdi_vid_pid 0x0403 0x6010 +ftdi_layout_init 0x0088 0x008b +ftdi_channel 1 + + +adapter_khz 10000 + +# ARCs supports only JTAG. +transport select jtag + + +# +# HS Development Kit SoC. +# +# Contains quad-core ARC HS38. +# + +source [find cpu/arc/hs.tcl] + +set _coreid 0 +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] + +# CHIPNAME will be used to choose core family (600, 700 or EM). As far as +# OpenOCD is concerned EM and HS are identical. +set _CHIPNAME arc-em + +# OpenOCD discovers JTAG TAPs in reverse order. + +set _TARGETNAME4 $_CHIPNAME.cpu4 +jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1 +set _TARGETNAME3 $_CHIPNAME.cpu3 +jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1 +set _TARGETNAME2 $_CHIPNAME.cpu2 +jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1 +set _TARGETNAME1 $_CHIPNAME.cpu1 +jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1 + +################################ +# ARC HS38 core 1 +################################ + +target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1 +$_TARGETNAME1 configure -coreid $_coreid +$_TARGETNAME1 configure -dbgbase $_dbgbase +$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1" +set _coreid [expr $_coreid + 1] +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +arc_hs_init_regs + +# Enable L2 cache support for core 1. +$_TARGETNAME1 arc has-l2cache true + + +################################ +# ARC HS38 core 2 +################################ + +target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2 +$_TARGETNAME2 configure -coreid $_coreid +$_TARGETNAME2 configure -dbgbase $_dbgbase +$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2" +set _coreid [expr $_coreid + 1] +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +arc_hs_init_regs + +# Enable L2 cache support for core 2. +$_TARGETNAME2 arc has-l2cache true + + +################################ +# ARC HS38 core 3 +################################ + +target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3 +$_TARGETNAME3 configure -coreid $_coreid +$_TARGETNAME3 configure -dbgbase $_dbgbase +$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3" +set _coreid [expr $_coreid + 1] +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +arc_hs_init_regs + +# Enable L2 cache support for core 3. +$_TARGETNAME3 arc has-l2cache true + +################################ +# ARC HS38 core 4 +################################ + +target create $_TARGETNAME4 arcv2 -chain-position $_TARGETNAME4 +$_TARGETNAME4 configure -coreid $_coreid +$_TARGETNAME4 configure -dbgbase $_dbgbase +# Flush L2$. +$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4" +set _coreid [expr $_coreid + 1] +set _dbgbase [expr 0x00000000 | ($_coreid << 13)] +arc_hs_init_regs + +# Enable L2 cache support for core 4. +$_TARGETNAME4 arc has-l2cache true + + + +# vi:ft=tcl diff --git a/dts/arc/arc_hsdk.dtsi b/dts/arc/arc_hsdk.dtsi new file mode 100644 index 00000000000..6c606b36dad --- /dev/null +++ b/dts/arc/arc_hsdk.dtsi @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2019, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "snps,archs38"; + reg = <3>; + }; + + }; + + intc: arcv2-intc { + compatible = "snps,arcv2-intc"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + + idu_intc: idu-interrupt-controller { + compatible = "snps,archs-idu-intc"; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&idu_intc>; + ranges; + + ddr0: memory@0 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 0x80000000>; + }; + + uart0: uart@f0005000 { + compatible = "ns16550"; + clock-frequency = <33333333>; + reg = <0xf0005000 0x1000>; + label = "UART_0"; + interrupts = <30 1>; + }; + + uart1: uart@f0026000{ + compatible = "ns16550"; + clock-frequency = <33333333>; + reg = <0xf0026000 0x1000>; + label = "UART_1"; + interrupts = <46 1>; + + status = "disabled"; + }; + + uart2: uart@f0027000 { + compatible = "ns16550"; + clock-frequency = <33333333>; + reg = <0xf0027000 0x1000>; + label = "UART_2"; + interrupts = <47 1>; + + status = "disabled"; + }; + + uart3: uart@f0028000 { + compatible = "ns16550"; + clock-frequency = <33333333>; + reg = <0xf0028000 0x1000>; + label = "UART_3"; + interrupts = <48 1>; + + status = "disabled"; + }; + + gpio0: gpio@f0003000 { + compatible = "snps,designware-gpio"; + reg = <0xf0003000 0x1000>; + bits = <32>; + label = "GPIO_0"; + interrupt-parent = <&idu_intc>; + + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + i2c0: i2c@f0023000 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0023000 0x1000>; + interrupts = <43 1>; + label = "I2C_0"; + + status = "disabled"; + }; + + i2c1: i2c@f0024000 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0024000 0x1000>; + interrupts = <44 1>; + label = "I2C_1"; + + status = "disabled"; + }; + + i2c2: i2c@f0025000 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0025000 0x1000>; + interrupts = <45 1>; + label = "I2C_2"; + + status = "disabled"; + }; + + spi0: spi@f0020000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0020000 0x1000>; + interrupts = <40 1>; + label = "SPI_0"; + + status = "disabled"; + }; + + spi1: spi@f0021000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0021000 0x1000>; + interrupts = <41 1>; + label = "SPI_1"; + status = "disabled"; + }; + + spi2: spi@f0022000 { + compatible = "snps,designware-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0022000 0x1000>; + interrupts = <42 1>; + label = "SPI_1"; + status = "disabled"; + }; + + }; +}; \ No newline at end of file diff --git a/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml b/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml new file mode 100644 index 00000000000..ae3afca2bc2 --- /dev/null +++ b/dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2019, synopsys +# +# SPDX-License-Identifier: Apache-2.0 +# + +title: ARC-HS Interrupt Distribution Unit + +description: > + This binding describes the 2nd level interrupt controller can be used in + SMP configurations for dynamic IRQ routing, load balancing of + common/external IRQs towards core intc + +inherits: + !include [interrupt-controller.yaml, base.yaml] + +properties: + compatible: + constraint: "snps,archs-idu-intc" + +"#cells": + - irq + - priority diff --git a/soc/arc/snps_arc_hsdk/CMakeLists.txt b/soc/arc/snps_arc_hsdk/CMakeLists.txt new file mode 100644 index 00000000000..eb9eb660ddd --- /dev/null +++ b/soc/arc/snps_arc_hsdk/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +# -mcpu=hs38_linux includes -matomic -mcode-density -mdiv-rem +# -mswap -mnorm -mll64 -mmpy-option=9 -mfpu=fpud_all +zephyr_cc_option(-mcpu=${GCC_M_CPU}) +zephyr_cc_option(-mno-sdata) +zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpud_all) + +zephyr_sources( + soc.c + ) diff --git a/soc/arc/snps_arc_hsdk/Kconfig.defconfig b/soc/arc/snps_arc_hsdk/Kconfig.defconfig new file mode 100644 index 00000000000..b21502f52fb --- /dev/null +++ b/soc/arc/snps_arc_hsdk/Kconfig.defconfig @@ -0,0 +1,63 @@ +# +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_ARC_HSDK + +config SOC + string + default "snps_arc_hsdk" + +config CPU_HS38_LINUX + def_bool y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 2 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 88 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 500000000 + +config ARC_FIRQ + default y + +config CODE_DENSITY + default y + +config ARCV2_TIMER_IRQ_PRIORITY + default 1 + +config ARC_CONNECT + default y + +config MP_NUM_CPUS + default 4 + +if SERIAL + +config UART_NS16550 + default y + +endif # SERIAL + +if UART_CONSOLE + +config UART_NS16550_PORT_0 + default y + +config UART_NS16550_ACCESS_WORD_ONLY + default y + +endif # UART_CONSOLE + +endif # ARC_HSDK diff --git a/soc/arc/snps_arc_hsdk/Kconfig.soc b/soc/arc/snps_arc_hsdk/Kconfig.soc new file mode 100644 index 00000000000..6699a8efce0 --- /dev/null +++ b/soc/arc/snps_arc_hsdk/Kconfig.soc @@ -0,0 +1,9 @@ +# +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_ARC_HSDK + bool "Synopsys ARC HSDK SoC" + select CPU_HAS_FPU diff --git a/soc/arc/snps_arc_hsdk/dts_fixup.h b/soc/arc/snps_arc_hsdk/dts_fixup.h new file mode 100644 index 00000000000..ff7cbf9f057 --- /dev/null +++ b/soc/arc/snps_arc_hsdk/dts_fixup.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2019 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +/* + * UART configuration + */ +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0005000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0005000_IRQ_0 +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0005000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0005000_CURRENT_SPEED +#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0005000_LABEL +#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0005000_IRQ_0_PRIORITY + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_arc_hsdk/linker.ld b/soc/arc/snps_arc_hsdk/linker.ld new file mode 100644 index 00000000000..90e9bd002c8 --- /dev/null +++ b/soc/arc/snps_arc_hsdk/linker.ld @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Linker script for the HS Development Kit + */ + +#include +#include + +/* + * SRAM base address and size + */ +#if defined(CONFIG_SRAM_BASE_ADDRESS) && (CONFIG_SRAM_SIZE > 0) +#define SRAM_START CONFIG_SRAM_BASE_ADDRESS +#define SRAM_SIZE CONFIG_SRAM_SIZE +#endif + + +#include diff --git a/soc/arc/snps_arc_hsdk/soc.c b/soc/arc/snps_arc_hsdk/soc.c new file mode 100644 index 00000000000..6db3821c18c --- /dev/null +++ b/soc/arc/snps_arc_hsdk/soc.c @@ -0,0 +1,41 @@ + +/* + * Copyright (c) 2019 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * This module provides routines to initialize and support soc-level hardware + * for the HS Development Kit + */ +#include +#include +#include "soc.h" + +static int arc_hsdk_init(struct device *dev) +{ + ARG_UNUSED(dev); + + u32_t core; + u32_t i; + + /* allocate all IDU interrupts to master core */ + core = z_arc_v2_core_id(); + + z_arc_connect_idu_disable(); + + for (i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) { + z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL, + ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN); + z_arc_connect_idu_set_dest(i, 1 << core); + z_arc_connect_idu_set_mask(i, 0x0); + } + + z_arc_connect_idu_enable(); + + + return 0; +} + +SYS_INIT(arc_hsdk_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/soc/arc/snps_arc_hsdk/soc.h b/soc/arc/snps_arc_hsdk/soc.h new file mode 100644 index 00000000000..90cdfc19567 --- /dev/null +++ b/soc/arc/snps_arc_hsdk/soc.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Board configuration macros for HS Development Kit + * + * This header file is used to specify and describe board-level + * aspects for the target. + */ + +#ifndef _SOC_H_ +#define _SOC_H_ + +#include + + +/* ARC HS Core IRQs */ +#define IRQ_TIMER0 16 +#define IRQ_TIMER1 17 +#define IRQ_ICI 19 + +#define BASE_ADDR_SYSCONFIG 0xF000A000 + +#ifndef _ASMLANGUAGE + + +#include +#include + +/* + * UARTs: UART0 & UART1 & UART2 + */ +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */ +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */ +#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */ + + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_H_ */