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checkpatch: warning - block_comment_style

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Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Dan Kalowsky 2015-10-20 09:42:33 -07:00 • committed by Anas Nashif
commit da67b29569
163 changed files with 1822 additions and 1721 deletions
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6
arch/arc/core/fatal.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module implements the routines necessary for handling fatal faults on
ARCv2 CPUs.
* DESCRIPTION
* This module implements the routines necessary for handling fatal faults on
* ARCv2 CPUs.
*/
#include <nano_private.h>

29
arch/arc/core/offsets/offsets.c
View file

@ -17,21 +17,20 @@
*/
/*
DESCRIPTION
This module is responsible for the generation of the absolute symbols whose
value represents the member offsets for various ARCv2 nanokernel
structures.
All of the absolute symbols defined by this module will be present in the
final microkernel or nanokernel ELF image (due to the linker's reference to
the _OffsetAbsSyms symbol).
INTERNAL
It is NOT necessary to define the offset for every member of a structure.
Typically, only those members that are accessed by assembly language routines
are defined; however, it doesn't hurt to define all fields for the sake of
completeness.
* DESCRIPTION
* This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various ARCv2 nanokernel
* structures.
*
* All of the absolute symbols defined by this module will be present in the
* final microkernel or nanokernel ELF image (due to the linker's reference to
* the _OffsetAbsSyms symbol).
*
* INTERNAL
* It is NOT necessary to define the offset for every member of a structure.
* Typically, only those members that are accessed by assembly language routines
* are defined; however, it doesn't hurt to define all fields for the sake of
* completeness.
*/
#include <gen_offset.h>

14
arch/arc/core/prep_c.c
View file

@ -17,13 +17,13 @@
*/
/*
DESCRIPTION
Initialization of full C support: zero the .bss, copy the .data if XIP,
call _Cstart().
Stack is available in this module, but not the global data/bss until their
initialization is performed.
* DESCRIPTION
*
* Initialization of full C support: zero the .bss, copy the .data if XIP,
* call _Cstart().
*
* Stack is available in this module, but not the global data/bss until their
* initialization is performed.
*/
#include <stdint.h>

4
arch/arc/core/sys_fatal_error_handler.c
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
* DESCRIPTION
* This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
*/
#include <nanokernel.h>

28
arch/arc/core/vector_table.c
View file

@ -17,20 +17,20 @@
*/
/*
DESCRIPTION
Vector table with exceptions filled in. The reset vector is the system entry
point, ie. the first instruction executed.
The table is populated with all the system exception handlers. No exception
should not be triggered until the kernel is ready to handle them.
We are using a C file instead of an assembly file (like the ARM vector table)
to work around an issue with the assembler where:
.word <function>
statements would end up with the two half-words of the functions' addresses
swapped.
* DESCRIPTION
* Vector table with exceptions filled in. The reset vector is the system entry
* point, ie. the first instruction executed.
*
* The table is populated with all the system exception handlers. No exception
* should not be triggered until the kernel is ready to handle them.
*
* We are using a C file instead of an assembly file (like the ARM vector table)
* to work around an issue with the assembler where:
*
* .word <function>
*
* statements would end up with the two half-words of the functions' addresses
* swapped.
*/
#include <stdint.h>

21
arch/arc/include/nano_private.h
View file

@ -17,14 +17,14 @@
*/
/*
DESCRIPTION
This file contains private nanokernel structures definitions and various other
definitions for the ARCv2 processor architecture.
This file is also included by assembly language files which must #define
_ASMLANGUAGE before including this header file. Note that nanokernel assembly
source files obtains structure offset values via "absolute symbols" in the
offsets.o module.
* DESCRIPTION
* This file contains private nanokernel structures definitions and various
* other definitions for the ARCv2 processor architecture.
*
* This file is also included by assembly language files which must #define
* _ASMLANGUAGE before including this header file. Note that nanokernel
* assembly source files obtains structure offset values via "absolute
* symbols" in the offsets.o module.
*/
#ifndef _NANO_PRIVATE_H
@ -161,11 +161,12 @@ typedef struct firq_regs tFirqRegs;
struct tcs {
struct tcs *link; /* node in singly-linked list
* _nanokernel.fibers */
* _nanokernel.fibers
*/
uint32_t flags; /* bitmask of flags above */
uint32_t intlock_key; /* interrupt key when relinquishing control */
int relinquish_cause; /* one of the _CAUSE_xxxx definitions above */
unsigned int return_value; /* return value from _Swap */
unsigned int return_value;/* return value from _Swap */
int prio; /* fiber priority, -1 for a task */
#ifdef CONFIG_THREAD_CUSTOM_DATA
void *custom_data; /* available for custom use */

18
arch/arc/include/vector_table.h
View file

@ -17,15 +17,15 @@
*/
/*
DESCRIPTION
Definitions for the boot vector table.
System exception handler names all have the same format:
__<exception name with underscores>
Refer to the ARCv2 manual for an explanation of the exceptions.
* DESCRIPTION
*
* Definitions for the boot vector table.
*
* System exception handler names all have the same format:
*
* __<exception name with underscores>
*
* Refer to the ARCv2 manual for an explanation of the exceptions.
*/
#ifndef _VECTOR_TABLE__H_

8
arch/arc/platforms/generic_arc/board.h
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for the
generic arc BSP.
*/
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for the
* generic arc BSP.
*/
#ifndef _BOARD__H_
#define _BOARD__H_

20
arch/arc/platforms/generic_arc/irq_vector_table.c
View file

@ -17,16 +17,16 @@
*/
/*
DESCRIPTION
This file contains the IRQ part of the vector table. It is meant to be used
for one of two cases:
a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
binds _IsrWrapper() to all the IRQ entries in the vector table.
b) When the BSP is written so that device ISRs are installed directly in the
vector table, they are enumerated here.
*/
* DESCRIPTION
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _IsrWrapper() to all the IRQ entries in the vector table.
*
* b) When the BSP is written so that device ISRs are installed directly in the
* vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>

10
arch/arc/platforms/generic_arc/sw_isr_table.c
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
This contains the ISR table meant to be used for ISRs that take a parameter.
It is also used when ISRs are to be connected at runtime, and in this case
provides a table that is filled with _SpuriousIRQ bindings.
*/
* DESCRIPTION
* This contains the ISR table meant to be used for ISRs that take a parameter.
* It is also used when ISRs are to be connected at runtime, and in this case
* provides a table that is filled with _SpuriousIRQ bindings.
*/
#include <toolchain.h>
#include <sections.h>

8
arch/arc/platforms/generic_arc/system.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the generic arc platform.
*/
* DESCRIPTION
* This module provides routines to initialize and support board-level hardware
* for the generic arc platform.
*/
#include <nanokernel.h>
#include <board.h>

8
arch/arm/core/cortex_m/nmi.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
Provides a boot time handler that simply hangs in a sleep loop, and a run time
handler that resets the CPU. Also provides a mechanism for hooking a custom
run time handler.
* DESCRIPTION
* Provides a boot time handler that simply hangs in a sleep loop, and a run
* time handler that resets the CPU. Also provides a mechanism for hooking a
* custom run time handler.
*/
#include <nanokernel.h>

14
arch/arm/core/cortex_m/prep_c.c
View file

@ -17,13 +17,13 @@
*/
/*
DESCRIPTION
Initialization of full C support: zero the .bss, copy the .data if XIP,
call _Cstart().
Stack is available in this module, but not the global data/bss until their
initialization is performed.
* DESCRIPTION
*
* Initialization of full C support: zero the .bss, copy the .data if XIP,
* call _Cstart().
*
* Stack is available in this module, but not the global data/bss until their
* initialization is performed.
*/
#include <stdint.h>

10
arch/arm/core/cortex_m/scb.c
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
Most of the SCB interface consists of simple bit-flipping methods, and is
implemented as inline functions in scb.h. This module thus contains only data
definitions and more complex routines, if needed.
* DESCRIPTION
*
* Most of the SCB interface consists of simple bit-flipping methods, and is
* implemented as inline functions in scb.h. This module thus contains only data
* definitions and more complex routines, if needed.
*/
#include <nanokernel.h>

8
arch/arm/core/cortex_m/scs.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
Most of the SCS interface consists of simple bit-flipping methods, and is
implemented as inline functions in scs.h. This module thus contains only data
definitions and more complex routines, if needed.
* DESCRIPTION
* Most of the SCS interface consists of simple bit-flipping methods, and is
* implemented as inline functions in scs.h. This module thus contains only data
* definitions and more complex routines, if needed.
*/
#include <nanokernel.h>

18
arch/arm/core/cortex_m/vector_table.h
View file

@ -17,15 +17,15 @@
*/
/*
DESCRIPTION
Definitions for the boot vector table.
System exception handler names all have the same format:
__<exception name with underscores>
No other symbol has the same format, so they are easy to spot.
* DESCRIPTION
*
* Definitions for the boot vector table.
*
* System exception handler names all have the same format:
*
* __<exception name with underscores>
*
* No other symbol has the same format, so they are easy to spot.
*/
#ifndef _VECTOR_TABLE__H_

4
arch/arm/core/fatal.c
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
* DESCRIPTION
* This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
*/
#include <toolchain.h>

4
arch/arm/core/fault.c
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
Common fault handler for ARM Cortex-M processors.
* DESCRIPTION
* Common fault handler for ARM Cortex-M processors.
*/
#include <toolchain.h>

14
arch/arm/core/fiber_abort.c
View file

@ -17,13 +17,13 @@
*/
/*
DESCRIPTION
The ARM Cortex-M architecture provides its own fiber_abort() to deal with
different CPU modes (handler vs thread) when a fiber aborts. When its entry
point returns or when it aborts itself, the CPU is in thread mode and must
call _Swap() (which triggers a service call), but when in handler mode, the
CPU must exit handler mode to cause the context switch, and thus must queue
the PendSV exception.
* DESCRIPTION
* The ARM Cortex-M architecture provides its own fiber_abort() to deal with
* different CPU modes (handler vs thread) when a fiber aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must
* call _Swap() (which triggers a service call), but when in handler mode, the
* CPU must exit handler mode to cause the context switch, and thus must queue
* the PendSV exception.
*/
#ifdef CONFIG_MICROKERNEL

8
arch/arm/core/gdb_stub_irq_vector_table.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
When GDB is enabled, the static IRQ vector table needs to install the
_irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
user-installed ISRs.
* DESCRIPTION
* When GDB is enabled, the static IRQ vector table needs to install the
* _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
* user-installed ISRs.
*/
#include <toolchain.h>

14
arch/arm/core/irq_init.c
View file

@ -17,13 +17,13 @@
*/
/*
DESCRIPTION
The ARM Cortex-M architecture provides its own fiber_abort() to deal with
different CPU modes (handler vs thread) when a fiber aborts. When its entry
point returns or when it aborts itself, the CPU is in thread mode and must
call _Swap() (which triggers a service call), but when in handler mode, the
CPU must exit handler mode to cause the context switch, and thus must queue
the PendSV exception.
* DESCRIPTION
* The ARM Cortex-M architecture provides its own fiber_abort() to deal with
* different CPU modes (handler vs thread) when a fiber aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must
* call _Swap() (which triggers a service call), but when in handler mode, the
* CPU must exit handler mode to cause the context switch, and thus must queue
* the PendSV exception.
*/
#include <toolchain.h>

9
arch/arm/core/irq_manage.c
View file

@ -17,10 +17,11 @@
*/
/*
DESCRIPTION
Interrupt management: enabling/disabling and dynamic ISR connecting/replacing.
SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime.
* DESCRIPTION
*
* Interrupt management: enabling/disabling and dynamic ISR
* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
* connecting ISRs at runtime.
*/
#include <nanokernel.h>

29
arch/arm/core/offsets/offsets.c
View file

@ -17,21 +17,20 @@
*/
/*
DESCRIPTION
This module is responsible for the generation of the absolute symbols whose
value represents the member offsets for various ARM nanokernel
structures.
All of the absolute symbols defined by this module will be present in the
final microkernel or nanokernel ELF image (due to the linker's reference to
the _OffsetAbsSyms symbol).
INTERNAL
It is NOT necessary to define the offset for every member of a structure.
Typically, only those members that are accessed by assembly language routines
are defined; however, it doesn't hurt to define all fields for the sake of
completeness.
* DESCRIPTION
* This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various ARM nanokernel
* structures.
*
* All of the absolute symbols defined by this module will be present in the
* final microkernel or nanokernel ELF image (due to the linker's reference to
* the _OffsetAbsSyms symbol).
*
* INTERNAL
* It is NOT necessary to define the offset for every member of a structure.
* Typically, only those members that are accessed by assembly language routines
* are defined; however, it doesn't hurt to define all fields for the sake of
* completeness.
*/
#include <gen_offset.h>

5
arch/arm/core/sys_fatal_error_handler.c
View file

@ -17,8 +17,9 @@
*/
/*
DESCRIPTION
This module provides the _SysFatalErrorHandler() routine for Cortex-M platforms.
* DESCRIPTION
* This module provides the _SysFatalErrorHandler() routine for Cortex-M
* platforms.
*/
#include <nanokernel.h>

14
arch/arm/core/task_abort.c
View file

@ -17,13 +17,13 @@
*/
/*
DESCRIPTION
The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
different CPU modes (handler vs thread) when a task aborts. When its entry
point returns or when it aborts itself, the CPU is in thread mode and must
call the equivalent of task_abort(<self>), but when in handler mode, the
CPU must queue a packet to _k_server(), then exit handler mode to queue the
PendSV exception and cause the immediate context switch to _k_server.
* DESCRIPTION
* The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
* different CPU modes (handler vs thread) when a task aborts. When its entry
* point returns or when it aborts itself, the CPU is in thread mode and must
* call the equivalent of task_abort(<self>), but when in handler mode, the
* CPU must queue a packet to _k_server(), then exit handler mode to queue the
* PendSV exception and cause the immediate context switch to _k_server.
*/
#ifdef CONFIG_MICROKERNEL

11
arch/arm/core/thread.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
Core nanokernel fiber related primitives for the ARM Cortex-M processor
architecture.
* DESCRIPTION
* Core nanokernel fiber related primitives for the ARM Cortex-M processor
* architecture.
*/
#include <nanokernel.h>
@ -57,8 +57,9 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
unsigned int key;
/*
* Add the newly initialized thread to head of the list of threads. This
* singly linked list of threads maintains ALL the threads in the system:
* Add the newly initialized thread to head of the list of threads.
* This singly linked list of threads maintains ALL the threads in the
* system:
* both tasks and fibers regardless of whether they are runnable.
*/

4
arch/arm/include/cortex_m/exc.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
Exception/interrupt context helpers.
* DESCRIPTION
* Exception/interrupt context helpers.
*/
#ifndef _ARM_CORTEXM_ISR__H_

4
arch/arm/include/cortex_m/stack.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
Stack helper functions.
* DESCRIPTION
* Stack helper functions.
*/
#ifndef _ARM_CORTEXM_STACK__H_

16
arch/arm/include/nano_private.h
View file

@ -17,14 +17,14 @@
*/
/*
DESCRIPTION
This file contains private nanokernel structures definitions and various other
definitions for the ARM Cortex-M3 processor architecture.
This file is also included by assembly language files which must #define
_ASMLANGUAGE before including this header file. Note that nanokernel assembly
source files obtains structure offset values via "absolute symbols" in the
offsets.o module.
* DESCRIPTION
* This file contains private nanokernel structures definitions and various
* other definitions for the ARM Cortex-M3 processor architecture.
*
* This file is also included by assembly language files which must #define
* _ASMLANGUAGE before including this header file. Note that nanokernel
* assembly source files obtains structure offset values via "absolute symbols"
* in the offsets.o module.
*/
#ifndef _NANO_PRIVATE_H

8
arch/arm/include/start_task_arch.h
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
ARM-specific parts of start_task().
Currently empty, only here for abstraction.
* DESCRIPTION
* ARM-specific parts of start_task().
*
* Currently empty, only here for abstraction.
*/
#ifndef _START_TASK_ARCH__H_

6
arch/arm/platforms/fsl_frdm_k64f/board.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for the
'fsl_frdm_k64f' platform.
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for the
* 'fsl_frdm_k64f' platform.
*/
#ifndef _BOARD__H_

18
arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c
View file

@ -17,15 +17,15 @@
*/
/*
DESCRIPTION
This file contains the IRQ part of the vector table. It is meant to be used
for one of two cases:
a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
binds _isr_wrapper() to all the IRQ entries in the vector table.
b) When the platform is written so that device ISRs are installed directly in
the vector table, they are enumerated here.
* DESCRIPTION
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _isr_wrapper() to all the IRQ entries in the vector table.
*
* b) When the platform is written so that device ISRs are installed directly in
* the vector table, they are enumerated here.
*/
#include <toolchain.h>

29
arch/arm/platforms/fsl_frdm_k64f/system.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the fsl_frdm_k64f platform.
* DESCRIPTION
* This module provides routines to initialize and support board-level
* hardware for the fsl_frdm_k64f platform.
*/
#include <nanokernel.h>
@ -89,7 +89,8 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system clock.
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
@ -152,15 +153,19 @@ static void clkInit(void)
mcg_p->c1 = temp_reg;
/* Confirm that the external reference clock is the FLL reference source
/*
* Confirm that the external reference clock is the FLL reference
* source
*/
while ((mcg_p->s & MCG_S_IREFST_MASK) != 0)
;
;
/* Confirm the external ref. clock is the system clock source
* (MCGOUTCLK) */
/*
* Confirm the external ref. clock is the system clock source
* (MCGOUTCLK)
*/
while ((mcg_p->s & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT_REF)
;
@ -298,10 +303,14 @@ static int fsl_frdm_k64f_init(struct device *arg)
(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
clkInit(); /* Initialize PLL/system clock to 120 MHz */
/* Initialize PLL/system clock to 120 MHz */
clkInit();
NMI_INIT(); /* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise */
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);

6
arch/arm/platforms/ti_lm3s6965/board.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for
the 'ti_lm3s6965' platform.
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for
* the 'ti_lm3s6965' platform.
*/
#ifndef _BOARD__H_

18
arch/arm/platforms/ti_lm3s6965/irq_vector_table.c
View file

@ -17,15 +17,15 @@
*/
/*
DESCRIPTION
This file contains the IRQ part of the vector table. It is meant to be used
for one of two cases:
a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
binds _isr_wrapper() to all the IRQ entries in the vector table.
b) When the platform is written so that device ISRs are installed directly in
the vector table, they are enumerated here.
* DESCRIPTION
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _isr_wrapper() to all the IRQ entries in the vector table.
*
* b) When the platform is written so that device ISRs are installed directly in
* the vector table, they are enumerated here.
*/
#include <toolchain.h>

12
arch/arm/platforms/ti_lm3s6965/scp.c
View file

@ -17,12 +17,12 @@
*/
/*
DESCRIPTION
Library for controlling target-specific devices present in the 0x400fe000
peripherals memory region.
Currently, only enabling the main OSC with default value is implemented.
* DESCRIPTION
*
* Library for controlling target-specific devices present in the 0x400fe000
* peripherals memory region.
*
* Currently, only enabling the main OSC with default value is implemented.
*/
#include <stdint.h>

30
arch/arm/platforms/ti_lm3s6965/scp.h
View file

@ -17,21 +17,21 @@
*/
/*
DESCRIPTION
This module defines the System Control Peripheral Registers for TI LM3S6965
processor. The registers defined are in region 0x400fe000.
System Control 0x400fe000
These modules are not defined:
Hibernation Module 0x400fc000
Internal Memory 0x400fd000
Hibernation Module 0x400fc000
The registers and bit field names are taken from the 'Stellaris LM3S6965
Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
section 5.4/5.5, pp .184-200.
* DESCRIPTION
* This module defines the System Control Peripheral Registers for TI LM3S6965
* processor. The registers defined are in region 0x400fe000.
*
* System Control 0x400fe000
*
* These modules are not defined:
*
* Hibernation Module 0x400fc000
* Internal Memory 0x400fd000
* Hibernation Module 0x400fc000
*
* The registers and bit field names are taken from the 'Stellaris LM3S6965
* Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
* section 5.4/5.5, pp .184-200.
*/
#ifndef _SCP_H_

6
arch/arm/platforms/ti_lm3s6965/system.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the ti_lm3s6965 platform.
* DESCRIPTION
* This module provides routines to initialize and support board-level hardware
* for the ti_lm3s6965 platform.
*/
#include <nanokernel.h>

24
arch/x86/core/atomic_nolock.c
View file

@ -17,18 +17,18 @@
*/
/*
DESCRIPTION
This module provides the atomic operators for IA-32 architectures on platforms
that do not support the LOCK prefix instruction.
The atomic operations are guaranteed to be atomic with respect to interrupt
service routines. However, they are NOT guaranteed to be atomic with respect
to operations performed by peer processors, unlike the versions of these
operators that do utilize the LOCK prefix instruction.
INTERNAL
These operators are currently unavailable to user space applications
as there is no requirement for this capability.
* DESCRIPTION
* This module provides the atomic operators for IA-32 architectures on
* platforms that do not support the LOCK prefix instruction.
*
* The atomic operations are guaranteed to be atomic with respect to interrupt
* service routines. However, they are NOT guaranteed to be atomic with respect
*to operations performed by peer processors, unlike the versions of these
* operators that do utilize the LOCK prefix instruction.
*
* INTERNAL
* These operators are currently unavailable to user space applications
* as there is no requirement for this capability.
*/
#if defined(CONFIG_LOCK_INSTRUCTION_UNSUPPORTED)

4
arch/x86/core/cache.c
View file

@ -16,8 +16,8 @@
* limitations under the License.
*/
/*
DESCRIPTION
This module contains functions for manipulation caches.
* DESCRIPTION
* This module contains functions for manipulation caches.
*/
#include <nanokernel.h>

89
arch/x86/core/excconnect.c
View file

@ -17,49 +17,49 @@
*/
/*
DESCRIPTION
This module provides routines to manage exceptions (synchronous interrupts)
on the IA-32 architecture.
This module provides the public routine nanoCpuExcConnect().
INTERNAL
An exception is defined as a synchronous interrupt, i.e. an interrupt
asserted as a direct result of program execution as opposed to a
hardware device asserting an interrupt.
Many (but not all) exceptions are handled by an "exception stub" whose code
is generated by the system itself. The stub performs various actions before
and after invoking the application (or operating system) specific exception
handler; for example, a thread or ISR context save is performed prior to
invoking the exception handler.
The IA-32 code that makes up a "full" exception stub is shown below. A full
exception stub is one that pushes a dummy error code at the start of
exception processing. Exception types where the processor automatically
pushes an error code when handling an exception utilize similar exception
stubs, however the first instruction is omitted. The use of the dummy error
code means that _ExcEnt() and _ExcExit() do not have to worry about whether
an error code is present on the stack or not.
0x00 pushl $0 /@ push dummy error code @/
Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
0x05 call _ExcEnt /@ inform kernel of exception @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
0x0a call ExcHandler /@ invoke exception handler @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
/@ _ExcExit() will adjust the stack to discard the error code @/
0x0f jmp _ExcExit /@ restore thread context @/
Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE
macro to reflect the size of the full exception stub (as shown above).
The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h.
* DESCRIPTION
* This module provides routines to manage exceptions (synchronous interrupts)
* on the IA-32 architecture.
*
* This module provides the public routine nanoCpuExcConnect().
*
* INTERNAL
* An exception is defined as a synchronous interrupt, i.e. an interrupt
* asserted as a direct result of program execution as opposed to a
* hardware device asserting an interrupt.
*
* Many (but not all) exceptions are handled by an "exception stub" whose code
* is generated by the system itself. The stub performs various actions before
* and after invoking the application (or operating system) specific exception
* handler; for example, a thread or ISR context save is performed prior to
* invoking the exception handler.
*
* The IA-32 code that makes up a "full" exception stub is shown below. A full
* exception stub is one that pushes a dummy error code at the start of
* exception processing. Exception types where the processor automatically
* pushes an error code when handling an exception utilize similar exception
* stubs, however the first instruction is omitted. The use of the dummy error
* code means that _ExcEnt() and _ExcExit() do not have to worry about whether
* an error code is present on the stack or not.
*
*
* 0x00 pushl $0 /@ push dummy error code @/
* Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
*
* 0x05 call _ExcEnt /@ inform kernel of exception @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* 0x0a call ExcHandler /@ invoke exception handler @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* /@ _ExcExit() will adjust the stack to discard the error code @/
*
* 0x0f jmp _ExcExit /@ restore thread context @/
* Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
*
* NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE
* macro to reflect the size of the full exception stub (as shown above).
* The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h.
*/
@ -105,7 +105,8 @@ void _NanoCpuExcConnectAtDpl(unsigned int vector,
*/
void nanoCpuExcConnect(unsigned int vector, /* interrupt vector: 0 to 255 on
IA-32 */
* IA-32
*/
void (*routine)(NANO_ESF * pEsf),
NANO_EXC_STUB pExcStubMem)
{

4
arch/x86/core/fatal.c
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
This module provides the _NanoFatalErrorHandler() routine.
* DESCRIPTION
* This module provides the _NanoFatalErrorHandler() routine.
*/
#include <toolchain.h>

112
arch/x86/core/float.c
View file

@ -17,61 +17,63 @@
*/
/*
DESCRIPTION
This module allows multiple tasks and fibers to safely share the system's
floating point resources, by allowing the system to save FPU state information
in a task or fiber's stack region when a pre-emptive context switch occurs.
The floating point resource sharing mechanism is designed for minimal
intrusiveness. Floating point thread saving is only performed for tasks and
fibers that explicitly enable FP resource sharing, to avoid impacting the stack
size requirements of all other tasks and fibers. For those tasks and fibers
that do require FP resource sharing, a "lazy save/restore" mechanism is employed
so that the FPU's register sets are only switched in and out when absolutely
necessary; this avoids wasting effort preserving them when there is no risk
that they will be altered, or when there is no need to preserve their contents.
The following APIs are provided to allow floating point resource sharing to be
enabled or disabled at run-time:
void fiber_float_enable (nano_thread_id_t thread_id, unsigned int options)
void task_float_enable (nano_thread_id_t thread_id, unsigned int options)
void fiber_float_disable (nano_thread_id_t thread_id)
void task_float_disable (nano_thread_id_t thread_id)
The 'options' parameter is used to specify what non-integer capabilities are
being used. The same options accepted by fiber_fiber_start() are used in the
aforementioned APIs, namely USE_FP and USE_SSE.
If the nanokernel has been built without SSE instruction support
(CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
If the nanokernel has been built without floating point resource
sharing support (CONFIG_FP_SHARING), the aforementioned APIs and
capabilities do not exist.
NOTE
It is possible for a single task or fiber to utilize floating instructions
_without_ enabling the FP resource sharing feature. Since no other task or
fiber uses the FPU the FP registers won't change when the FP-capable task or
fiber isn't executing, meaning there is no need to save the registers.
WARNING
The use of floating point instructions by ISRs is not supported by the kernel.
INTERNAL
If automatic enabling of floating point resource sharing _is not_ configured
the system leaves CR0[TS] = 0 for all tasks and fibers. This means that any
task or fiber can perform floating point operations at any time without causing
an exception, and the system won't stop a task or fiber that shouldn't be
doing FP stuff from doing it.
If automatic enabling of floating point resource sharing _is_ configured the
system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to perform
FP operations. All other tasks and fibers have CR0[TS] = 1 so that an attempt
to perform an FP operation will cause an exception, allowing the system to
enable FP resource sharing on its behalf.
* DESCRIPTION
* This module allows multiple tasks and fibers to safely share the system's
* floating point resources, by allowing the system to save FPU state
* information in a task or fiber's stack region when a pre-emptive context
* switch occurs.
*
* The floating point resource sharing mechanism is designed for minimal
* intrusiveness. Floating point thread saving is only performed for tasks and
* fibers that explicitly enable FP resource sharing, to avoid impacting the
* stack size requirements of all other tasks and fibers. For those tasks and
* fibers that do require FP resource sharing, a "lazy save/restore" mechanism
* is employed so that the FPU's register sets are only switched in and out
* when absolutely necessary; this avoids wasting effort preserving them when
* there is no risk that they will be altered, or when there is no need to
* preserve their contents.
*
* The following APIs are provided to allow floating point resource sharing to
* be enabled or disabled at run-time:
*
* void fiber_float_enable (nano_thread_id_t thread_id, unsigned int options)
* void task_float_enable (nano_thread_id_t thread_id, unsigned int options)
* void fiber_float_disable (nano_thread_id_t thread_id)
* void task_float_disable (nano_thread_id_t thread_id)
*
* The 'options' parameter is used to specify what non-integer capabilities are
* being used. The same options accepted by fiber_fiber_start() are used in the
* aforementioned APIs, namely USE_FP and USE_SSE.
*
* If the nanokernel has been built without SSE instruction support
* (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
*
* If the nanokernel has been built without floating point resource sharing
* support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not
* exist.
*
* NOTE
* It is possible for a single task or fiber to utilize floating instructions
* _without_ enabling the FP resource sharing feature. Since no other task or
* fiber uses the FPU the FP registers won't change when the FP-capable task or
* fiber isn't executing, meaning there is no need to save the registers.
*
* WARNING
* The use of floating point instructions by ISRs is not supported by the
* kernel.
*
* INTERNAL
* If automatic enabling of floating point resource sharing _is not_ configured
* the system leaves CR0[TS] = 0 for all tasks and fibers. This means that any
* task or fiber can perform floating point operations at any time without
* causing an exception, and the system won't stop a task or fiber that
* shouldn't be doing FP stuff from doing it.
*
* If automatic enabling of floating point resource sharing _is_ configured
* the system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to
* perform FP operations. All other tasks and fibers have CR0[TS] = 1 so that
* an attempt to perform an FP operation will cause an exception, allowing the
* system to enable FP resource sharing on its behalf.
*/
#ifdef CONFIG_MICROKERNEL

6
arch/x86/core/gdt.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module contains routines for updating the global descriptor table (GDT)
for the IA-32 architecture.
* DESCRIPTION
* This module contains routines for updating the global descriptor table (GDT)
* for the IA-32 architecture.
*/
#include <linker-defs.h>

109
arch/x86/core/intconnect.c
View file

@ -17,60 +17,61 @@
*/
/*
DESCRIPTION
This module provides routines to manage asynchronous interrupts
on the IA-32 architecture.
This module provides the public routine irq_connect(), the private
routine _IntVecSet(), and the support routines _IntVecAlloc(),
_IntVecMarkAllocated() and _IntVecMarkFree().
INTERNAL
The _idt_base_address symbol is used to determine the base address of the IDT.
(It is generated by the linker script, and doesn't correspond to an actual
global variable.)
Interrupts are handled by an "interrupt stub" whose code is generated by the
system itself. The stub performs various actions before and after invoking
the application (or operating system) specific interrupt handler; for example,
a thread context save is performed prior to invoking the interrupt handler.
The IA-32 code that makes up a "full" interrupt stub is shown below. A full
interrupt stub is one that is associated with an interrupt vector that requires
a "beginning of interrupt" (BOI) callout and an "end of interrupt" (EOI) callout
(both of which require a parameter).
0x00 call _IntEnt /@ inform kernel of interrupt @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
0x05 pushl $BoiParameter /@ optional: push BOI handler parameter @/
Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
0x0a call BoiRoutine /@ optional: callout to BOI rtn @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
0x0f pushl $IsrParameter /@ push ISR parameter @/
Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
0x14 call IsrRoutine /@ invoke ISR @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
0x19 pushl $EoiParameter /@ optional: push EOI handler parameter @/
Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
0x1e call EoiRoutine /@ optional: callout to EOI rtn @/
Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
0x23 addl $(4 * numParams), %esp /@ pop parameters @/
Machine code: 0x83, 0xc4, (4 * numParams)
0x26 jmp _IntExit /@ restore thread or reschedule @/
Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE macro
to reflect the maximum potential size of the interrupt stub (as shown above).
The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h.
* DESCRIPTION
* This module provides routines to manage asynchronous interrupts
* on the IA-32 architecture.
*
* This module provides the public routine irq_connect(), the private
* routine _IntVecSet(), and the support routines _IntVecAlloc(),
* _IntVecMarkAllocated() and _IntVecMarkFree().
*
* INTERNAL
* The _idt_base_address symbol is used to determine the base address of the
* IDT. (It is generated by the linker script, and doesn't correspond to an
* actual global variable.)
*
* Interrupts are handled by an "interrupt stub" whose code is generated by the
* system itself. The stub performs various actions before and after invoking
* the application (or operating system) specific interrupt handler; for
* example, a thread context save is performed prior to invoking the interrupt
* handler.
*
* The IA-32 code that makes up a "full" interrupt stub is shown below. A full
* interrupt stub is one that is associated with an interrupt vector that
* requires a "beginning of interrupt" (BOI) callout and an "end of interrupt"
* (EOI) callout (both of which require a parameter).
*
* 0x00 call _IntEnt /@ inform kernel of interrupt @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* 0x05 pushl $BoiParameter /@ optional: push BOI handler parameter @/
* Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
*
* 0x0a call BoiRoutine /@ optional: callout to BOI rtn @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* 0x0f pushl $IsrParameter /@ push ISR parameter @/
* Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
*
* 0x14 call IsrRoutine /@ invoke ISR @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* 0x19 pushl $EoiParameter /@ optional: push EOI handler parameter @/
* Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
*
* 0x1e call EoiRoutine /@ optional: callout to EOI rtn @/
* Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
*
* 0x23 addl $(4 * numParams), %esp /@ pop parameters @/
* Machine code: 0x83, 0xc4, (4 * numParams)
*
* 0x26 jmp _IntExit /@ restore thread or reschedule @/
* Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
*
* NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE
* macro to reflect the maximum potential size of the interrupt stub (as shown
* above).
* The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h.
*/
#ifndef CONFIG_NO_ISRS

27
arch/x86/core/offsets/offsets.c
View file

@ -17,20 +17,19 @@
*/
/*
DESCRIPTION
This module is responsible for the generation of the absolute symbols whose
value represents the member offsets for various IA-32 nanokernel structures.
All of the absolute symbols defined by this module will be present in the
final microkernel or nanokernel ELF image (due to the linker's reference to
the _OffsetAbsSyms symbol).
INTERNAL
It is NOT necessary to define the offset for every member of a structure.
Typically, only those members that are accessed by assembly language routines
are defined; however, it doesn't hurt to define all fields for the sake of
completeness.
* DESCRIPTION
* This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets for various IA-32 nanokernel structures.
*
* All of the absolute symbols defined by this module will be present in the
* final microkernel or nanokernel ELF image (due to the linker's reference to
* the _OffsetAbsSyms symbol).
*
* INTERNAL
* It is NOT necessary to define the offset for every member of a structure.
* Typically, only those members that are accessed by assembly language routines
* are defined; however, it doesn't hurt to define all fields for the sake of
* completeness.
*/
#include <gen_offset.h> /* located in kernel/arch/common/include */

4
arch/x86/core/strtask.c
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
Intel-specific parts of start_task(). Only FP functionality currently.
* DESCRIPTION
* Intel-specific parts of start_task(). Only FP functionality currently.
*/
#ifdef CONFIG_MICROKERNEL

6
arch/x86/core/sys_fatal_error_handler.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module provides the _SysFatalErrorHandler() routine which is common to
supported platforms.
* DESCRIPTION
* This module provides the _SysFatalErrorHandler() routine which is common to
* supported platforms.
*/
#include <nanokernel.h>

9
arch/x86/core/thread.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module provides core nanokernel fiber related primitives for the IA-32
processor architecture.
* DESCRIPTION
* This module provides core nanokernel fiber related primitives for the IA-32
* processor architecture.
*/
#ifdef CONFIG_MICROKERNEL
@ -257,7 +257,8 @@ static void _new_thread_internal(char *pStackMem, unsigned stackSize,
__asm__("\t.globl _thread_entry\n"
"\t.section .text\n"
"_thread_entry_wrapper:\n" /* should place this func .S file and use
SECTION_FUNC */
* SECTION_FUNC
*/
"\tmovl $0, (%esp)\n" /* zero initialEFLAGS location */
"\tjmp _thread_entry\n");
#endif /* CONFIG_GDB_INFO */

10
arch/x86/include/advidle.h
View file

@ -16,11 +16,11 @@
* limitations under the License.
*/
/*
DESCRIPTION
This header file specifies the custom advanced idle management interface.
All of the APIs declared here must be supplied by the custom advanced idle
management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc()
and _AdvIdleStart() functions.
* DESCRIPTION
* This header file specifies the custom advanced idle management interface.
* All of the APIs declared here must be supplied by the custom advanced idle
* management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc()
* and _AdvIdleStart() functions.
*/
#ifndef __INCadvidle

6
arch/x86/include/gdt.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This file provides definitions for the Global Descriptor Table (GDT) for the
IA-32 architecture.
* DESCRIPTION
* This file provides definitions for the Global Descriptor Table (GDT) for the
* IA-32 architecture.
*/
#ifndef _GDT_H

6
arch/x86/include/idtEnt.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file provides code for constructing an IA-32 interrupt descriptor.
* DESCRIPTION
* This header file provides code for constructing an IA-32 interrupt
* descriptor.
*/
#ifndef _IDTENT_H

77
arch/x86/include/nano_private.h
View file

@ -17,17 +17,18 @@
*/
/*
DESCRIPTION
This file contains private nanokernel structures definitions and various other
definitions for the Intel Architecture 32 bit (IA-32) processor architecture.
The header include/nanokernel.h contains the public nanokernel interface
definitions, with include/arch/nanokernel/x86/arch.h supplying the
IA-32 specific portions of the public nanokernel interface.
This file is also included by assembly language files which must #define
_ASMLANGUAGE before including this header file. Note that nanokernel assembly
source files obtains structure offset values via "absolute symbols" in the
offsets.o module.
* DESCRIPTION
* This file contains private nanokernel structures definitions and various
* other definitions for the Intel Architecture 32 bit (IA-32) processor
* architecture.
* The header include/nanokernel.h contains the public nanokernel interface
* definitions, with include/arch/nanokernel/x86/arch.h supplying the
* IA-32 specific portions of the public nanokernel interface.
*
* This file is also included by assembly language files which must #define
* _ASMLANGUAGE before including this header file. Note that nanokernel
* assembly source files obtains structure offset values via "absolute symbols"
* in the offsets.o module.
*/
#ifndef _NANO_PRIVATE_H
@ -602,9 +603,10 @@ typedef struct s_coopFloatReg {
typedef struct s_preempFloatReg {
union {
tFpRegSet fpRegs; /* threads with USE_FP utilize this format */
tFpRegSetEx fpRegsEx; /* threads with USE_SSE utilize this
format */
/* threads with USE_FP utilize this format */
tFpRegSet fpRegs;
/* threads with USE_SSE utilize this format */
tFpRegSetEx fpRegsEx;
} floatRegsUnion;
} tPreempFloatReg;
@ -618,9 +620,8 @@ typedef struct s_preempFloatReg {
struct tcs {
/*
* Link to next thread in singly-linked thread list (such as
* prioritized
* list of runnable fibers, or list of fibers waiting on a nanokernel
* FIFO).
* prioritized list of runnable fibers, or list of fibers waiting on a
* nanokernel FIFO).
*/
struct tcs *link;
@ -656,8 +657,7 @@ struct tcs {
/*
* Nested exception count to maintain setting of EXC_ACTIVE flag across
* outermost exception. EXC_ACTIVE is used by _Swap() lazy FP
* save/restore
* and by debug tools.
* save/restore and by debug tools.
*/
unsigned excNestCount; /* nested exception count */
#endif /* CONFIG_FP_SHARING || CONFIG_GDB_INFO */
@ -673,19 +673,15 @@ struct tcs {
/*
* The location of all floating point related structures/fields MUST be
* located at the end of struct tcs. This way only the
*fibers/tasks
* that actually utilize non-integer capabilities need to account for
* the increased memory required for storing FP state when sizing
*stacks.
* fibers/tasks that actually utilize non-integer capabilities need to
* account for the increased memory required for storing FP state when
* sizing stacks.
*
* Given that stacks "grow down" on IA-32, and the TCS is
*located
* Given that stacks "grow down" on IA-32, and the TCS is located
* at the start of a thread's "workspace" memory, the stacks of
*fibers/tasks
* that do not utilize floating point instruction can effectively
*consume
* the memory occupied by the 'tCoopFloatReg' and 'tPreempFloatReg'
* structures without ill effect.
* fibers/tasks that do not utilize floating point instruction can
* effectively consume the memory occupied by the 'tCoopFloatReg' and
* 'tPreempFloatReg' structures without ill effect.
*/
tCoopFloatReg coopFloatReg; /* non-volatile float register storage */
@ -716,11 +712,10 @@ typedef struct s_NANO {
/*
* A 'current_sse' field does not exist in addition to the 'current_fp'
* field since it's not possible to divide the IA-32 non-integer
* registers
* into 2 distinct blocks owned by differing threads. In other words,
* given that the 'fxnsave/fxrstor' instructions save/restore both the
* X87 FPU and XMM registers, it's not possible for a thread to only
* "own" the XMM registers.
* registers into 2 distinct blocks owned by differing threads. In
* other words, given that the 'fxnsave/fxrstor' instructions
* save/restore both the X87 FPU and XMM registers, it's not possible
* for a thread to only "own" the XMM registers.
*/
struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
@ -787,16 +782,16 @@ static inline void nanoArchInit(void)
/*
* Forces the inclusion of the spurious interrupt handlers. If a
* reference
* isn't made then intconnect.o is never pulled in by the linker.
* reference isn't made then intconnect.o is never pulled in by the
* linker.
*/
_dummy_spurious_interrupt = &__isr___SpuriousIntHandler;
/*
* Forces the inclusion of the exception vector stub code. If a
* reference
* isn't made then excstubs.o is never pulled in by the linker.
* reference isn't made then excstubs.o is never pulled in by the
* linker.
*/
_dummy_exception_vector_stub = &_ExcEnt;
@ -811,8 +806,8 @@ static inline void nanoArchInit(void)
* @param fiber pointer to fiber
* @param value value to set as return value
*
* The register used to store the return value from a function call invocation is
* set to <value>. It is assumed that the specified <fiber> is pending, and
* The register used to store the return value from a function call invocation
* is set to <value>. It is assumed that the specified <fiber> is pending, and
* thus the fibers context is stored in its TCS.
*
* @return N/A

4
arch/x86/include/start_task_arch.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
Intel-specific parts of start_task(). Only FP functionality currently.
* DESCRIPTION
* Intel-specific parts of start_task(). Only FP functionality currently.
*/
#ifndef _START_TASK_ARCH__H_

16
arch/x86/include/swapstk.h
View file

@ -17,14 +17,14 @@
*/
/*
DESCRIPTION
This file details the stack frame generated by _Swap() when it saves a task
or fiber's context. This is specific to the IA-32 processor architecture.
NOTE: _Swap() does not use this file as it uses the push instruction to save a
context. Changes to the file will not automatically be picked up by _Swap().
Conversely, changes to _Swap() should be mirrored here if the stack frame is
modified.
* DESCRIPTION
* This file details the stack frame generated by _Swap() when it saves a task
* or fiber's context. This is specific to the IA-32 processor architecture.
*
* NOTE: _Swap() does not use this file as it uses the push instruction to
* save a context. Changes to the file will not automatically be picked up by
* _Swap(). Conversely, changes to _Swap() should be mirrored here if the
* stack frame is modified.
*/
#ifndef _SWAPSTK_H

6
arch/x86/platforms/galileo/board.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for
the 'galileo' platform.
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for
* the 'galileo' platform.
*/
#ifndef __INCboardh

12
arch/x86/platforms/galileo/galileo.c
View file

@ -17,12 +17,12 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the galileo platform.
Implementation Remarks:
Handlers for the secondary serial port have not been added.
* DESCRIPTION
* This module provides routines to initialize and support board-level hardware
* for the galileo platform.
*
* Implementation Remarks:
* Handlers for the secondary serial port have not been added.
*/
#include <nanokernel.h>

7
arch/x86/platforms/galileo/galileo_pinmux.c
View file

@ -552,8 +552,11 @@ uint8_t _galileo_set_pin(struct device *port, uint8_t pin, uint8_t func)
/* NUM_PIN_FUNCS being the number of alt functions */
mux_index = NUM_PIN_FUNCS * pin;
mux_index += func; /* functions are in numeric order, we can just
skip to the index needed */
/*
* functions are in numeric order, we can just skip to the index
* needed
*/
mux_index += func;
enable = &_galileo_path[mux_index];

6
arch/x86/platforms/ia32/board.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for
the 'ia32' platform.
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for
* the 'ia32' platform.
*/
#ifndef __INCboardh

6
arch/x86/platforms/ia32/ia32.c
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the ia32 platform.
* DESCRIPTION
* This module provides routines to initialize and support board-level hardware
* for the ia32 platform.
*/
#include <nanokernel.h>

6
arch/x86/platforms/ia32_pci/board.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
This header file is used to specify and describe board-level aspects for
the 'ia32_pci' platform.
* DESCRIPTION
* This header file is used to specify and describe board-level aspects for
* the 'ia32_pci' platform.
*/
#ifndef __INCboardh

12
arch/x86/platforms/ia32_pci/ia32_pci.c
View file

@ -17,12 +17,12 @@
*/
/*
DESCRIPTION
This module provides routines to initialize and support board-level hardware
for the ia32_pci platform.
Implementation Remarks:
Handlers for the secondary serial port have not been added.
* DESCRIPTION
* This module provides routines to initialize and support board-level hardware
* for the ia32_pci platform.
*
* Implementation Remarks:
* Handlers for the secondary serial port have not been added.
*/
#include <nanokernel.h>

6
drivers/adc/adc_ti_adc108s102.c
View file

@ -173,9 +173,11 @@ static void _ti_adc108s102_spi_cb(struct device *spi_dev,
static void ti_adc108s102_enable(struct device *dev)
{
/* There is nothing to be done. If there is no sampling going on,
/*
* There is nothing to be done. If there is no sampling going on,
* the chip will put itself on power-saving mode (that is because
* SPI will release CS) */
* SPI will release CS)
*/
}
static void ti_adc108s102_disable(struct device *dev)

1
drivers/bluetooth/uart.c
View file

@ -263,6 +263,7 @@ static void bt_uart_setup(struct device *uart, struct uart_init_info *info)
/* Drain the fifo */
while (uart_irq_rx_ready(uart)) {
unsigned char c;
uart_fifo_read(uart, &c, 1);
}

6
drivers/console/ipi_console_sender.c
View file

@ -29,8 +29,10 @@ static int consoleOut(int character)
return character;
}
/* We just stash the character into the id field and don't supply
* any extra data */
/*
* We just stash the character into the id field and don't supply
* any extra data
*/
ipi_send(ipi_console_device, 1, character, NULL, 0);
return character;

9
drivers/console/uart_console.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
Serial console driver.
Hooks into the printk and fputc (for printf) modules. Poll driven.
* DESCRIPTION
*
* Serial console driver.
* Hooks into the printk and fputc (for printf) modules. Poll driven.
*/
#include <nanokernel.h>
@ -51,6 +51,7 @@ static int consoleIn(void)
{
#ifdef UART_CONSOLE_DEV
unsigned char c;
if (uart_poll_in(UART_CONSOLE_DEV, &c) < 0)
return EOF;
else

6
drivers/grove/lcd_rgb.c
View file

@ -302,8 +302,10 @@ int glcd_initialize(struct device *port)
*/
/* We're here! Let's just make sure we've had enough time for the
* VDD to power on, so pause a little here, 30 ms min, so we go 50 */
/*
* We're here! Let's just make sure we've had enough time for the
* VDD to power on, so pause a little here, 30 ms min, so we go 50
*/
DBG("Grove LCD: delay 50 ms while the VDD powers on\n");
_sleep(50);

35
drivers/i2c/i2c_dw.c
View file

@ -64,9 +64,10 @@ static inline void _i2c_dw_data_ask(struct device *dev, uint8_t restart)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t data;
/* No more bytes to request */
if (dw->request_bytes == 0) {
@ -95,6 +96,7 @@ static void _i2c_dw_data_read(struct device *dev)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
@ -123,9 +125,10 @@ static void _i2c_dw_data_send(struct device *dev)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
uint32_t data = 0;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t data = 0;
/* Nothing to send anymore, mask the interrupt */
if (dw->tx_len == 0) {
@ -170,11 +173,12 @@ static inline void _i2c_dw_transfer_complete(struct device *dev)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t cb_type = 0;
uint32_t value;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
if (dw->state == I2C_DW_CMD_ERROR) {
cb_type = I2C_CB_ERROR;
} else if (dw->tx_buffer && !dw->tx_len) {
@ -200,11 +204,11 @@ void i2c_dw_isr(struct device *port)
{
struct i2c_dw_rom_config const * const rom = port->config->config_info;
struct i2c_dw_dev_config * const dw = port->driver_data;
uint32_t value = 0;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t value = 0;
#if CONFIG_SHARED_IRQ
/* If using with shared IRQ, this function will be called
* by the shared IRQ driver. So check here if the interrupt
@ -390,11 +394,12 @@ static int _i2c_dw_transfer_init(struct device *dev,
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t value = 0;
int ret;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
dw->state |= I2C_DW_BUSY;
if (write_len > 0) {
dw->state |= I2C_DW_CMD_SEND;
@ -440,9 +445,10 @@ static int i2c_dw_transfer(struct device *dev,
uint16_t slave_address, uint32_t flags)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
int ret;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
int ret;
/* First step, check if there is current activity */
if (regs->ic_status.bits.activity) {
@ -481,12 +487,13 @@ static int i2c_dw_poll_transfer(struct device *dev,
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t value = 0;
uint32_t start_time;
int ret = DEV_OK;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
if (!regs->ic_con.bits.master_mode) {
/* Only acting as master is supported */
return DEV_INVALID_OP;
@ -592,11 +599,12 @@ static int i2c_dw_runtime_configure(struct device *dev, uint32_t config)
{
struct i2c_dw_rom_config const * const rom = dev->config->config_info;
struct i2c_dw_dev_config * const dw = dev->driver_data;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
uint32_t value = 0;
uint32_t rc = DEV_OK;
volatile struct i2c_dw_registers * const regs =
(struct i2c_dw_registers *)rom->base_address;
dw->app_config.raw = config;
/* Make sure we have a supported speed for the DesignWare model */
@ -758,6 +766,7 @@ int i2c_dw_initialize(struct device *port)
{
struct i2c_dw_rom_config const * const rom = port->config->config_info;
struct i2c_dw_dev_config * const dev = port->driver_data;
volatile struct i2c_dw_registers *regs;
if (!i2c_dw_pci_setup(port)) {

8
drivers/interrupt_controller/i8259.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This module disables the Intel 8259A PIC (Programmable Interrupt Controller)
to prevent it from generating spurious interrupts.
*/
* DESCRIPTION
* This module disables the Intel 8259A PIC (Programmable Interrupt Controller)
* to prevent it from generating spurious interrupts.
*/
#include <nanokernel.h>

136
drivers/interrupt_controller/loapic_intr.c
View file

@ -17,74 +17,74 @@
*/
/*
DESCRIPTION
This module is a driver for the local APIC/xAPIC (Advanced Programmable
Interrupt Controller) in P6 (PentiumPro, II, III) family processors
and P7 (Pentium4) family processors. The local APIC/xAPIC is included
in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors.
Beginning with the P6 family processors, the presence or absence of an
on-chip local APIC can be detected using the CPUID instruction. When the
CPUID instruction is executed, bit 9 of the feature flags returned in the
EDX register indicates the presence (set) or absence (clear) of an on-chip
local APIC.
The local APIC performs two main functions for the processor:
- It processes local external interrupts that the processor receives at its
interrupt pins and local internal interrupts that software generates.
- It communicates with an external IO APIC
chip. The external IO APIC receives external interrupt events from
peripheral and direct them to the local APIC. The IO APIC is
part of Intel's system chip set.
The local APIC controls the dispatching of interrupts (to its associated
processor) that it receives either locally or from the IO APIC. It provides
facilities for queuing, nesting and masking of interrupts. It handles the
interrupt delivery protocol with its local processor and accesses to APIC
registers.
A timer on the local APIC allows local generation of interrupts, and
local interrupt pins permit local reception of processor-specific interrupts.
The local APIC can be disabled and used in conjunction with a standard 8259A
style interrupt controller. Disabling the local APIC can be done in hardware
for the Pentium processors or in software for the P6 and P7 (Pentium4) family
processors.
The local APIC in the Pentium4 processors (called the xAPIC) is an extension
of the local APIC found in the P6 family processors. The primary difference
between the APIC architecture and xAPIC architecture is that with Pentium4
processors, the local xAPICs and IO xAPIC communicate with one another through
the processors system bus; whereas, with the P6 family processors, communication
between the local APICs and the IO APIC is handled through a dedicated 3-wire
APIC bus. Also, some of the architectural features of the local APIC have been
extended and/or modified in the local xAPIC.
This driver contains three routines for use. They are:
_loapic_init() initializes the Local APIC for the interrupt mode chosen.
_loapic_enable()/disable() enables / disables the Local APIC.
Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT.
Virtual Wire Mode is one of three interrupt modes defined by the MP
specification. In this mode, interrupts are generated by the 8259A equivalent
PICs (if present) and delivered to the Boot Strap Processor by
the local APIC that is programmed to act as a "virtual Wire"; that
is, the local APIC is logically indistinguishable from a hardware
connection. This is a uniprocessor compatibility mode.
The local and IO APICs support interrupts in the range of 32 to 255.
Interrupt priority is implied by its vector, according to the following
relationship: "priority = vector / 16".
Here the quotient is rounded down to the nearest integer value to determine
the priority, with 1 being the lowest and 15 is the highest. Because vectors
0 through 31 are reserved for exclusive use by the processor, the priority of
user defined interrupts range from 2 to 15. A value of 15 in the Interrupt
Class field of the Task Priority Register (TPR) will mask off all interrupts,
which require interrupt service.
The P6 family processor's local APIC includes an in-service entry and a holding
entry for each priority level. To avoid losing interrupts, software should
allocate no more than 2 interrupt vectors per priority. The Pentium4 processor
expands this support of all acceptance of two interrupts per vector rather than
per priority level.
INCLUDE FILES: loapic.h
* DESCRIPTION
* This module is a driver for the local APIC/xAPIC (Advanced Programmable
* Interrupt Controller) in P6 (PentiumPro, II, III) family processors
* and P7 (Pentium4) family processors. The local APIC/xAPIC is included
* in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors.
* Beginning with the P6 family processors, the presence or absence of an
* on-chip local APIC can be detected using the CPUID instruction. When the
* CPUID instruction is executed, bit 9 of the feature flags returned in the
* EDX register indicates the presence (set) or absence (clear) of an on-chip
* local APIC.
*
* The local APIC performs two main functions for the processor:
* - It processes local external interrupts that the processor receives at its
* interrupt pins and local internal interrupts that software generates.
* - It communicates with an external IO APIC
* chip. The external IO APIC receives external interrupt events from
* peripheral and direct them to the local APIC. The IO APIC is
* part of Intel's system chip set.
* The local APIC controls the dispatching of interrupts (to its associated
* processor) that it receives either locally or from the IO APIC. It provides
* facilities for queuing, nesting and masking of interrupts. It handles the
* interrupt delivery protocol with its local processor and accesses to APIC
* registers.
* A timer on the local APIC allows local generation of interrupts, and
* local interrupt pins permit local reception of processor-specific interrupts.
* The local APIC can be disabled and used in conjunction with a standard 8259A
* style interrupt controller. Disabling the local APIC can be done in hardware
* for the Pentium processors or in software for the P6 and P7 (Pentium4) family
* processors.
*
* The local APIC in the Pentium4 processors (called the xAPIC) is an extension
* of the local APIC found in the P6 family processors. The primary difference
* between the APIC architecture and xAPIC architecture is that with Pentium4
* processors, the local xAPICs and IO xAPIC communicate with one another
* through the processors system bus; whereas, with the P6 family processors,
* communication between the local APICs and the IO APIC is handled through a
* dedicated 3-wire APIC bus. Also, some of the architectural features of the
* local APIC have been extended and/or modified in the local xAPIC.
*
* This driver contains three routines for use. They are:
* _loapic_init() initializes the Local APIC for the interrupt mode chosen.
* _loapic_enable()/disable() enables / disables the Local APIC.
*
* Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT.
*
* Virtual Wire Mode is one of three interrupt modes defined by the MP
* specification. In this mode, interrupts are generated by the 8259A
* equivalent PICs (if present) and delivered to the Boot Strap Processor by
* the local APIC that is programmed to act as a "virtual Wire"; that
* is, the local APIC is logically indistinguishable from a hardware
* connection. This is a uniprocessor compatibility mode.
*
* The local and IO APICs support interrupts in the range of 32 to 255.
* Interrupt priority is implied by its vector, according to the following
* relationship: "priority = vector / 16".
* Here the quotient is rounded down to the nearest integer value to determine
* the priority, with 1 being the lowest and 15 is the highest. Because vectors
* 0 through 31 are reserved for exclusive use by the processor, the priority of
* user defined interrupts range from 2 to 15. A value of 15 in the Interrupt
* Class field of the Task Priority Register (TPR) will mask off all interrupts,
* which require interrupt service.
* The P6 family processor's local APIC includes an in-service entry and a
* holding entry for each priority level. To avoid losing interrupts, software
* should allocate no more than 2 interrupt vectors per priority. The Pentium4
* processor expands this support of all acceptance of two interrupts per vector
* rather than per priority level.
*
* INCLUDE FILES: loapic.h
*/
#include <nanokernel.h>

6
drivers/interrupt_controller/system_apic.c
View file

@ -143,8 +143,10 @@ int _SysIntVecAlloc(unsigned int irq, unsigned int priority,
} else {
_loapic_int_vec_set(irq - CONFIG_IOAPIC_NUM_RTES, vector);
/* specify that the EOI handler in loApicIntr.c driver
* be invoked */
/*
* specify that the EOI handler in loApicIntr.c driver
* be invoked
*/
*eoiRtn = (NANO_EOI_GET_FUNC)_loapic_eoi;
*eoiParamRequired = 0;

121
drivers/pci/pci.c
View file

@ -17,67 +17,66 @@
*/
/*
DESCRIPTION
Module implements routines for PCI bus initialization and query.
USAGE
To use the driver, the platform must define:
- Numbers of BUSes:
- PCI_BUS_NUMBERS;
- Register addresses:
- PCI_CTRL_ADDR_REG;
- PCI_CTRL_DATA_REG;
- pci_pin2irq() - the routine that converts the PCI interrupt pin
number to IRQ number.
About scanning the PCI buses:
At every new usage of this API, the code should call pci_bus_scan_init().
It should own a struct pci_dev_info, filled in with the parameters it is
interested to look for: class and/or vendor_id/device_id.
Then it can loop on pci_bus_scan() providing a pointer on that structure.
Such function can be called as long as it returns 1. At every successful
return of pci_bus_scan() it means the provided structure pointer will have
been updated with the current scan result which the code might be interested
in. On pci_bus_scan() returning 0, the code should discard the result and
stop calling pci_bus_scan(). If it wants to retrieve the result, it will
have to restart the procedure all over again.
EXAMPLE
struct pci_dev_info info = {
.class = PCI_CLASS_COMM_CTLR
};
pci_bus_scan_init();
while (pci_bus_scan(&info) {
// do something with "info" which holds a valid result, i.e. some
// device information matching the PCI class PCI_CLASS_COMM_CTLR
}
INTERNALS
The whole logic runs around a structure: struct lookup_data, which exists
on one instanciation called 'lookup'.
Such structure is used for 2 distinct roles:
- to match devices the caller is looking for
- to loop on PCI bus, devices, function and BARs
The search criterias are the class and/or the vendor_id/device_id of a PCI
device. The caller first initializes the lookup structure by calling
pci_bus_scan_init(), which will reset the search criterias as well as the
loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
the lookup structure will store the search criterias. Then the loop starts.
For each bus it will run through each device on which it will loop on each
function and BARs, as long as the criterias does not match or until it hit
the limit of bus/dev/functions to scan.
On a successful match, it will stop the loop, fill in the caller's
pci_dev_info structure with the found device information, and return 1.
Hopefully, the lookup structure still remembers where it stopped and the
original search criterias. Thus, when the caller asks to scan again for
a possible result next, the loop will restart where it stopped.
That will work as long as there are relevant results found.
* DESCRIPTION
* Module implements routines for PCI bus initialization and query.
*
* USAGE
* To use the driver, the platform must define:
* - Numbers of BUSes:
* - PCI_BUS_NUMBERS;
* - Register addresses:
* - PCI_CTRL_ADDR_REG;
* - PCI_CTRL_DATA_REG;
* - pci_pin2irq() - the routine that converts the PCI interrupt pin
* number to IRQ number.
*
* About scanning the PCI buses:
* At every new usage of this API, the code should call pci_bus_scan_init().
* It should own a struct pci_dev_info, filled in with the parameters it is
* interested to look for: class and/or vendor_id/device_id.
*
* Then it can loop on pci_bus_scan() providing a pointer on that structure.
* Such function can be called as long as it returns 1. At every successful
* return of pci_bus_scan() it means the provided structure pointer will have
* been updated with the current scan result which the code might be interested
* in. On pci_bus_scan() returning 0, the code should discard the result and
* stop calling pci_bus_scan(). If it wants to retrieve the result, it will
* have to restart the procedure all over again.
*
* EXAMPLE
* struct pci_dev_info info = {
* .class = PCI_CLASS_COMM_CTLR
* };
*
* pci_bus_scan_init();
*
* while (pci_bus_scan(&info) {
* // do something with "info" which holds a valid result, i.e. some
* // device information matching the PCI class PCI_CLASS_COMM_CTLR
* }
*
* INTERNALS
* The whole logic runs around a structure: struct lookup_data, which exists
* on one instanciation called 'lookup'.
* Such structure is used for 2 distinct roles:
* - to match devices the caller is looking for
* - to loop on PCI bus, devices, function and BARs
*
* The search criterias are the class and/or the vendor_id/device_id of a PCI
* device. The caller first initializes the lookup structure by calling
* pci_bus_scan_init(), which will reset the search criterias as well as the
* loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
* the lookup structure will store the search criterias. Then the loop starts.
* For each bus it will run through each device on which it will loop on each
* function and BARs, as long as the criterias does not match or until it hit
* the limit of bus/dev/functions to scan.
*
* On a successful match, it will stop the loop, fill in the caller's
* pci_dev_info structure with the found device information, and return 1.
* Hopefully, the lookup structure still remembers where it stopped and the
* original search criterias. Thus, when the caller asks to scan again for
* a possible result next, the loop will restart where it stopped.
* That will work as long as there are relevant results found.
*/
#include <nanokernel.h>

8
drivers/pci/pci_config.c
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This module implements the PCI config space access functions
* DESCRIPTION
*
* This module implements the PCI config space access functions
*
*/
#include <nanokernel.h>

7
drivers/pci/pci_interface.c
View file

@ -17,10 +17,9 @@
*/
/*
DESCRIPTION
This module implements the PCI H/W access functions.
* DESCRIPTION
*
* This module implements the PCI H/W access functions.
*/
#include <nanokernel.h>

10
drivers/pci/pci_legacy_bridge.c
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
Module provides routines for utilizing the PCI legacy bridge, including
detection of the bridge and using the bridge to configure the routing between
PCI interrupt pins and IRQs.
*/
* DESCRIPTION
* Module provides routines for utilizing the PCI legacy bridge, including
* detection of the bridge and using the bridge to configure the routing between
* PCI interrupt pins and IRQs.
*/
#include <nanokernel.h>
#include <arch/cpu.h>

10
drivers/random/rand32_timer.c
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
This module provides a non-random implementation of sys_rand32_get(), which is
not meant to be used in a final product as a truly random number generator. It
was provided to allow testing on a platform that does not (yet) provide a
random number generator.
* DESCRIPTION
* This module provides a non-random implementation of sys_rand32_get(), which
* is not meant to be used in a final product as a truly random number
* generator. It was provided to allow testing on a platform that does not (yet)
* provide a random number generator.
*/
#include <drivers/rand32.h>

10
drivers/random/rand32_timestamp.c
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
This module provides a non-random implementation of sys_rand32_get(), which is
not meant to be used in a final product as a truly random number generator. It
was provided to allow testing on a platform that does not (yet) provide a
random number generator.
* DESCRIPTION
* This module provides a non-random implementation of sys_rand32_get(), which
* is not meant to be used in a final product as a truly random number
* generator. It was provided to allow testing on a platform that does not (yet)
* provide a random number generator.
*/
#include <nanokernel.h>

12
drivers/serial/stellarisUartDrv.c
View file

@ -163,15 +163,19 @@ static void baudrate_set(struct device *dev,
div = (16 * baudrate);
rem = sys_clk_freq_hz % div;
/* floating part of baud rate (LM3S6965 p.433), equivalent to
* [float part of (SYSCLK / div)] * 64 + 0.5 */
/*
* floating part of baud rate (LM3S6965 p.433), equivalent to
* [float part of (SYSCLK / div)] * 64 + 0.5
*/
brdf = ((((rem * 64) << 1) / div) + 1) >> 1;
/* integer part of baud rate (LM3S6965 p.433) */
brdi = sys_clk_freq_hz / div;
/* those registers are 32-bit, but the reserved bits should be
* preserved */
/*
* those registers are 32-bit, but the reserved bits should be
* preserved
*/
uart->ibrd = (uint16_t)(brdi & 0xffff); /* 16 bits */
uart->fbrd = (uint8_t)(brdf & 0x3f); /* 6 bits */
}

1
drivers/simple/uart.c
View file

@ -82,6 +82,7 @@ static void uart_simple_setup(struct device *uart, struct uart_init_info *info)
/* Drain the fifo */
while (uart_irq_rx_ready(uart)) {
unsigned char c;
uart_fifo_read(uart, &c, 1);
}

13
drivers/timer/arcv2_timer0.c
View file

@ -17,12 +17,13 @@
*/
/*
DESCRIPTION
This module implements a kernel device driver for the ARCv2 processor timer 0
and provides the standard "system clock driver" interfaces.
\INTERNAL IMPLEMENTATION DETAILS
The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero counter.
* DESCRIPTION
* This module implements a kernel device driver for the ARCv2 processor timer 0
* and provides the standard "system clock driver" interfaces.
*
* \INTERNAL IMPLEMENTATION DETAILS
* The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero
* counter.
*/
#include <nanokernel.h>

51
drivers/timer/cortex_m_systick.c
View file

@ -17,24 +17,24 @@
*/
/*
DESCRIPTION
This module implements the kernel's CORTEX-M ARM's systick device driver.
It provides the standard kernel "system clock driver" interfaces.
The driver utilizes systick to provide kernel ticks.
\INTERNAL IMPLEMENTATION DETAILS
The systick device provides a 24-bit clear-on-write, decrementing,
wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
\INTERNAL PACKAGING DETAILS
The systick device driver is part of the microkernel in both a monolithic kernel
system and a split kernel system; it is not included in the nanokernel portion
of a split kernel.
The device driver is also part of a nanokernel-only system, but omits more
complex capabilities (such as tickless idle support) that are only used in
conjunction with a microkernel.
* DESCRIPTION
* This module implements the kernel's CORTEX-M ARM's systick device driver.
* It provides the standard kernel "system clock driver" interfaces.
*
* The driver utilizes systick to provide kernel ticks.
*
* \INTERNAL IMPLEMENTATION DETAILS
* The systick device provides a 24-bit clear-on-write, decrementing,
* wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
*
* \INTERNAL PACKAGING DETAILS
* The systick device driver is part of the microkernel in both a monolithic
* kernel system and a split kernel system; it is not included in the
* nanokernel portion of a split kernel.
*
* The device driver is also part of a nanokernel-only system, but omits more
* complex capabilities (such as tickless idle support) that are only used in
* conjunction with a microkernel.
*/
#include <nanokernel.h>
@ -477,20 +477,19 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
if ((ticks == -1) || (ticks > max_system_ticks)) {
/*
* We've been asked to fire the timer so far in the future that
* the
* required count value would not fit in the 24-bit reload
* the required count value would not fit in the 24-bit reload
* register.
* Instead, we program for the maximum programmable interval
* minus one
* system tick to prevent overflow when the left over count read
* earlier
* is added.
* minus one system tick to prevent overflow when the left over
* count read earlier is added.
*/
idle_original_count += max_load_value - default_load_value;
idle_original_ticks = max_system_ticks - 1;
} else {
/* leave one tick of buffer to have to time react when coming
* back */
/*
* leave one tick of buffer to have to time react when coming
* back
*/
idle_original_ticks = ticks - 1;
idle_original_count += idle_original_ticks * default_load_value;
}

118
drivers/timer/hpet.c
View file

@ -17,37 +17,41 @@
*/
/*
DESCRIPTION
This module implements a kernel device driver for the Intel High Precision
Event Timer (HPET) device, and provides the standard "system clock driver"
interfaces.
The driver utilizes HPET timer0 to provide kernel ticks.
\INTERNAL IMPLEMENTATION DETAILS
The HPET device driver makes no assumption about the initial state of the HPET,
and explicitly puts the device into a reset-like state. It also assumes that
the main up counter never wraps around to 0 during the lifetime of the system.
The platform can configure the HPET to use level rather than the default edge
sensitive interrupts by enabling the following configuration parameters:
CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW
When not configured to support tickless idle timer0 is programmed in periodic
mode so it automatically generates a single interrupt per kernel tick interval.
When configured to support tickless idle timer0 is programmed in one-shot mode.
When the CPU is not idling the timer interrupt handler sets the timer to expire
when the next kernel tick is due, waits for this to occur, and then repeats
this "ad infinitum". When the CPU begins idling the timer driver reprograms
the expiry time for the timer (thereby overriding the previously scheduled
timer interrupt) and waits for the timer to expire or for a non-timer interrupt
to occur. When the CPU ceases idling the driver determines how many complete
ticks have elapsed, reprograms the timer so that it expires on the next tick,
and announces the number of elapsed ticks (if any) to the microkernel.
In a nanokernel-only system this device driver omits more complex capabilities
(such as tickless idle support) that are only used with a microkernel.
* DESCRIPTION
* This module implements a kernel device driver for the Intel High Precision
* Event Timer (HPET) device, and provides the standard "system clock driver"
* interfaces.
*
* The driver utilizes HPET timer0 to provide kernel ticks.
*
* \INTERNAL IMPLEMENTATION DETAILS
* The HPET device driver makes no assumption about the initial state of the
* HPET, and explicitly puts the device into a reset-like state. It also assumes
* that the main up counter never wraps around to 0 during the lifetime of the
* system.
*
* The platform can configure the HPET to use level rather than the default edge
* sensitive interrupts by enabling the following configuration parameters:
* CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW
*
* When not configured to support tickless idle timer0 is programmed in periodic
* mode so it automatically generates a single interrupt per kernel tick
* interval.
*
* When configured to support tickless idle timer0 is programmed in one-shot
* mode. When the CPU is not idling the timer interrupt handler sets the timer
* to expire when the next kernel tick is due, waits for this to occur, and then
* repeats this "ad infinitum". When the CPU begins idling the timer driver
* reprograms the expiry time for the timer (thereby overriding the previously
* scheduled timer interrupt) and waits for the timer to expire or for a
* non-timer interrupt to occur. When the CPU ceases idling the driver
* determines how many complete ticks have elapsed, reprograms the timer so that
* it expires on the next tick, and announces the number of elapsed ticks (if
* any) to the microkernel.
*
* In a nanokernel-only system this device driver omits more complex
* capabilities (such as tickless idle support) that are only used with a
* microkernel.
*/
#include <nanokernel.h>
@ -193,14 +197,14 @@ extern uint32_t _hw_irq_to_c_handler_latency;
extern int32_t _sys_idle_elapsed_ticks;
static uint32_t __noinit counter_load_value; /* main counter units
per system tick */
static uint64_t counter_last_value =
0; /* counter value for most recent tick */
static int32_t programmed_ticks =
1; /* # ticks timer is programmed for */
static int stale_irq_check =
0; /* is stale interrupt possible? */
/* main counter units per system tick */
static uint32_t __noinit counter_load_value;
/* counter value for most recent tick */
static uint64_t counter_last_value = 0;
/* # ticks timer is programmed for */
static int32_t programmed_ticks = 1;
/* is stale interrupt possible? */
static int stale_irq_check = 0;
/**
*
@ -389,23 +393,22 @@ void _timer_idle_exit(void)
/*
* update # of ticks since last tick event was announced,
* so that this value is available to ISRs that run before the
* timer
* interrupt handler runs (which is unlikely, but could happen)
* timer interrupt handler runs (which is unlikely, but could
* happen)
*/
_sys_idle_elapsed_ticks = programmed_ticks - 1;
/*
* Announce elapsed ticks to the microkernel. Note we are
* guaranteed
* that the timer ISR will execute first before the tick event
* is
* serviced.
* guaranteed that the timer ISR will execute first before the
* tick event is serviced.
*/
_sys_clock_tick_announce();
/* timer interrupt handler reprograms the timer for the next
* tick */
* tick
*/
return;
}
@ -422,9 +425,8 @@ void _timer_idle_exit(void)
* the microkernel, which gets informed of the correct number of elapsed
* ticks when the following tick finally occurs; however, any ISRs that
* access _sys_idle_elapsed_ticks to determine the current time may be
*misled
* during the (very brief) interval before the tick-in-progress finishes
* and the following tick begins
* misled during the (very brief) interval before the tick-in-progress
* finishes and the following tick begins
*/
elapsedTicks =
@ -458,10 +460,8 @@ void _timer_idle_exit(void)
/*
* Any elapsed ticks have been accounted for so simply set the
* programmed
* ticks to 1 since the timer has been programmed to fire on the next
* tick
* boundary.
* programmed ticks to 1 since the timer has been programmed to fire on
* the next tick boundary.
*/
programmed_ticks = 1;
@ -491,8 +491,7 @@ int _sys_clock_driver_init(struct device *device)
/*
* Initial state of HPET is unknown, so put it back in a reset-like
* state
* (i.e. set main counter to 0 and disable interrupts)
* state (i.e. set main counter to 0 and disable interrupts)
*/
*_HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
@ -588,9 +587,9 @@ int _sys_clock_driver_init(struct device *device)
*/
/*
* HPET timers IRQ field is 5 bits wide, and hence, can support only IRQ's
* up to 31. Some platforms, however, use IRQs greater than 31. In this
* case program leaves the IRQ fields blank.
* HPET timers IRQ field is 5 bits wide, and hence, can support only
* IRQ's up to 31. Some platforms, however, use IRQs greater than 31. In
* this case program leaves the IRQ fields blank.
*/
*_HPET_TIMER0_CONFIG_CAPS =
@ -609,8 +608,7 @@ int _sys_clock_driver_init(struct device *device)
/*
* Although the stub has already been "connected", the vector number
* still
* has to be programmed into the interrupt controller.
* still has to be programmed into the interrupt controller.
*/
IRQ_CONFIG(hpet, CONFIG_HPET_TIMER_IRQ, 0);

10
drivers/timer/loapic_timer.c
View file

@ -132,8 +132,8 @@ IRQ_CONNECT_STATIC(loapic, CONFIG_LOAPIC_TIMER_IRQ,
CONFIG_LOAPIC_TIMER_IRQ_PRIORITY,
_timer_int_handler, 0);
static uint32_t __noinit cycles_per_tick; /* computed counter 0
initial count value */
/* computed counter 0 initial count value */
static uint32_t __noinit cycles_per_tick;
static uint32_t accumulated_cycle_count;
#if defined(TIMER_SUPPORTS_TICKLESS)
@ -596,13 +596,13 @@ int _sys_clock_driver_init(struct device *device)
/*
* Although the stub has already been "connected", the vector number
* still
* has to be programmed into the interrupt controller.
* still has to be programmed into the interrupt controller.
*/
IRQ_CONFIG(loapic, CONFIG_LOAPIC_TIMER_IRQ, 0);
/* Everything has been configured. It is now safe to enable the
* interrupt */
* interrupt
*/
irq_enable(CONFIG_LOAPIC_TIMER_IRQ);
return 0;

17
drivers/timer/sys_clock_init.c
View file

@ -17,14 +17,15 @@
*/
/*
DESCRIPTION
Initializing the timer driver is done in this module to reduce code duplication.
Although both nanokernel and microkernel systems initialize the timer driver at
the same point, the two systems differ in when the system can begin to process
system clock ticks. A nanokernel system can process system clock ticks once
the driver has initialized. However, in a microkernel system all system clock
ticks are deferred (and stored on the kernel server command stack) until the
kernel server fiber starts and begins processing any queued ticks.
* DESCRIPTION
* Initializing the timer driver is done in this module to reduce code
* duplication. Although both nanokernel and microkernel systems initialize
* the timer driver at the same point, the two systems differ in when the system
* can begin to process system clock ticks. A nanokernel system can process
* system clock ticks once the driver has initialized. However, in a
* microkernel system all system clock ticks are deferred (and stored on the
* kernel server command stack) until the kernel server fiber starts and begins
* processing any queued ticks.
*/
#include <nanokernel.h>

8
include/arch/arc/arch.h
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This header contains the ARC specific nanokernel interface. It is
included by the nanokernel interface architecture-abstraction header
(nanokernel/cpu.h)
* DESCRIPTION
* This header contains the ARC specific nanokernel interface. It is
* included by the nanokernel interface architecture-abstraction header
* (nanokernel/cpu.h)
*/
#ifndef _ARC_ARCH__H_

6
include/arch/arc/v2/aux_regs.h
View file

@ -17,9 +17,9 @@
*/
/*
DESCRIPTION
Definitions for auxiliary registers.
* DESCRIPTION
*
* Definitions for auxiliary registers.
*/
#ifndef _ARC_V2_AUX_REGS__H_

4
include/arch/arc/v2/error.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARC-specific nanokernel error handling interface. Included by ARC/arch.h.
* DESCRIPTION
* ARC-specific nanokernel error handling interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_ERROR_H_

4
include/arch/arc/v2/exc.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARC-specific nanokernel exception handling interface. Included by ARC/arch.h.
* DESCRIPTION
* ARC-specific nanokernel exception handling interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_EXC_H_

4
include/arch/arc/v2/ffs.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARC-specific nanokernel ffs interface. Included by ARC/arch.h.
* DESCRIPTION
* ARC-specific nanokernel ffs interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_FFS_H_

4
include/arch/arc/v2/misc.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h.
* DESCRIPTION
* ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h.
*/
#ifndef _ARCH_ARC_V2_MISC_H_

8
include/arch/arm/arch.h
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This header contains the ARM specific nanokernel interface. It is
included by the nanokernel interface architecture-abstraction header
(nanokernel/cpu.h)
* DESCRIPTION
* This header contains the ARM specific nanokernel interface. It is
* included by the nanokernel interface architecture-abstraction header
* (nanokernel/cpu.h)
*/
#ifndef _ARM_ARCH__H_

4
include/arch/arm/cortex_m/error.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
* DESCRIPTION
* ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_ERROR_H_

4
include/arch/arm/cortex_m/exc.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARM-specific nanokernel exception handling interface. Included by ARM/arch.h.
* DESCRIPTION
* ARM-specific nanokernel exception handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_EXC_H_

10
include/arch/arm/cortex_m/gdb_stub.h
View file

@ -17,11 +17,11 @@
*/
/*
DESCRIPTION
Prep work done when entering exceptions consists of saving the callee-saved
registers before they get used by exception handlers, and recording the fact
that we are running in an exception.
* DESCRIPTION
*
* Prep work done when entering exceptions consists of saving the callee-saved
* registers before they get used by exception handlers, and recording the fact
* that we are running in an exception.
*/
#ifndef _GDB_STUB__H_

4
include/arch/arm/cortex_m/irq.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
* DESCRIPTION
* ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_IRQ_H_

8
include/arch/arm/cortex_m/memory_map-m3-m4.h
View file

@ -17,10 +17,10 @@
*/
/*
DESCRIPTION
This module contains definitions for the memory map parts specific to the
CORTEX-M3/M4 series of processors. It is included by nanokernel/ARM/memory_map.h
* DESCRIPTION
* This module contains definitions for the memory map parts specific to the
* CORTEX-M3/M4 series of processors. It is included by
* nanokernel/ARM/memory_map.h
*/
#ifndef _MEMORY_MAP_M3_M4__H_

7
include/arch/arm/cortex_m/memory_map.h
View file

@ -17,10 +17,9 @@
*/
/*
DESCRIPTION
This module contains definitions for the memory map of the CORTEX-M series of
processors.
* DESCRIPTION
* This module contains definitions for the memory map of the CORTEX-M series of
* processors.
*/
#ifndef _CORTEXM_MEMORY_MAP__H_

4
include/arch/arm/cortex_m/misc.h
View file

@ -17,8 +17,8 @@
*/
/*
DESCRIPTION
ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h.
* DESCRIPTION
* ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_MISC_H_

30
include/arch/arm/cortex_m/nvic.h
View file

@ -17,21 +17,21 @@
*/
/*
DESCRIPTION
Provide an interface to the Nested Vectored Interrupt Controller found on
ARM Cortex-M processors.
The API does not account for all possible usages of the NVIC, only the
functionalities needed by the kernel.
The same effect can be achieved by directly writing in the registers of the
NVIC, with the layout available from scs.h, using the __scs.nvic data
structure (or hardcoded values), but these APIs are less error-prone,
especially for registers with multiple instances to account for potentially
240 interrupt lines. If access to a missing functionality is needed, this is
the way to implement it.
Supports up to 240 IRQs and 256 priority levels.
* DESCRIPTION
* Provide an interface to the Nested Vectored Interrupt Controller found on
* ARM Cortex-M processors.
*
* The API does not account for all possible usages of the NVIC, only the
* functionalities needed by the kernel.
*
* The same effect can be achieved by directly writing in the registers of the
* NVIC, with the layout available from scs.h, using the __scs.nvic data
* structure (or hardcoded values), but these APIs are less error-prone,
* especially for registers with multiple instances to account for potentially
* 240 interrupt lines. If access to a missing functionality is needed, this is
* the way to implement it.
*
* Supports up to 240 IRQs and 256 priority levels.
*/
#ifndef _NVIC_H_

33
include/arch/arm/cortex_m/scb.h
View file

@ -17,22 +17,23 @@
*/
/*
DESCRIPTION
Provide an interface to the System Control Block found on ARM Cortex-M
processors.
The API does not account for all possible usages of the SCB, only the
functionalities needed by the kernel. It does not contain NVIC
functionalities either: these can be found in nvic.h. MPU functionalities
are not implemented.
The same effect can be achieved by directly writing in the registers of the
SCB, with the layout available from scs.h, using the __scs.scb data
structure (or hardcoded values), but the APIs found here are less error-prone,
especially for registers with multiple instances to account for 16 exceptions.
If access to a missing functionality is needed, directly writing to the
registers is the way to implement it.
* DESCRIPTION
* Provide an interface to the System Control Block found on ARM Cortex-M
* processors.
*
* The API does not account for all possible usages of the SCB, only the
* functionalities needed by the kernel. It does not contain NVIC
* functionalities either: these can be found in nvic.h. MPU functionalities
* are not implemented.
*
* The same effect can be achieved by directly writing in the registers of the
* SCB, with the layout available from scs.h, using the __scs.scb data
* structure (or hardcoded values), but the APIs found here are less
* error-prone, especially for registers with multiple instances to account
* for 16 exceptions.
*
* If access to a missing functionality is needed, directly writing to the
* registers is the way to implement it.
*/
#ifndef _SCB__H_

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