diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c index 1f24f0b912f..cc2586dcb4e 100644 --- a/arch/arc/core/fatal.c +++ b/arch/arc/core/fatal.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module implements the routines necessary for handling fatal faults on -ARCv2 CPUs. + * DESCRIPTION + * This module implements the routines necessary for handling fatal faults on + * ARCv2 CPUs. */ #include diff --git a/arch/arc/core/offsets/offsets.c b/arch/arc/core/offsets/offsets.c index d3a32408af7..9e6c354d559 100644 --- a/arch/arc/core/offsets/offsets.c +++ b/arch/arc/core/offsets/offsets.c @@ -17,21 +17,20 @@ */ /* -DESCRIPTION -This module is responsible for the generation of the absolute symbols whose -value represents the member offsets for various ARCv2 nanokernel -structures. - -All of the absolute symbols defined by this module will be present in the -final microkernel or nanokernel ELF image (due to the linker's reference to -the _OffsetAbsSyms symbol). - -INTERNAL -It is NOT necessary to define the offset for every member of a structure. -Typically, only those members that are accessed by assembly language routines -are defined; however, it doesn't hurt to define all fields for the sake of -completeness. - + * DESCRIPTION + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various ARCv2 nanokernel + * structures. + * + * All of the absolute symbols defined by this module will be present in the + * final microkernel or nanokernel ELF image (due to the linker's reference to + * the _OffsetAbsSyms symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. */ #include diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index 416f61b5e9b..bd2429bfa1a 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION - -Initialization of full C support: zero the .bss, copy the .data if XIP, -call _Cstart(). - -Stack is available in this module, but not the global data/bss until their -initialization is performed. + * DESCRIPTION + * + * Initialization of full C support: zero the .bss, copy the .data if XIP, + * call _Cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. */ #include diff --git a/arch/arc/core/sys_fatal_error_handler.c b/arch/arc/core/sys_fatal_error_handler.c index 045ba6099d9..c7f5daae078 100644 --- a/arch/arc/core/sys_fatal_error_handler.c +++ b/arch/arc/core/sys_fatal_error_handler.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs. + * DESCRIPTION + * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs. */ #include diff --git a/arch/arc/core/vector_table.c b/arch/arc/core/vector_table.c index 759dae0fc54..67a03c0c5ba 100644 --- a/arch/arc/core/vector_table.c +++ b/arch/arc/core/vector_table.c @@ -17,20 +17,20 @@ */ /* -DESCRIPTION -Vector table with exceptions filled in. The reset vector is the system entry -point, ie. the first instruction executed. - -The table is populated with all the system exception handlers. No exception -should not be triggered until the kernel is ready to handle them. - -We are using a C file instead of an assembly file (like the ARM vector table) -to work around an issue with the assembler where: - - .word - -statements would end up with the two half-words of the functions' addresses -swapped. + * DESCRIPTION + * Vector table with exceptions filled in. The reset vector is the system entry + * point, ie. the first instruction executed. + * + * The table is populated with all the system exception handlers. No exception + * should not be triggered until the kernel is ready to handle them. + * + * We are using a C file instead of an assembly file (like the ARM vector table) + * to work around an issue with the assembler where: + * + * .word + * + * statements would end up with the two half-words of the functions' addresses + * swapped. */ #include diff --git a/arch/arc/include/nano_private.h b/arch/arc/include/nano_private.h index 2dc836899c0..91a41cfa971 100644 --- a/arch/arc/include/nano_private.h +++ b/arch/arc/include/nano_private.h @@ -17,14 +17,14 @@ */ /* -DESCRIPTION -This file contains private nanokernel structures definitions and various other -definitions for the ARCv2 processor architecture. - -This file is also included by assembly language files which must #define -_ASMLANGUAGE before including this header file. Note that nanokernel assembly -source files obtains structure offset values via "absolute symbols" in the -offsets.o module. + * DESCRIPTION + * This file contains private nanokernel structures definitions and various + * other definitions for the ARCv2 processor architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that nanokernel + * assembly source files obtains structure offset values via "absolute + * symbols" in the offsets.o module. */ #ifndef _NANO_PRIVATE_H @@ -160,15 +160,16 @@ typedef struct firq_regs tFirqRegs; #ifndef _ASMLANGUAGE struct tcs { - struct tcs *link; /* node in singly-linked list - * _nanokernel.fibers */ - uint32_t flags; /* bitmask of flags above */ - uint32_t intlock_key; /* interrupt key when relinquishing control */ - int relinquish_cause; /* one of the _CAUSE_xxxx definitions above */ - unsigned int return_value; /* return value from _Swap */ - int prio; /* fiber priority, -1 for a task */ + struct tcs *link; /* node in singly-linked list + * _nanokernel.fibers + */ + uint32_t flags; /* bitmask of flags above */ + uint32_t intlock_key; /* interrupt key when relinquishing control */ + int relinquish_cause; /* one of the _CAUSE_xxxx definitions above */ + unsigned int return_value;/* return value from _Swap */ + int prio; /* fiber priority, -1 for a task */ #ifdef CONFIG_THREAD_CUSTOM_DATA - void *custom_data; /* available for custom use */ + void *custom_data; /* available for custom use */ #endif struct coop coopReg; struct preempt preempReg; diff --git a/arch/arc/include/vector_table.h b/arch/arc/include/vector_table.h index a64ba5e2cd3..3a721826bdd 100644 --- a/arch/arc/include/vector_table.h +++ b/arch/arc/include/vector_table.h @@ -17,15 +17,15 @@ */ /* -DESCRIPTION - -Definitions for the boot vector table. - -System exception handler names all have the same format: - - __ - -Refer to the ARCv2 manual for an explanation of the exceptions. + * DESCRIPTION + * + * Definitions for the boot vector table. + * + * System exception handler names all have the same format: + * + * __ + * + * Refer to the ARCv2 manual for an explanation of the exceptions. */ #ifndef _VECTOR_TABLE__H_ diff --git a/arch/arc/platforms/generic_arc/board.h b/arch/arc/platforms/generic_arc/board.h index a674b9dda96..942698cf6c8 100644 --- a/arch/arc/platforms/generic_arc/board.h +++ b/arch/arc/platforms/generic_arc/board.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for the -generic arc BSP. -*/ + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for the + * generic arc BSP. + */ #ifndef _BOARD__H_ #define _BOARD__H_ diff --git a/arch/arc/platforms/generic_arc/irq_vector_table.c b/arch/arc/platforms/generic_arc/irq_vector_table.c index 2872bd6071f..3f03b1f880e 100644 --- a/arch/arc/platforms/generic_arc/irq_vector_table.c +++ b/arch/arc/platforms/generic_arc/irq_vector_table.c @@ -17,16 +17,16 @@ */ /* -DESCRIPTION -This file contains the IRQ part of the vector table. It is meant to be used -for one of two cases: - -a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it - binds _IsrWrapper() to all the IRQ entries in the vector table. - -b) When the BSP is written so that device ISRs are installed directly in the - vector table, they are enumerated here. -*/ + * DESCRIPTION + * This file contains the IRQ part of the vector table. It is meant to be used + * for one of two cases: + * + * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it + * binds _IsrWrapper() to all the IRQ entries in the vector table. + * + * b) When the BSP is written so that device ISRs are installed directly in the + * vector table, they are enumerated here. + */ #include #include diff --git a/arch/arc/platforms/generic_arc/sw_isr_table.c b/arch/arc/platforms/generic_arc/sw_isr_table.c index ac1b6c960e4..1da8467a726 100644 --- a/arch/arc/platforms/generic_arc/sw_isr_table.c +++ b/arch/arc/platforms/generic_arc/sw_isr_table.c @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This contains the ISR table meant to be used for ISRs that take a parameter. -It is also used when ISRs are to be connected at runtime, and in this case -provides a table that is filled with _SpuriousIRQ bindings. -*/ + * DESCRIPTION + * This contains the ISR table meant to be used for ISRs that take a parameter. + * It is also used when ISRs are to be connected at runtime, and in this case + * provides a table that is filled with _SpuriousIRQ bindings. + */ #include #include diff --git a/arch/arc/platforms/generic_arc/system.c b/arch/arc/platforms/generic_arc/system.c index 9b4f0527ba3..dc73119b83c 100644 --- a/arch/arc/platforms/generic_arc/system.c +++ b/arch/arc/platforms/generic_arc/system.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the generic arc platform. -*/ + * DESCRIPTION + * This module provides routines to initialize and support board-level hardware + * for the generic arc platform. + */ #include #include diff --git a/arch/arm/core/cortex_m/nmi.c b/arch/arm/core/cortex_m/nmi.c index 554ffe53067..6e7cb1eb7d1 100644 --- a/arch/arm/core/cortex_m/nmi.c +++ b/arch/arm/core/cortex_m/nmi.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -Provides a boot time handler that simply hangs in a sleep loop, and a run time -handler that resets the CPU. Also provides a mechanism for hooking a custom -run time handler. + * DESCRIPTION + * Provides a boot time handler that simply hangs in a sleep loop, and a run + * time handler that resets the CPU. Also provides a mechanism for hooking a + * custom run time handler. */ #include diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index a9c1ab75284..8ab5d934a1e 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION - -Initialization of full C support: zero the .bss, copy the .data if XIP, -call _Cstart(). - -Stack is available in this module, but not the global data/bss until their -initialization is performed. + * DESCRIPTION + * + * Initialization of full C support: zero the .bss, copy the .data if XIP, + * call _Cstart(). + * + * Stack is available in this module, but not the global data/bss until their + * initialization is performed. */ #include diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index 4404a9aae6a..a0190d3e2ae 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -17,11 +17,11 @@ */ /* -DESCRIPTION - -Most of the SCB interface consists of simple bit-flipping methods, and is -implemented as inline functions in scb.h. This module thus contains only data -definitions and more complex routines, if needed. + * DESCRIPTION + * + * Most of the SCB interface consists of simple bit-flipping methods, and is + * implemented as inline functions in scb.h. This module thus contains only data + * definitions and more complex routines, if needed. */ #include diff --git a/arch/arm/core/cortex_m/scs.c b/arch/arm/core/cortex_m/scs.c index 6912fb1c789..77cd8458c83 100644 --- a/arch/arm/core/cortex_m/scs.c +++ b/arch/arm/core/cortex_m/scs.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -Most of the SCS interface consists of simple bit-flipping methods, and is -implemented as inline functions in scs.h. This module thus contains only data -definitions and more complex routines, if needed. + * DESCRIPTION + * Most of the SCS interface consists of simple bit-flipping methods, and is + * implemented as inline functions in scs.h. This module thus contains only data + * definitions and more complex routines, if needed. */ #include diff --git a/arch/arm/core/cortex_m/vector_table.h b/arch/arm/core/cortex_m/vector_table.h index 4c6aa5e7ddc..6cc313c3ce9 100644 --- a/arch/arm/core/cortex_m/vector_table.h +++ b/arch/arm/core/cortex_m/vector_table.h @@ -17,15 +17,15 @@ */ /* -DESCRIPTION - -Definitions for the boot vector table. - -System exception handler names all have the same format: - - __ - -No other symbol has the same format, so they are easy to spot. + * DESCRIPTION + * + * Definitions for the boot vector table. + * + * System exception handler names all have the same format: + * + * __ + * + * No other symbol has the same format, so they are easy to spot. */ #ifndef _VECTOR_TABLE__H_ diff --git a/arch/arm/core/fatal.c b/arch/arm/core/fatal.c index e835ab2da22..fbb226d397a 100644 --- a/arch/arm/core/fatal.c +++ b/arch/arm/core/fatal.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M. + * DESCRIPTION + * This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M. */ #include diff --git a/arch/arm/core/fault.c b/arch/arm/core/fault.c index 91174721e5d..6e1b636fa94 100644 --- a/arch/arm/core/fault.c +++ b/arch/arm/core/fault.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Common fault handler for ARM Cortex-M processors. + * DESCRIPTION + * Common fault handler for ARM Cortex-M processors. */ #include diff --git a/arch/arm/core/fiber_abort.c b/arch/arm/core/fiber_abort.c index 85ff39ea220..d86855a9ead 100644 --- a/arch/arm/core/fiber_abort.c +++ b/arch/arm/core/fiber_abort.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION -The ARM Cortex-M architecture provides its own fiber_abort() to deal with -different CPU modes (handler vs thread) when a fiber aborts. When its entry -point returns or when it aborts itself, the CPU is in thread mode and must -call _Swap() (which triggers a service call), but when in handler mode, the -CPU must exit handler mode to cause the context switch, and thus must queue -the PendSV exception. + * DESCRIPTION + * The ARM Cortex-M architecture provides its own fiber_abort() to deal with + * different CPU modes (handler vs thread) when a fiber aborts. When its entry + * point returns or when it aborts itself, the CPU is in thread mode and must + * call _Swap() (which triggers a service call), but when in handler mode, the + * CPU must exit handler mode to cause the context switch, and thus must queue + * the PendSV exception. */ #ifdef CONFIG_MICROKERNEL diff --git a/arch/arm/core/gdb_stub_irq_vector_table.c b/arch/arm/core/gdb_stub_irq_vector_table.c index e9c849fe1dd..81b14900b3c 100644 --- a/arch/arm/core/gdb_stub_irq_vector_table.c +++ b/arch/arm/core/gdb_stub_irq_vector_table.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -When GDB is enabled, the static IRQ vector table needs to install the -_irq_vector_table_entry_with_gdb_stub stub to do some work before calling the -user-installed ISRs. + * DESCRIPTION + * When GDB is enabled, the static IRQ vector table needs to install the + * _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the + * user-installed ISRs. */ #include diff --git a/arch/arm/core/irq_init.c b/arch/arm/core/irq_init.c index 11d63799bdf..5f70c03beb1 100644 --- a/arch/arm/core/irq_init.c +++ b/arch/arm/core/irq_init.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION -The ARM Cortex-M architecture provides its own fiber_abort() to deal with -different CPU modes (handler vs thread) when a fiber aborts. When its entry -point returns or when it aborts itself, the CPU is in thread mode and must -call _Swap() (which triggers a service call), but when in handler mode, the -CPU must exit handler mode to cause the context switch, and thus must queue -the PendSV exception. + * DESCRIPTION + * The ARM Cortex-M architecture provides its own fiber_abort() to deal with + * different CPU modes (handler vs thread) when a fiber aborts. When its entry + * point returns or when it aborts itself, the CPU is in thread mode and must + * call _Swap() (which triggers a service call), but when in handler mode, the + * CPU must exit handler mode to cause the context switch, and thus must queue + * the PendSV exception. */ #include diff --git a/arch/arm/core/irq_manage.c b/arch/arm/core/irq_manage.c index c314a51df3d..ed4d648b9bf 100644 --- a/arch/arm/core/irq_manage.c +++ b/arch/arm/core/irq_manage.c @@ -17,10 +17,11 @@ */ /* -DESCRIPTION - -Interrupt management: enabling/disabling and dynamic ISR connecting/replacing. -SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime. + * DESCRIPTION + * + * Interrupt management: enabling/disabling and dynamic ISR + * connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for + * connecting ISRs at runtime. */ #include diff --git a/arch/arm/core/offsets/offsets.c b/arch/arm/core/offsets/offsets.c index 9e626d777d4..292c8ae0cae 100644 --- a/arch/arm/core/offsets/offsets.c +++ b/arch/arm/core/offsets/offsets.c @@ -17,21 +17,20 @@ */ /* -DESCRIPTION -This module is responsible for the generation of the absolute symbols whose -value represents the member offsets for various ARM nanokernel -structures. - -All of the absolute symbols defined by this module will be present in the -final microkernel or nanokernel ELF image (due to the linker's reference to -the _OffsetAbsSyms symbol). - -INTERNAL -It is NOT necessary to define the offset for every member of a structure. -Typically, only those members that are accessed by assembly language routines -are defined; however, it doesn't hurt to define all fields for the sake of -completeness. - + * DESCRIPTION + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various ARM nanokernel + * structures. + * + * All of the absolute symbols defined by this module will be present in the + * final microkernel or nanokernel ELF image (due to the linker's reference to + * the _OffsetAbsSyms symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. */ #include diff --git a/arch/arm/core/sys_fatal_error_handler.c b/arch/arm/core/sys_fatal_error_handler.c index ac6b68cd5c6..fb2d1080283 100644 --- a/arch/arm/core/sys_fatal_error_handler.c +++ b/arch/arm/core/sys_fatal_error_handler.c @@ -17,8 +17,9 @@ */ /* -DESCRIPTION -This module provides the _SysFatalErrorHandler() routine for Cortex-M platforms. + * DESCRIPTION + * This module provides the _SysFatalErrorHandler() routine for Cortex-M + * platforms. */ #include diff --git a/arch/arm/core/task_abort.c b/arch/arm/core/task_abort.c index 024ff81d0f7..1f9256da93b 100644 --- a/arch/arm/core/task_abort.c +++ b/arch/arm/core/task_abort.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION -The ARM Cortex-M architecture provides its own _TaskAbort() to deal with -different CPU modes (handler vs thread) when a task aborts. When its entry -point returns or when it aborts itself, the CPU is in thread mode and must -call the equivalent of task_abort(), but when in handler mode, the -CPU must queue a packet to _k_server(), then exit handler mode to queue the -PendSV exception and cause the immediate context switch to _k_server. + * DESCRIPTION + * The ARM Cortex-M architecture provides its own _TaskAbort() to deal with + * different CPU modes (handler vs thread) when a task aborts. When its entry + * point returns or when it aborts itself, the CPU is in thread mode and must + * call the equivalent of task_abort(), but when in handler mode, the + * CPU must queue a packet to _k_server(), then exit handler mode to queue the + * PendSV exception and cause the immediate context switch to _k_server. */ #ifdef CONFIG_MICROKERNEL diff --git a/arch/arm/core/thread.c b/arch/arm/core/thread.c index 0bb126e7093..251ab316947 100644 --- a/arch/arm/core/thread.c +++ b/arch/arm/core/thread.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -Core nanokernel fiber related primitives for the ARM Cortex-M processor -architecture. + * DESCRIPTION + * Core nanokernel fiber related primitives for the ARM Cortex-M processor + * architecture. */ #include @@ -57,8 +57,9 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */ unsigned int key; /* - * Add the newly initialized thread to head of the list of threads. This - * singly linked list of threads maintains ALL the threads in the system: + * Add the newly initialized thread to head of the list of threads. + * This singly linked list of threads maintains ALL the threads in the + * system: * both tasks and fibers regardless of whether they are runnable. */ diff --git a/arch/arm/include/cortex_m/exc.h b/arch/arm/include/cortex_m/exc.h index cb9ac167f9c..5ed6914e106 100644 --- a/arch/arm/include/cortex_m/exc.h +++ b/arch/arm/include/cortex_m/exc.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Exception/interrupt context helpers. + * DESCRIPTION + * Exception/interrupt context helpers. */ #ifndef _ARM_CORTEXM_ISR__H_ diff --git a/arch/arm/include/cortex_m/stack.h b/arch/arm/include/cortex_m/stack.h index 2890c954660..fe4d5ee94b8 100644 --- a/arch/arm/include/cortex_m/stack.h +++ b/arch/arm/include/cortex_m/stack.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Stack helper functions. + * DESCRIPTION + * Stack helper functions. */ #ifndef _ARM_CORTEXM_STACK__H_ diff --git a/arch/arm/include/nano_private.h b/arch/arm/include/nano_private.h index bb389a63fa8..066a0b41e0d 100644 --- a/arch/arm/include/nano_private.h +++ b/arch/arm/include/nano_private.h @@ -17,14 +17,14 @@ */ /* -DESCRIPTION -This file contains private nanokernel structures definitions and various other -definitions for the ARM Cortex-M3 processor architecture. - -This file is also included by assembly language files which must #define -_ASMLANGUAGE before including this header file. Note that nanokernel assembly -source files obtains structure offset values via "absolute symbols" in the -offsets.o module. + * DESCRIPTION + * This file contains private nanokernel structures definitions and various + * other definitions for the ARM Cortex-M3 processor architecture. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that nanokernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. */ #ifndef _NANO_PRIVATE_H diff --git a/arch/arm/include/start_task_arch.h b/arch/arm/include/start_task_arch.h index 02a7522db66..8d80ec084c3 100644 --- a/arch/arm/include/start_task_arch.h +++ b/arch/arm/include/start_task_arch.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -ARM-specific parts of start_task(). - -Currently empty, only here for abstraction. + * DESCRIPTION + * ARM-specific parts of start_task(). + * + * Currently empty, only here for abstraction. */ #ifndef _START_TASK_ARCH__H_ diff --git a/arch/arm/platforms/fsl_frdm_k64f/board.h b/arch/arm/platforms/fsl_frdm_k64f/board.h index bd1aadb41bb..6244f3a7bb4 100644 --- a/arch/arm/platforms/fsl_frdm_k64f/board.h +++ b/arch/arm/platforms/fsl_frdm_k64f/board.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for the -'fsl_frdm_k64f' platform. + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for the + * 'fsl_frdm_k64f' platform. */ #ifndef _BOARD__H_ diff --git a/arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c b/arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c index a4d9f84932d..3284191a3ca 100644 --- a/arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c +++ b/arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c @@ -17,15 +17,15 @@ */ /* -DESCRIPTION -This file contains the IRQ part of the vector table. It is meant to be used -for one of two cases: - -a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it - binds _isr_wrapper() to all the IRQ entries in the vector table. - -b) When the platform is written so that device ISRs are installed directly in - the vector table, they are enumerated here. + * DESCRIPTION + * This file contains the IRQ part of the vector table. It is meant to be used + * for one of two cases: + * + * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it + * binds _isr_wrapper() to all the IRQ entries in the vector table. + * + * b) When the platform is written so that device ISRs are installed directly in + * the vector table, they are enumerated here. */ #include diff --git a/arch/arm/platforms/fsl_frdm_k64f/system.c b/arch/arm/platforms/fsl_frdm_k64f/system.c index 8565340441f..cfaf777e431 100644 --- a/arch/arm/platforms/fsl_frdm_k64f/system.c +++ b/arch/arm/platforms/fsl_frdm_k64f/system.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the fsl_frdm_k64f platform. + * DESCRIPTION + * This module provides routines to initialize and support board-level + * hardware for the fsl_frdm_k64f platform. */ #include @@ -67,7 +67,7 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = { /* Backdoor Comparison Key (unused) */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, /* Program flash protection; 1 bit/region - 0=protected, 1=unprotected - */ + */ 0xFF, 0xFF, 0xFF, 0xFF, /* * Flash security: Backdoor key disabled, Mass erase enabled, @@ -89,7 +89,8 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = { * that the current MCG mode is FLL Engaged Internal (FEI), as from reset. * It transitions through the FLL Bypassed External (FBE) and * PLL Bypassed External (PBE) modes to get to the desired - * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system clock. + * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system + * clock. * * @return N/A * @@ -152,15 +153,19 @@ static void clkInit(void) mcg_p->c1 = temp_reg; - /* Confirm that the external reference clock is the FLL reference source + /* + * Confirm that the external reference clock is the FLL reference + * source */ while ((mcg_p->s & MCG_S_IREFST_MASK) != 0) ; ; - /* Confirm the external ref. clock is the system clock source - * (MCGOUTCLK) */ + /* + * Confirm the external ref. clock is the system clock source + * (MCGOUTCLK) + */ while ((mcg_p->s & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT_REF) ; @@ -298,10 +303,14 @@ static int fsl_frdm_k64f_init(struct device *arg) (SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) | (SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT)); - clkInit(); /* Initialize PLL/system clock to 120 MHz */ + /* Initialize PLL/system clock to 120 MHz */ + clkInit(); - NMI_INIT(); /* install default handler that simply resets the CPU - * if configured in the kernel, NOP otherwise */ + /* + * install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); /* restore interrupt state */ irq_unlock(oldLevel); diff --git a/arch/arm/platforms/ti_lm3s6965/board.h b/arch/arm/platforms/ti_lm3s6965/board.h index cf3bc1a6490..d58fafaca62 100644 --- a/arch/arm/platforms/ti_lm3s6965/board.h +++ b/arch/arm/platforms/ti_lm3s6965/board.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for -the 'ti_lm3s6965' platform. + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for + * the 'ti_lm3s6965' platform. */ #ifndef _BOARD__H_ diff --git a/arch/arm/platforms/ti_lm3s6965/irq_vector_table.c b/arch/arm/platforms/ti_lm3s6965/irq_vector_table.c index a4d9f84932d..3284191a3ca 100644 --- a/arch/arm/platforms/ti_lm3s6965/irq_vector_table.c +++ b/arch/arm/platforms/ti_lm3s6965/irq_vector_table.c @@ -17,15 +17,15 @@ */ /* -DESCRIPTION -This file contains the IRQ part of the vector table. It is meant to be used -for one of two cases: - -a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it - binds _isr_wrapper() to all the IRQ entries in the vector table. - -b) When the platform is written so that device ISRs are installed directly in - the vector table, they are enumerated here. + * DESCRIPTION + * This file contains the IRQ part of the vector table. It is meant to be used + * for one of two cases: + * + * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it + * binds _isr_wrapper() to all the IRQ entries in the vector table. + * + * b) When the platform is written so that device ISRs are installed directly in + * the vector table, they are enumerated here. */ #include diff --git a/arch/arm/platforms/ti_lm3s6965/scp.c b/arch/arm/platforms/ti_lm3s6965/scp.c index 4d7c72cb062..6c001e91d8e 100644 --- a/arch/arm/platforms/ti_lm3s6965/scp.c +++ b/arch/arm/platforms/ti_lm3s6965/scp.c @@ -17,12 +17,12 @@ */ /* -DESCRIPTION - -Library for controlling target-specific devices present in the 0x400fe000 -peripherals memory region. - -Currently, only enabling the main OSC with default value is implemented. + * DESCRIPTION + * + * Library for controlling target-specific devices present in the 0x400fe000 + * peripherals memory region. + * + * Currently, only enabling the main OSC with default value is implemented. */ #include diff --git a/arch/arm/platforms/ti_lm3s6965/scp.h b/arch/arm/platforms/ti_lm3s6965/scp.h index 87daae8f1f4..5e677d16278 100644 --- a/arch/arm/platforms/ti_lm3s6965/scp.h +++ b/arch/arm/platforms/ti_lm3s6965/scp.h @@ -17,21 +17,21 @@ */ /* -DESCRIPTION -This module defines the System Control Peripheral Registers for TI LM3S6965 -processor. The registers defined are in region 0x400fe000. - - System Control 0x400fe000 - -These modules are not defined: - - Hibernation Module 0x400fc000 - Internal Memory 0x400fd000 - Hibernation Module 0x400fc000 - -The registers and bit field names are taken from the 'Stellaris LM3S6965 -Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document, -section 5.4/5.5, pp .184-200. + * DESCRIPTION + * This module defines the System Control Peripheral Registers for TI LM3S6965 + * processor. The registers defined are in region 0x400fe000. + * + * System Control 0x400fe000 + * + * These modules are not defined: + * + * Hibernation Module 0x400fc000 + * Internal Memory 0x400fd000 + * Hibernation Module 0x400fc000 + * + * The registers and bit field names are taken from the 'Stellaris LM3S6965 + * Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document, + * section 5.4/5.5, pp .184-200. */ #ifndef _SCP_H_ diff --git a/arch/arm/platforms/ti_lm3s6965/system.c b/arch/arm/platforms/ti_lm3s6965/system.c index fc84a7fa002..a86d6d03437 100644 --- a/arch/arm/platforms/ti_lm3s6965/system.c +++ b/arch/arm/platforms/ti_lm3s6965/system.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the ti_lm3s6965 platform. + * DESCRIPTION + * This module provides routines to initialize and support board-level hardware + * for the ti_lm3s6965 platform. */ #include diff --git a/arch/x86/core/atomic_nolock.c b/arch/x86/core/atomic_nolock.c index ae63763c04e..fdbd6e5ecc5 100644 --- a/arch/x86/core/atomic_nolock.c +++ b/arch/x86/core/atomic_nolock.c @@ -17,18 +17,18 @@ */ /* -DESCRIPTION -This module provides the atomic operators for IA-32 architectures on platforms -that do not support the LOCK prefix instruction. - -The atomic operations are guaranteed to be atomic with respect to interrupt -service routines. However, they are NOT guaranteed to be atomic with respect -to operations performed by peer processors, unlike the versions of these -operators that do utilize the LOCK prefix instruction. - -INTERNAL -These operators are currently unavailable to user space applications -as there is no requirement for this capability. + * DESCRIPTION + * This module provides the atomic operators for IA-32 architectures on + * platforms that do not support the LOCK prefix instruction. + * + * The atomic operations are guaranteed to be atomic with respect to interrupt + * service routines. However, they are NOT guaranteed to be atomic with respect + *to operations performed by peer processors, unlike the versions of these + * operators that do utilize the LOCK prefix instruction. + * + * INTERNAL + * These operators are currently unavailable to user space applications + * as there is no requirement for this capability. */ #if defined(CONFIG_LOCK_INSTRUCTION_UNSUPPORTED) diff --git a/arch/x86/core/cache.c b/arch/x86/core/cache.c index 1779ac86588..c5b680b78b3 100644 --- a/arch/x86/core/cache.c +++ b/arch/x86/core/cache.c @@ -16,8 +16,8 @@ * limitations under the License. */ /* -DESCRIPTION -This module contains functions for manipulation caches. + * DESCRIPTION + * This module contains functions for manipulation caches. */ #include diff --git a/arch/x86/core/excconnect.c b/arch/x86/core/excconnect.c index 4f1cb739604..12fb69dcd50 100644 --- a/arch/x86/core/excconnect.c +++ b/arch/x86/core/excconnect.c @@ -17,49 +17,49 @@ */ /* -DESCRIPTION -This module provides routines to manage exceptions (synchronous interrupts) -on the IA-32 architecture. - -This module provides the public routine nanoCpuExcConnect(). - -INTERNAL -An exception is defined as a synchronous interrupt, i.e. an interrupt -asserted as a direct result of program execution as opposed to a -hardware device asserting an interrupt. - -Many (but not all) exceptions are handled by an "exception stub" whose code -is generated by the system itself. The stub performs various actions before -and after invoking the application (or operating system) specific exception -handler; for example, a thread or ISR context save is performed prior to -invoking the exception handler. - -The IA-32 code that makes up a "full" exception stub is shown below. A full -exception stub is one that pushes a dummy error code at the start of -exception processing. Exception types where the processor automatically -pushes an error code when handling an exception utilize similar exception -stubs, however the first instruction is omitted. The use of the dummy error -code means that _ExcEnt() and _ExcExit() do not have to worry about whether -an error code is present on the stack or not. - - - 0x00 pushl $0 /@ push dummy error code @/ - Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 - - 0x05 call _ExcEnt /@ inform kernel of exception @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - 0x0a call ExcHandler /@ invoke exception handler @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - /@ _ExcExit() will adjust the stack to discard the error code @/ - - 0x0f jmp _ExcExit /@ restore thread context @/ - Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00 - -NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE -macro to reflect the size of the full exception stub (as shown above). -The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h. + * DESCRIPTION + * This module provides routines to manage exceptions (synchronous interrupts) + * on the IA-32 architecture. + * + * This module provides the public routine nanoCpuExcConnect(). + * + * INTERNAL + * An exception is defined as a synchronous interrupt, i.e. an interrupt + * asserted as a direct result of program execution as opposed to a + * hardware device asserting an interrupt. + * + * Many (but not all) exceptions are handled by an "exception stub" whose code + * is generated by the system itself. The stub performs various actions before + * and after invoking the application (or operating system) specific exception + * handler; for example, a thread or ISR context save is performed prior to + * invoking the exception handler. + * + * The IA-32 code that makes up a "full" exception stub is shown below. A full + * exception stub is one that pushes a dummy error code at the start of + * exception processing. Exception types where the processor automatically + * pushes an error code when handling an exception utilize similar exception + * stubs, however the first instruction is omitted. The use of the dummy error + * code means that _ExcEnt() and _ExcExit() do not have to worry about whether + * an error code is present on the stack or not. + * + * + * 0x00 pushl $0 /@ push dummy error code @/ + * Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 + * + * 0x05 call _ExcEnt /@ inform kernel of exception @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * 0x0a call ExcHandler /@ invoke exception handler @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * /@ _ExcExit() will adjust the stack to discard the error code @/ + * + * 0x0f jmp _ExcExit /@ restore thread context @/ + * Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00 + * + * NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE + * macro to reflect the size of the full exception stub (as shown above). + * The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h. */ @@ -105,7 +105,8 @@ void _NanoCpuExcConnectAtDpl(unsigned int vector, */ void nanoCpuExcConnect(unsigned int vector, /* interrupt vector: 0 to 255 on - IA-32 */ + * IA-32 + */ void (*routine)(NANO_ESF * pEsf), NANO_EXC_STUB pExcStubMem) { diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c index 3d5af425fc4..1c8a408b246 100644 --- a/arch/x86/core/fatal.c +++ b/arch/x86/core/fatal.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module provides the _NanoFatalErrorHandler() routine. + * DESCRIPTION + * This module provides the _NanoFatalErrorHandler() routine. */ #include diff --git a/arch/x86/core/float.c b/arch/x86/core/float.c index c6cc4fece57..20c5fbb61fe 100644 --- a/arch/x86/core/float.c +++ b/arch/x86/core/float.c @@ -17,61 +17,63 @@ */ /* -DESCRIPTION -This module allows multiple tasks and fibers to safely share the system's -floating point resources, by allowing the system to save FPU state information -in a task or fiber's stack region when a pre-emptive context switch occurs. - -The floating point resource sharing mechanism is designed for minimal -intrusiveness. Floating point thread saving is only performed for tasks and -fibers that explicitly enable FP resource sharing, to avoid impacting the stack -size requirements of all other tasks and fibers. For those tasks and fibers -that do require FP resource sharing, a "lazy save/restore" mechanism is employed -so that the FPU's register sets are only switched in and out when absolutely -necessary; this avoids wasting effort preserving them when there is no risk -that they will be altered, or when there is no need to preserve their contents. - -The following APIs are provided to allow floating point resource sharing to be -enabled or disabled at run-time: - - void fiber_float_enable (nano_thread_id_t thread_id, unsigned int options) - void task_float_enable (nano_thread_id_t thread_id, unsigned int options) - void fiber_float_disable (nano_thread_id_t thread_id) - void task_float_disable (nano_thread_id_t thread_id) - -The 'options' parameter is used to specify what non-integer capabilities are -being used. The same options accepted by fiber_fiber_start() are used in the -aforementioned APIs, namely USE_FP and USE_SSE. - -If the nanokernel has been built without SSE instruction support -(CONFIG_SSE), the system treats USE_SSE as if it was USE_FP. - -If the nanokernel has been built without floating point resource -sharing support (CONFIG_FP_SHARING), the aforementioned APIs and -capabilities do not exist. - -NOTE -It is possible for a single task or fiber to utilize floating instructions -_without_ enabling the FP resource sharing feature. Since no other task or -fiber uses the FPU the FP registers won't change when the FP-capable task or -fiber isn't executing, meaning there is no need to save the registers. - -WARNING -The use of floating point instructions by ISRs is not supported by the kernel. - -INTERNAL -If automatic enabling of floating point resource sharing _is not_ configured -the system leaves CR0[TS] = 0 for all tasks and fibers. This means that any -task or fiber can perform floating point operations at any time without causing -an exception, and the system won't stop a task or fiber that shouldn't be -doing FP stuff from doing it. - -If automatic enabling of floating point resource sharing _is_ configured the -system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to perform -FP operations. All other tasks and fibers have CR0[TS] = 1 so that an attempt -to perform an FP operation will cause an exception, allowing the system to -enable FP resource sharing on its behalf. - + * DESCRIPTION + * This module allows multiple tasks and fibers to safely share the system's + * floating point resources, by allowing the system to save FPU state + * information in a task or fiber's stack region when a pre-emptive context + * switch occurs. + * + * The floating point resource sharing mechanism is designed for minimal + * intrusiveness. Floating point thread saving is only performed for tasks and + * fibers that explicitly enable FP resource sharing, to avoid impacting the + * stack size requirements of all other tasks and fibers. For those tasks and + * fibers that do require FP resource sharing, a "lazy save/restore" mechanism + * is employed so that the FPU's register sets are only switched in and out + * when absolutely necessary; this avoids wasting effort preserving them when + * there is no risk that they will be altered, or when there is no need to + * preserve their contents. + * + * The following APIs are provided to allow floating point resource sharing to + * be enabled or disabled at run-time: + * + * void fiber_float_enable (nano_thread_id_t thread_id, unsigned int options) + * void task_float_enable (nano_thread_id_t thread_id, unsigned int options) + * void fiber_float_disable (nano_thread_id_t thread_id) + * void task_float_disable (nano_thread_id_t thread_id) + * + * The 'options' parameter is used to specify what non-integer capabilities are + * being used. The same options accepted by fiber_fiber_start() are used in the + * aforementioned APIs, namely USE_FP and USE_SSE. + * + * If the nanokernel has been built without SSE instruction support + * (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP. + * + * If the nanokernel has been built without floating point resource sharing + * support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not + * exist. + * + * NOTE + * It is possible for a single task or fiber to utilize floating instructions + * _without_ enabling the FP resource sharing feature. Since no other task or + * fiber uses the FPU the FP registers won't change when the FP-capable task or + * fiber isn't executing, meaning there is no need to save the registers. + * + * WARNING + * The use of floating point instructions by ISRs is not supported by the + * kernel. + * + * INTERNAL + * If automatic enabling of floating point resource sharing _is not_ configured + * the system leaves CR0[TS] = 0 for all tasks and fibers. This means that any + * task or fiber can perform floating point operations at any time without + * causing an exception, and the system won't stop a task or fiber that + * shouldn't be doing FP stuff from doing it. + * + * If automatic enabling of floating point resource sharing _is_ configured + * the system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to + * perform FP operations. All other tasks and fibers have CR0[TS] = 1 so that + * an attempt to perform an FP operation will cause an exception, allowing the + * system to enable FP resource sharing on its behalf. */ #ifdef CONFIG_MICROKERNEL diff --git a/arch/x86/core/gdt.c b/arch/x86/core/gdt.c index 7009c011f6f..bd15d77df04 100644 --- a/arch/x86/core/gdt.c +++ b/arch/x86/core/gdt.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module contains routines for updating the global descriptor table (GDT) -for the IA-32 architecture. + * DESCRIPTION + * This module contains routines for updating the global descriptor table (GDT) + * for the IA-32 architecture. */ #include diff --git a/arch/x86/core/intconnect.c b/arch/x86/core/intconnect.c index 94ad186ef3d..13a6f902945 100644 --- a/arch/x86/core/intconnect.c +++ b/arch/x86/core/intconnect.c @@ -17,60 +17,61 @@ */ /* -DESCRIPTION -This module provides routines to manage asynchronous interrupts -on the IA-32 architecture. - -This module provides the public routine irq_connect(), the private -routine _IntVecSet(), and the support routines _IntVecAlloc(), -_IntVecMarkAllocated() and _IntVecMarkFree(). - -INTERNAL -The _idt_base_address symbol is used to determine the base address of the IDT. -(It is generated by the linker script, and doesn't correspond to an actual -global variable.) - -Interrupts are handled by an "interrupt stub" whose code is generated by the -system itself. The stub performs various actions before and after invoking -the application (or operating system) specific interrupt handler; for example, -a thread context save is performed prior to invoking the interrupt handler. - -The IA-32 code that makes up a "full" interrupt stub is shown below. A full -interrupt stub is one that is associated with an interrupt vector that requires -a "beginning of interrupt" (BOI) callout and an "end of interrupt" (EOI) callout -(both of which require a parameter). - - 0x00 call _IntEnt /@ inform kernel of interrupt @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - 0x05 pushl $BoiParameter /@ optional: push BOI handler parameter @/ - Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 - - 0x0a call BoiRoutine /@ optional: callout to BOI rtn @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - 0x0f pushl $IsrParameter /@ push ISR parameter @/ - Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 - - 0x14 call IsrRoutine /@ invoke ISR @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - 0x19 pushl $EoiParameter /@ optional: push EOI handler parameter @/ - Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 - - 0x1e call EoiRoutine /@ optional: callout to EOI rtn @/ - Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 - - 0x23 addl $(4 * numParams), %esp /@ pop parameters @/ - Machine code: 0x83, 0xc4, (4 * numParams) - - 0x26 jmp _IntExit /@ restore thread or reschedule @/ - Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00 - -NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE macro -to reflect the maximum potential size of the interrupt stub (as shown above). -The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h. - + * DESCRIPTION + * This module provides routines to manage asynchronous interrupts + * on the IA-32 architecture. + * + * This module provides the public routine irq_connect(), the private + * routine _IntVecSet(), and the support routines _IntVecAlloc(), + * _IntVecMarkAllocated() and _IntVecMarkFree(). + * + * INTERNAL + * The _idt_base_address symbol is used to determine the base address of the + * IDT. (It is generated by the linker script, and doesn't correspond to an + * actual global variable.) + * + * Interrupts are handled by an "interrupt stub" whose code is generated by the + * system itself. The stub performs various actions before and after invoking + * the application (or operating system) specific interrupt handler; for + * example, a thread context save is performed prior to invoking the interrupt + * handler. + * + * The IA-32 code that makes up a "full" interrupt stub is shown below. A full + * interrupt stub is one that is associated with an interrupt vector that + * requires a "beginning of interrupt" (BOI) callout and an "end of interrupt" + * (EOI) callout (both of which require a parameter). + * + * 0x00 call _IntEnt /@ inform kernel of interrupt @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * 0x05 pushl $BoiParameter /@ optional: push BOI handler parameter @/ + * Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 + * + * 0x0a call BoiRoutine /@ optional: callout to BOI rtn @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * 0x0f pushl $IsrParameter /@ push ISR parameter @/ + * Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 + * + * 0x14 call IsrRoutine /@ invoke ISR @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * 0x19 pushl $EoiParameter /@ optional: push EOI handler parameter @/ + * Machine code: 0x68, 0x00, 0x00, 0x00, 0x00 + * + * 0x1e call EoiRoutine /@ optional: callout to EOI rtn @/ + * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00 + * + * 0x23 addl $(4 * numParams), %esp /@ pop parameters @/ + * Machine code: 0x83, 0xc4, (4 * numParams) + * + * 0x26 jmp _IntExit /@ restore thread or reschedule @/ + * Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00 + * + * NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE + * macro to reflect the maximum potential size of the interrupt stub (as shown + * above). + * The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h. */ #ifndef CONFIG_NO_ISRS diff --git a/arch/x86/core/offsets/offsets.c b/arch/x86/core/offsets/offsets.c index 9abe822db58..6deb23f5931 100644 --- a/arch/x86/core/offsets/offsets.c +++ b/arch/x86/core/offsets/offsets.c @@ -17,20 +17,19 @@ */ /* -DESCRIPTION -This module is responsible for the generation of the absolute symbols whose -value represents the member offsets for various IA-32 nanokernel structures. - -All of the absolute symbols defined by this module will be present in the -final microkernel or nanokernel ELF image (due to the linker's reference to -the _OffsetAbsSyms symbol). - -INTERNAL -It is NOT necessary to define the offset for every member of a structure. -Typically, only those members that are accessed by assembly language routines -are defined; however, it doesn't hurt to define all fields for the sake of -completeness. - + * DESCRIPTION + * This module is responsible for the generation of the absolute symbols whose + * value represents the member offsets for various IA-32 nanokernel structures. + * + * All of the absolute symbols defined by this module will be present in the + * final microkernel or nanokernel ELF image (due to the linker's reference to + * the _OffsetAbsSyms symbol). + * + * INTERNAL + * It is NOT necessary to define the offset for every member of a structure. + * Typically, only those members that are accessed by assembly language routines + * are defined; however, it doesn't hurt to define all fields for the sake of + * completeness. */ #include /* located in kernel/arch/common/include */ diff --git a/arch/x86/core/strtask.c b/arch/x86/core/strtask.c index a7812f81335..396a76db3a3 100644 --- a/arch/x86/core/strtask.c +++ b/arch/x86/core/strtask.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Intel-specific parts of start_task(). Only FP functionality currently. + * DESCRIPTION + * Intel-specific parts of start_task(). Only FP functionality currently. */ #ifdef CONFIG_MICROKERNEL diff --git a/arch/x86/core/sys_fatal_error_handler.c b/arch/x86/core/sys_fatal_error_handler.c index fbd4615b977..c97ca0868fb 100644 --- a/arch/x86/core/sys_fatal_error_handler.c +++ b/arch/x86/core/sys_fatal_error_handler.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides the _SysFatalErrorHandler() routine which is common to -supported platforms. + * DESCRIPTION + * This module provides the _SysFatalErrorHandler() routine which is common to + * supported platforms. */ #include diff --git a/arch/x86/core/thread.c b/arch/x86/core/thread.c index 3d4104da2e5..14c2a8a098d 100644 --- a/arch/x86/core/thread.c +++ b/arch/x86/core/thread.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides core nanokernel fiber related primitives for the IA-32 -processor architecture. + * DESCRIPTION + * This module provides core nanokernel fiber related primitives for the IA-32 + * processor architecture. */ #ifdef CONFIG_MICROKERNEL @@ -257,7 +257,8 @@ static void _new_thread_internal(char *pStackMem, unsigned stackSize, __asm__("\t.globl _thread_entry\n" "\t.section .text\n" "_thread_entry_wrapper:\n" /* should place this func .S file and use - SECTION_FUNC */ + * SECTION_FUNC + */ "\tmovl $0, (%esp)\n" /* zero initialEFLAGS location */ "\tjmp _thread_entry\n"); #endif /* CONFIG_GDB_INFO */ diff --git a/arch/x86/include/advidle.h b/arch/x86/include/advidle.h index 75555524515..ffd6d8001c8 100644 --- a/arch/x86/include/advidle.h +++ b/arch/x86/include/advidle.h @@ -16,11 +16,11 @@ * limitations under the License. */ /* -DESCRIPTION -This header file specifies the custom advanced idle management interface. -All of the APIs declared here must be supplied by the custom advanced idle -management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc() -and _AdvIdleStart() functions. + * DESCRIPTION + * This header file specifies the custom advanced idle management interface. + * All of the APIs declared here must be supplied by the custom advanced idle + * management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc() + * and _AdvIdleStart() functions. */ #ifndef __INCadvidle diff --git a/arch/x86/include/gdt.h b/arch/x86/include/gdt.h index ff66d9cfbf5..4da3215edf8 100644 --- a/arch/x86/include/gdt.h +++ b/arch/x86/include/gdt.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This file provides definitions for the Global Descriptor Table (GDT) for the -IA-32 architecture. + * DESCRIPTION + * This file provides definitions for the Global Descriptor Table (GDT) for the + * IA-32 architecture. */ #ifndef _GDT_H diff --git a/arch/x86/include/idtEnt.h b/arch/x86/include/idtEnt.h index 44c50784dee..267918646d8 100644 --- a/arch/x86/include/idtEnt.h +++ b/arch/x86/include/idtEnt.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file provides code for constructing an IA-32 interrupt descriptor. - + * DESCRIPTION + * This header file provides code for constructing an IA-32 interrupt + * descriptor. */ #ifndef _IDTENT_H diff --git a/arch/x86/include/nano_private.h b/arch/x86/include/nano_private.h index ef26a04da85..6a05e451f0d 100644 --- a/arch/x86/include/nano_private.h +++ b/arch/x86/include/nano_private.h @@ -17,17 +17,18 @@ */ /* -DESCRIPTION -This file contains private nanokernel structures definitions and various other -definitions for the Intel Architecture 32 bit (IA-32) processor architecture. -The header include/nanokernel.h contains the public nanokernel interface -definitions, with include/arch/nanokernel/x86/arch.h supplying the -IA-32 specific portions of the public nanokernel interface. - -This file is also included by assembly language files which must #define -_ASMLANGUAGE before including this header file. Note that nanokernel assembly -source files obtains structure offset values via "absolute symbols" in the -offsets.o module. + * DESCRIPTION + * This file contains private nanokernel structures definitions and various + * other definitions for the Intel Architecture 32 bit (IA-32) processor + * architecture. + * The header include/nanokernel.h contains the public nanokernel interface + * definitions, with include/arch/nanokernel/x86/arch.h supplying the + * IA-32 specific portions of the public nanokernel interface. + * + * This file is also included by assembly language files which must #define + * _ASMLANGUAGE before including this header file. Note that nanokernel + * assembly source files obtains structure offset values via "absolute symbols" + * in the offsets.o module. */ #ifndef _NANO_PRIVATE_H @@ -602,9 +603,10 @@ typedef struct s_coopFloatReg { typedef struct s_preempFloatReg { union { - tFpRegSet fpRegs; /* threads with USE_FP utilize this format */ - tFpRegSetEx fpRegsEx; /* threads with USE_SSE utilize this - format */ + /* threads with USE_FP utilize this format */ + tFpRegSet fpRegs; + /* threads with USE_SSE utilize this format */ + tFpRegSetEx fpRegsEx; } floatRegsUnion; } tPreempFloatReg; @@ -618,9 +620,8 @@ typedef struct s_preempFloatReg { struct tcs { /* * Link to next thread in singly-linked thread list (such as - * prioritized - * list of runnable fibers, or list of fibers waiting on a nanokernel - * FIFO). + * prioritized list of runnable fibers, or list of fibers waiting on a + * nanokernel FIFO). */ struct tcs *link; @@ -656,8 +657,7 @@ struct tcs { /* * Nested exception count to maintain setting of EXC_ACTIVE flag across * outermost exception. EXC_ACTIVE is used by _Swap() lazy FP - * save/restore - * and by debug tools. + * save/restore and by debug tools. */ unsigned excNestCount; /* nested exception count */ #endif /* CONFIG_FP_SHARING || CONFIG_GDB_INFO */ @@ -673,19 +673,15 @@ struct tcs { /* * The location of all floating point related structures/fields MUST be * located at the end of struct tcs. This way only the - *fibers/tasks - * that actually utilize non-integer capabilities need to account for - * the increased memory required for storing FP state when sizing - *stacks. + * fibers/tasks that actually utilize non-integer capabilities need to + * account for the increased memory required for storing FP state when + * sizing stacks. * - * Given that stacks "grow down" on IA-32, and the TCS is - *located + * Given that stacks "grow down" on IA-32, and the TCS is located * at the start of a thread's "workspace" memory, the stacks of - *fibers/tasks - * that do not utilize floating point instruction can effectively - *consume - * the memory occupied by the 'tCoopFloatReg' and 'tPreempFloatReg' - * structures without ill effect. + * fibers/tasks that do not utilize floating point instruction can + * effectively consume the memory occupied by the 'tCoopFloatReg' and + * 'tPreempFloatReg' structures without ill effect. */ tCoopFloatReg coopFloatReg; /* non-volatile float register storage */ @@ -716,11 +712,10 @@ typedef struct s_NANO { /* * A 'current_sse' field does not exist in addition to the 'current_fp' * field since it's not possible to divide the IA-32 non-integer - * registers - * into 2 distinct blocks owned by differing threads. In other words, - * given that the 'fxnsave/fxrstor' instructions save/restore both the - * X87 FPU and XMM registers, it's not possible for a thread to only - * "own" the XMM registers. + * registers into 2 distinct blocks owned by differing threads. In + * other words, given that the 'fxnsave/fxrstor' instructions + * save/restore both the X87 FPU and XMM registers, it's not possible + * for a thread to only "own" the XMM registers. */ struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */ @@ -787,16 +782,16 @@ static inline void nanoArchInit(void) /* * Forces the inclusion of the spurious interrupt handlers. If a - * reference - * isn't made then intconnect.o is never pulled in by the linker. + * reference isn't made then intconnect.o is never pulled in by the + * linker. */ _dummy_spurious_interrupt = &__isr___SpuriousIntHandler; /* * Forces the inclusion of the exception vector stub code. If a - * reference - * isn't made then excstubs.o is never pulled in by the linker. + * reference isn't made then excstubs.o is never pulled in by the + * linker. */ _dummy_exception_vector_stub = &_ExcEnt; @@ -811,8 +806,8 @@ static inline void nanoArchInit(void) * @param fiber pointer to fiber * @param value value to set as return value * - * The register used to store the return value from a function call invocation is - * set to . It is assumed that the specified is pending, and + * The register used to store the return value from a function call invocation + * is set to . It is assumed that the specified is pending, and * thus the fibers context is stored in its TCS. * * @return N/A diff --git a/arch/x86/include/start_task_arch.h b/arch/x86/include/start_task_arch.h index 293db9ca60c..0a501a3021c 100644 --- a/arch/x86/include/start_task_arch.h +++ b/arch/x86/include/start_task_arch.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Intel-specific parts of start_task(). Only FP functionality currently. + * DESCRIPTION + * Intel-specific parts of start_task(). Only FP functionality currently. */ #ifndef _START_TASK_ARCH__H_ diff --git a/arch/x86/include/swapstk.h b/arch/x86/include/swapstk.h index 07c20a668be..2ba157c2844 100644 --- a/arch/x86/include/swapstk.h +++ b/arch/x86/include/swapstk.h @@ -17,14 +17,14 @@ */ /* -DESCRIPTION -This file details the stack frame generated by _Swap() when it saves a task -or fiber's context. This is specific to the IA-32 processor architecture. - -NOTE: _Swap() does not use this file as it uses the push instruction to save a -context. Changes to the file will not automatically be picked up by _Swap(). -Conversely, changes to _Swap() should be mirrored here if the stack frame is -modified. + * DESCRIPTION + * This file details the stack frame generated by _Swap() when it saves a task + * or fiber's context. This is specific to the IA-32 processor architecture. + * + * NOTE: _Swap() does not use this file as it uses the push instruction to + * save a context. Changes to the file will not automatically be picked up by + * _Swap(). Conversely, changes to _Swap() should be mirrored here if the + * stack frame is modified. */ #ifndef _SWAPSTK_H diff --git a/arch/x86/platforms/galileo/board.h b/arch/x86/platforms/galileo/board.h index cf4cbb5283e..e81b1d1256c 100644 --- a/arch/x86/platforms/galileo/board.h +++ b/arch/x86/platforms/galileo/board.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for -the 'galileo' platform. + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for + * the 'galileo' platform. */ #ifndef __INCboardh diff --git a/arch/x86/platforms/galileo/galileo.c b/arch/x86/platforms/galileo/galileo.c index 5410d375355..486de5fd390 100644 --- a/arch/x86/platforms/galileo/galileo.c +++ b/arch/x86/platforms/galileo/galileo.c @@ -17,12 +17,12 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the galileo platform. - -Implementation Remarks: -Handlers for the secondary serial port have not been added. + * DESCRIPTION + * This module provides routines to initialize and support board-level hardware + * for the galileo platform. + * + * Implementation Remarks: + * Handlers for the secondary serial port have not been added. */ #include diff --git a/arch/x86/platforms/galileo/galileo_pinmux.c b/arch/x86/platforms/galileo/galileo_pinmux.c index 478402a666e..e25e366bf1e 100644 --- a/arch/x86/platforms/galileo/galileo_pinmux.c +++ b/arch/x86/platforms/galileo/galileo_pinmux.c @@ -552,8 +552,11 @@ uint8_t _galileo_set_pin(struct device *port, uint8_t pin, uint8_t func) /* NUM_PIN_FUNCS being the number of alt functions */ mux_index = NUM_PIN_FUNCS * pin; - mux_index += func; /* functions are in numeric order, we can just - skip to the index needed */ + /* + * functions are in numeric order, we can just skip to the index + * needed + */ + mux_index += func; enable = &_galileo_path[mux_index]; diff --git a/arch/x86/platforms/ia32/board.h b/arch/x86/platforms/ia32/board.h index 3df711a867d..65b48f47127 100644 --- a/arch/x86/platforms/ia32/board.h +++ b/arch/x86/platforms/ia32/board.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for -the 'ia32' platform. + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for + * the 'ia32' platform. */ #ifndef __INCboardh diff --git a/arch/x86/platforms/ia32/ia32.c b/arch/x86/platforms/ia32/ia32.c index 21298e04659..d565fa23737 100644 --- a/arch/x86/platforms/ia32/ia32.c +++ b/arch/x86/platforms/ia32/ia32.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the ia32 platform. + * DESCRIPTION + * This module provides routines to initialize and support board-level hardware + * for the ia32 platform. */ #include diff --git a/arch/x86/platforms/ia32_pci/board.h b/arch/x86/platforms/ia32_pci/board.h index 0faed1d7ae7..44de6d0fae9 100644 --- a/arch/x86/platforms/ia32_pci/board.h +++ b/arch/x86/platforms/ia32_pci/board.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to specify and describe board-level aspects for -the 'ia32_pci' platform. + * DESCRIPTION + * This header file is used to specify and describe board-level aspects for + * the 'ia32_pci' platform. */ #ifndef __INCboardh diff --git a/arch/x86/platforms/ia32_pci/ia32_pci.c b/arch/x86/platforms/ia32_pci/ia32_pci.c index f1604f99886..e7b4aae3c0a 100644 --- a/arch/x86/platforms/ia32_pci/ia32_pci.c +++ b/arch/x86/platforms/ia32_pci/ia32_pci.c @@ -17,12 +17,12 @@ */ /* -DESCRIPTION -This module provides routines to initialize and support board-level hardware -for the ia32_pci platform. - -Implementation Remarks: -Handlers for the secondary serial port have not been added. + * DESCRIPTION + * This module provides routines to initialize and support board-level hardware + * for the ia32_pci platform. + * + * Implementation Remarks: + * Handlers for the secondary serial port have not been added. */ #include diff --git a/drivers/adc/adc_ti_adc108s102.c b/drivers/adc/adc_ti_adc108s102.c index fb4f322cad4..5ffa12bcf1c 100644 --- a/drivers/adc/adc_ti_adc108s102.c +++ b/drivers/adc/adc_ti_adc108s102.c @@ -173,9 +173,11 @@ static void _ti_adc108s102_spi_cb(struct device *spi_dev, static void ti_adc108s102_enable(struct device *dev) { - /* There is nothing to be done. If there is no sampling going on, + /* + * There is nothing to be done. If there is no sampling going on, * the chip will put itself on power-saving mode (that is because - * SPI will release CS) */ + * SPI will release CS) + */ } static void ti_adc108s102_disable(struct device *dev) diff --git a/drivers/bluetooth/uart.c b/drivers/bluetooth/uart.c index cd4a83d0164..40d03c4067a 100644 --- a/drivers/bluetooth/uart.c +++ b/drivers/bluetooth/uart.c @@ -263,6 +263,7 @@ static void bt_uart_setup(struct device *uart, struct uart_init_info *info) /* Drain the fifo */ while (uart_irq_rx_ready(uart)) { unsigned char c; + uart_fifo_read(uart, &c, 1); } diff --git a/drivers/console/ipi_console_sender.c b/drivers/console/ipi_console_sender.c index 40c55c4e5bf..f754117dd7e 100644 --- a/drivers/console/ipi_console_sender.c +++ b/drivers/console/ipi_console_sender.c @@ -29,8 +29,10 @@ static int consoleOut(int character) return character; } - /* We just stash the character into the id field and don't supply - * any extra data */ + /* + * We just stash the character into the id field and don't supply + * any extra data + */ ipi_send(ipi_console_device, 1, character, NULL, 0); return character; diff --git a/drivers/console/uart_console.c b/drivers/console/uart_console.c index d19957afa0a..6b35370c6ca 100644 --- a/drivers/console/uart_console.c +++ b/drivers/console/uart_console.c @@ -17,10 +17,10 @@ */ /* - DESCRIPTION - - Serial console driver. - Hooks into the printk and fputc (for printf) modules. Poll driven. + * DESCRIPTION + * + * Serial console driver. + * Hooks into the printk and fputc (for printf) modules. Poll driven. */ #include @@ -51,6 +51,7 @@ static int consoleIn(void) { #ifdef UART_CONSOLE_DEV unsigned char c; + if (uart_poll_in(UART_CONSOLE_DEV, &c) < 0) return EOF; else diff --git a/drivers/grove/lcd_rgb.c b/drivers/grove/lcd_rgb.c index 580509e6359..e6a0d3355a4 100644 --- a/drivers/grove/lcd_rgb.c +++ b/drivers/grove/lcd_rgb.c @@ -302,8 +302,10 @@ int glcd_initialize(struct device *port) */ - /* We're here! Let's just make sure we've had enough time for the - * VDD to power on, so pause a little here, 30 ms min, so we go 50 */ + /* + * We're here! Let's just make sure we've had enough time for the + * VDD to power on, so pause a little here, 30 ms min, so we go 50 + */ DBG("Grove LCD: delay 50 ms while the VDD powers on\n"); _sleep(50); diff --git a/drivers/i2c/i2c_dw.c b/drivers/i2c/i2c_dw.c index 706c002e7b0..2f94af6d222 100644 --- a/drivers/i2c/i2c_dw.c +++ b/drivers/i2c/i2c_dw.c @@ -64,9 +64,10 @@ static inline void _i2c_dw_data_ask(struct device *dev, uint8_t restart) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; + uint32_t data; + volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; - uint32_t data; /* No more bytes to request */ if (dw->request_bytes == 0) { @@ -95,6 +96,7 @@ static void _i2c_dw_data_read(struct device *dev) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; + volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; @@ -123,9 +125,10 @@ static void _i2c_dw_data_send(struct device *dev) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; + uint32_t data = 0; + volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; - uint32_t data = 0; /* Nothing to send anymore, mask the interrupt */ if (dw->tx_len == 0) { @@ -170,11 +173,12 @@ static inline void _i2c_dw_transfer_complete(struct device *dev) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; - volatile struct i2c_dw_registers * const regs = - (struct i2c_dw_registers *)rom->base_address; uint32_t cb_type = 0; uint32_t value; + volatile struct i2c_dw_registers * const regs = + (struct i2c_dw_registers *)rom->base_address; + if (dw->state == I2C_DW_CMD_ERROR) { cb_type = I2C_CB_ERROR; } else if (dw->tx_buffer && !dw->tx_len) { @@ -200,11 +204,11 @@ void i2c_dw_isr(struct device *port) { struct i2c_dw_rom_config const * const rom = port->config->config_info; struct i2c_dw_dev_config * const dw = port->driver_data; + uint32_t value = 0; + volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; - uint32_t value = 0; - #if CONFIG_SHARED_IRQ /* If using with shared IRQ, this function will be called * by the shared IRQ driver. So check here if the interrupt @@ -390,11 +394,12 @@ static int _i2c_dw_transfer_init(struct device *dev, { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; - volatile struct i2c_dw_registers * const regs = - (struct i2c_dw_registers *)rom->base_address; uint32_t value = 0; int ret; + volatile struct i2c_dw_registers * const regs = + (struct i2c_dw_registers *)rom->base_address; + dw->state |= I2C_DW_BUSY; if (write_len > 0) { dw->state |= I2C_DW_CMD_SEND; @@ -440,9 +445,10 @@ static int i2c_dw_transfer(struct device *dev, uint16_t slave_address, uint32_t flags) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; + int ret; + volatile struct i2c_dw_registers * const regs = (struct i2c_dw_registers *)rom->base_address; - int ret; /* First step, check if there is current activity */ if (regs->ic_status.bits.activity) { @@ -481,12 +487,13 @@ static int i2c_dw_poll_transfer(struct device *dev, { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; - volatile struct i2c_dw_registers * const regs = - (struct i2c_dw_registers *)rom->base_address; uint32_t value = 0; uint32_t start_time; int ret = DEV_OK; + volatile struct i2c_dw_registers * const regs = + (struct i2c_dw_registers *)rom->base_address; + if (!regs->ic_con.bits.master_mode) { /* Only acting as master is supported */ return DEV_INVALID_OP; @@ -592,11 +599,12 @@ static int i2c_dw_runtime_configure(struct device *dev, uint32_t config) { struct i2c_dw_rom_config const * const rom = dev->config->config_info; struct i2c_dw_dev_config * const dw = dev->driver_data; - volatile struct i2c_dw_registers * const regs = - (struct i2c_dw_registers *)rom->base_address; uint32_t value = 0; uint32_t rc = DEV_OK; + volatile struct i2c_dw_registers * const regs = + (struct i2c_dw_registers *)rom->base_address; + dw->app_config.raw = config; /* Make sure we have a supported speed for the DesignWare model */ @@ -758,6 +766,7 @@ int i2c_dw_initialize(struct device *port) { struct i2c_dw_rom_config const * const rom = port->config->config_info; struct i2c_dw_dev_config * const dev = port->driver_data; + volatile struct i2c_dw_registers *regs; if (!i2c_dw_pci_setup(port)) { diff --git a/drivers/interrupt_controller/i8259.c b/drivers/interrupt_controller/i8259.c index e46d3584193..d17bf123267 100644 --- a/drivers/interrupt_controller/i8259.c +++ b/drivers/interrupt_controller/i8259.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This module disables the Intel 8259A PIC (Programmable Interrupt Controller) -to prevent it from generating spurious interrupts. -*/ + * DESCRIPTION + * This module disables the Intel 8259A PIC (Programmable Interrupt Controller) + * to prevent it from generating spurious interrupts. + */ #include diff --git a/drivers/interrupt_controller/loapic_intr.c b/drivers/interrupt_controller/loapic_intr.c index 74e74152f87..17f8f8bb6c6 100644 --- a/drivers/interrupt_controller/loapic_intr.c +++ b/drivers/interrupt_controller/loapic_intr.c @@ -17,74 +17,74 @@ */ /* -DESCRIPTION -This module is a driver for the local APIC/xAPIC (Advanced Programmable -Interrupt Controller) in P6 (PentiumPro, II, III) family processors -and P7 (Pentium4) family processors. The local APIC/xAPIC is included -in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors. -Beginning with the P6 family processors, the presence or absence of an -on-chip local APIC can be detected using the CPUID instruction. When the -CPUID instruction is executed, bit 9 of the feature flags returned in the -EDX register indicates the presence (set) or absence (clear) of an on-chip -local APIC. - -The local APIC performs two main functions for the processor: - - It processes local external interrupts that the processor receives at its - interrupt pins and local internal interrupts that software generates. - - It communicates with an external IO APIC - chip. The external IO APIC receives external interrupt events from - peripheral and direct them to the local APIC. The IO APIC is - part of Intel's system chip set. -The local APIC controls the dispatching of interrupts (to its associated -processor) that it receives either locally or from the IO APIC. It provides -facilities for queuing, nesting and masking of interrupts. It handles the -interrupt delivery protocol with its local processor and accesses to APIC -registers. -A timer on the local APIC allows local generation of interrupts, and -local interrupt pins permit local reception of processor-specific interrupts. -The local APIC can be disabled and used in conjunction with a standard 8259A -style interrupt controller. Disabling the local APIC can be done in hardware -for the Pentium processors or in software for the P6 and P7 (Pentium4) family -processors. - -The local APIC in the Pentium4 processors (called the xAPIC) is an extension -of the local APIC found in the P6 family processors. The primary difference -between the APIC architecture and xAPIC architecture is that with Pentium4 -processors, the local xAPICs and IO xAPIC communicate with one another through -the processors system bus; whereas, with the P6 family processors, communication -between the local APICs and the IO APIC is handled through a dedicated 3-wire -APIC bus. Also, some of the architectural features of the local APIC have been -extended and/or modified in the local xAPIC. - -This driver contains three routines for use. They are: -_loapic_init() initializes the Local APIC for the interrupt mode chosen. -_loapic_enable()/disable() enables / disables the Local APIC. - -Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT. - -Virtual Wire Mode is one of three interrupt modes defined by the MP -specification. In this mode, interrupts are generated by the 8259A equivalent -PICs (if present) and delivered to the Boot Strap Processor by -the local APIC that is programmed to act as a "virtual Wire"; that -is, the local APIC is logically indistinguishable from a hardware -connection. This is a uniprocessor compatibility mode. - -The local and IO APICs support interrupts in the range of 32 to 255. -Interrupt priority is implied by its vector, according to the following -relationship: "priority = vector / 16". -Here the quotient is rounded down to the nearest integer value to determine -the priority, with 1 being the lowest and 15 is the highest. Because vectors -0 through 31 are reserved for exclusive use by the processor, the priority of -user defined interrupts range from 2 to 15. A value of 15 in the Interrupt -Class field of the Task Priority Register (TPR) will mask off all interrupts, -which require interrupt service. -The P6 family processor's local APIC includes an in-service entry and a holding -entry for each priority level. To avoid losing interrupts, software should -allocate no more than 2 interrupt vectors per priority. The Pentium4 processor -expands this support of all acceptance of two interrupts per vector rather than -per priority level. - -INCLUDE FILES: loapic.h + * DESCRIPTION + * This module is a driver for the local APIC/xAPIC (Advanced Programmable + * Interrupt Controller) in P6 (PentiumPro, II, III) family processors + * and P7 (Pentium4) family processors. The local APIC/xAPIC is included + * in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors. + * Beginning with the P6 family processors, the presence or absence of an + * on-chip local APIC can be detected using the CPUID instruction. When the + * CPUID instruction is executed, bit 9 of the feature flags returned in the + * EDX register indicates the presence (set) or absence (clear) of an on-chip + * local APIC. + * + * The local APIC performs two main functions for the processor: + * - It processes local external interrupts that the processor receives at its + * interrupt pins and local internal interrupts that software generates. + * - It communicates with an external IO APIC + * chip. The external IO APIC receives external interrupt events from + * peripheral and direct them to the local APIC. The IO APIC is + * part of Intel's system chip set. + * The local APIC controls the dispatching of interrupts (to its associated + * processor) that it receives either locally or from the IO APIC. It provides + * facilities for queuing, nesting and masking of interrupts. It handles the + * interrupt delivery protocol with its local processor and accesses to APIC + * registers. + * A timer on the local APIC allows local generation of interrupts, and + * local interrupt pins permit local reception of processor-specific interrupts. + * The local APIC can be disabled and used in conjunction with a standard 8259A + * style interrupt controller. Disabling the local APIC can be done in hardware + * for the Pentium processors or in software for the P6 and P7 (Pentium4) family + * processors. + * + * The local APIC in the Pentium4 processors (called the xAPIC) is an extension + * of the local APIC found in the P6 family processors. The primary difference + * between the APIC architecture and xAPIC architecture is that with Pentium4 + * processors, the local xAPICs and IO xAPIC communicate with one another + * through the processors system bus; whereas, with the P6 family processors, + * communication between the local APICs and the IO APIC is handled through a + * dedicated 3-wire APIC bus. Also, some of the architectural features of the + * local APIC have been extended and/or modified in the local xAPIC. + * + * This driver contains three routines for use. They are: + * _loapic_init() initializes the Local APIC for the interrupt mode chosen. + * _loapic_enable()/disable() enables / disables the Local APIC. + * + * Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT. + * + * Virtual Wire Mode is one of three interrupt modes defined by the MP + * specification. In this mode, interrupts are generated by the 8259A + * equivalent PICs (if present) and delivered to the Boot Strap Processor by + * the local APIC that is programmed to act as a "virtual Wire"; that + * is, the local APIC is logically indistinguishable from a hardware + * connection. This is a uniprocessor compatibility mode. + * + * The local and IO APICs support interrupts in the range of 32 to 255. + * Interrupt priority is implied by its vector, according to the following + * relationship: "priority = vector / 16". + * Here the quotient is rounded down to the nearest integer value to determine + * the priority, with 1 being the lowest and 15 is the highest. Because vectors + * 0 through 31 are reserved for exclusive use by the processor, the priority of + * user defined interrupts range from 2 to 15. A value of 15 in the Interrupt + * Class field of the Task Priority Register (TPR) will mask off all interrupts, + * which require interrupt service. + * The P6 family processor's local APIC includes an in-service entry and a + * holding entry for each priority level. To avoid losing interrupts, software + * should allocate no more than 2 interrupt vectors per priority. The Pentium4 + * processor expands this support of all acceptance of two interrupts per vector + * rather than per priority level. + * + * INCLUDE FILES: loapic.h */ #include diff --git a/drivers/interrupt_controller/system_apic.c b/drivers/interrupt_controller/system_apic.c index 386ba027831..b868d364938 100644 --- a/drivers/interrupt_controller/system_apic.c +++ b/drivers/interrupt_controller/system_apic.c @@ -143,8 +143,10 @@ int _SysIntVecAlloc(unsigned int irq, unsigned int priority, } else { _loapic_int_vec_set(irq - CONFIG_IOAPIC_NUM_RTES, vector); - /* specify that the EOI handler in loApicIntr.c driver - * be invoked */ + /* + * specify that the EOI handler in loApicIntr.c driver + * be invoked + */ *eoiRtn = (NANO_EOI_GET_FUNC)_loapic_eoi; *eoiParamRequired = 0; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b9a489ab8bd..81e40953061 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -17,67 +17,66 @@ */ /* -DESCRIPTION -Module implements routines for PCI bus initialization and query. - -USAGE -To use the driver, the platform must define: -- Numbers of BUSes: - - PCI_BUS_NUMBERS; -- Register addresses: - - PCI_CTRL_ADDR_REG; - - PCI_CTRL_DATA_REG; -- pci_pin2irq() - the routine that converts the PCI interrupt pin - number to IRQ number. - -About scanning the PCI buses: -At every new usage of this API, the code should call pci_bus_scan_init(). -It should own a struct pci_dev_info, filled in with the parameters it is -interested to look for: class and/or vendor_id/device_id. - -Then it can loop on pci_bus_scan() providing a pointer on that structure. -Such function can be called as long as it returns 1. At every successful -return of pci_bus_scan() it means the provided structure pointer will have -been updated with the current scan result which the code might be interested -in. On pci_bus_scan() returning 0, the code should discard the result and -stop calling pci_bus_scan(). If it wants to retrieve the result, it will -have to restart the procedure all over again. - -EXAMPLE -struct pci_dev_info info = { - .class = PCI_CLASS_COMM_CTLR -}; - -pci_bus_scan_init(); - -while (pci_bus_scan(&info) { - // do something with "info" which holds a valid result, i.e. some - // device information matching the PCI class PCI_CLASS_COMM_CTLR -} - -INTERNALS -The whole logic runs around a structure: struct lookup_data, which exists -on one instanciation called 'lookup'. -Such structure is used for 2 distinct roles: -- to match devices the caller is looking for -- to loop on PCI bus, devices, function and BARs - -The search criterias are the class and/or the vendor_id/device_id of a PCI -device. The caller first initializes the lookup structure by calling -pci_bus_scan_init(), which will reset the search criterias as well as the -loop paramaters to 0. At the very first subsequent call of pci_bus_scan() -the lookup structure will store the search criterias. Then the loop starts. -For each bus it will run through each device on which it will loop on each -function and BARs, as long as the criterias does not match or until it hit -the limit of bus/dev/functions to scan. - -On a successful match, it will stop the loop, fill in the caller's -pci_dev_info structure with the found device information, and return 1. -Hopefully, the lookup structure still remembers where it stopped and the -original search criterias. Thus, when the caller asks to scan again for -a possible result next, the loop will restart where it stopped. -That will work as long as there are relevant results found. - + * DESCRIPTION + * Module implements routines for PCI bus initialization and query. + * + * USAGE + * To use the driver, the platform must define: + * - Numbers of BUSes: + * - PCI_BUS_NUMBERS; + * - Register addresses: + * - PCI_CTRL_ADDR_REG; + * - PCI_CTRL_DATA_REG; + * - pci_pin2irq() - the routine that converts the PCI interrupt pin + * number to IRQ number. + * + * About scanning the PCI buses: + * At every new usage of this API, the code should call pci_bus_scan_init(). + * It should own a struct pci_dev_info, filled in with the parameters it is + * interested to look for: class and/or vendor_id/device_id. + * + * Then it can loop on pci_bus_scan() providing a pointer on that structure. + * Such function can be called as long as it returns 1. At every successful + * return of pci_bus_scan() it means the provided structure pointer will have + * been updated with the current scan result which the code might be interested + * in. On pci_bus_scan() returning 0, the code should discard the result and + * stop calling pci_bus_scan(). If it wants to retrieve the result, it will + * have to restart the procedure all over again. + * + * EXAMPLE + * struct pci_dev_info info = { + * .class = PCI_CLASS_COMM_CTLR + * }; + * + * pci_bus_scan_init(); + * + * while (pci_bus_scan(&info) { + * // do something with "info" which holds a valid result, i.e. some + * // device information matching the PCI class PCI_CLASS_COMM_CTLR + * } + * + * INTERNALS + * The whole logic runs around a structure: struct lookup_data, which exists + * on one instanciation called 'lookup'. + * Such structure is used for 2 distinct roles: + * - to match devices the caller is looking for + * - to loop on PCI bus, devices, function and BARs + * + * The search criterias are the class and/or the vendor_id/device_id of a PCI + * device. The caller first initializes the lookup structure by calling + * pci_bus_scan_init(), which will reset the search criterias as well as the + * loop paramaters to 0. At the very first subsequent call of pci_bus_scan() + * the lookup structure will store the search criterias. Then the loop starts. + * For each bus it will run through each device on which it will loop on each + * function and BARs, as long as the criterias does not match or until it hit + * the limit of bus/dev/functions to scan. + * + * On a successful match, it will stop the loop, fill in the caller's + * pci_dev_info structure with the found device information, and return 1. + * Hopefully, the lookup structure still remembers where it stopped and the + * original search criterias. Thus, when the caller asks to scan again for + * a possible result next, the loop will restart where it stopped. + * That will work as long as there are relevant results found. */ #include diff --git a/drivers/pci/pci_config.c b/drivers/pci/pci_config.c index 3484f05cf60..37e7bb89af0 100644 --- a/drivers/pci/pci_config.c +++ b/drivers/pci/pci_config.c @@ -17,10 +17,10 @@ */ /* -DESCRIPTION - -This module implements the PCI config space access functions - + * DESCRIPTION + * + * This module implements the PCI config space access functions + * */ #include diff --git a/drivers/pci/pci_interface.c b/drivers/pci/pci_interface.c index ff76db30113..337deb31425 100644 --- a/drivers/pci/pci_interface.c +++ b/drivers/pci/pci_interface.c @@ -17,10 +17,9 @@ */ /* -DESCRIPTION - -This module implements the PCI H/W access functions. - + * DESCRIPTION + * + * This module implements the PCI H/W access functions. */ #include diff --git a/drivers/pci/pci_legacy_bridge.c b/drivers/pci/pci_legacy_bridge.c index e0a549adcbe..e2ca3dce295 100644 --- a/drivers/pci/pci_legacy_bridge.c +++ b/drivers/pci/pci_legacy_bridge.c @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -Module provides routines for utilizing the PCI legacy bridge, including -detection of the bridge and using the bridge to configure the routing between -PCI interrupt pins and IRQs. -*/ + * DESCRIPTION + * Module provides routines for utilizing the PCI legacy bridge, including + * detection of the bridge and using the bridge to configure the routing between + * PCI interrupt pins and IRQs. + */ #include #include diff --git a/drivers/random/rand32_timer.c b/drivers/random/rand32_timer.c index 26638cd64a9..c1ede5a51d5 100644 --- a/drivers/random/rand32_timer.c +++ b/drivers/random/rand32_timer.c @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This module provides a non-random implementation of sys_rand32_get(), which is -not meant to be used in a final product as a truly random number generator. It -was provided to allow testing on a platform that does not (yet) provide a -random number generator. + * DESCRIPTION + * This module provides a non-random implementation of sys_rand32_get(), which + * is not meant to be used in a final product as a truly random number + * generator. It was provided to allow testing on a platform that does not (yet) + * provide a random number generator. */ #include diff --git a/drivers/random/rand32_timestamp.c b/drivers/random/rand32_timestamp.c index 311c1252d01..9d6ad841a89 100644 --- a/drivers/random/rand32_timestamp.c +++ b/drivers/random/rand32_timestamp.c @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This module provides a non-random implementation of sys_rand32_get(), which is -not meant to be used in a final product as a truly random number generator. It -was provided to allow testing on a platform that does not (yet) provide a -random number generator. + * DESCRIPTION + * This module provides a non-random implementation of sys_rand32_get(), which + * is not meant to be used in a final product as a truly random number + * generator. It was provided to allow testing on a platform that does not (yet) + * provide a random number generator. */ #include diff --git a/drivers/serial/stellarisUartDrv.c b/drivers/serial/stellarisUartDrv.c index 0e1adff1174..7d52e54f87f 100644 --- a/drivers/serial/stellarisUartDrv.c +++ b/drivers/serial/stellarisUartDrv.c @@ -163,15 +163,19 @@ static void baudrate_set(struct device *dev, div = (16 * baudrate); rem = sys_clk_freq_hz % div; - /* floating part of baud rate (LM3S6965 p.433), equivalent to - * [float part of (SYSCLK / div)] * 64 + 0.5 */ + /* + * floating part of baud rate (LM3S6965 p.433), equivalent to + * [float part of (SYSCLK / div)] * 64 + 0.5 + */ brdf = ((((rem * 64) << 1) / div) + 1) >> 1; /* integer part of baud rate (LM3S6965 p.433) */ brdi = sys_clk_freq_hz / div; - /* those registers are 32-bit, but the reserved bits should be - * preserved */ + /* + * those registers are 32-bit, but the reserved bits should be + * preserved + */ uart->ibrd = (uint16_t)(brdi & 0xffff); /* 16 bits */ uart->fbrd = (uint8_t)(brdf & 0x3f); /* 6 bits */ } diff --git a/drivers/simple/uart.c b/drivers/simple/uart.c index 3f009c0a7fc..3975ccff3eb 100644 --- a/drivers/simple/uart.c +++ b/drivers/simple/uart.c @@ -82,6 +82,7 @@ static void uart_simple_setup(struct device *uart, struct uart_init_info *info) /* Drain the fifo */ while (uart_irq_rx_ready(uart)) { unsigned char c; + uart_fifo_read(uart, &c, 1); } diff --git a/drivers/timer/arcv2_timer0.c b/drivers/timer/arcv2_timer0.c index 916058bf9cd..3e9da62c560 100644 --- a/drivers/timer/arcv2_timer0.c +++ b/drivers/timer/arcv2_timer0.c @@ -17,12 +17,13 @@ */ /* -DESCRIPTION -This module implements a kernel device driver for the ARCv2 processor timer 0 -and provides the standard "system clock driver" interfaces. - -\INTERNAL IMPLEMENTATION DETAILS -The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero counter. + * DESCRIPTION + * This module implements a kernel device driver for the ARCv2 processor timer 0 + * and provides the standard "system clock driver" interfaces. + * + * \INTERNAL IMPLEMENTATION DETAILS + * The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero + * counter. */ #include diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c index 56084acdafb..5ae2767efab 100644 --- a/drivers/timer/cortex_m_systick.c +++ b/drivers/timer/cortex_m_systick.c @@ -17,24 +17,24 @@ */ /* -DESCRIPTION -This module implements the kernel's CORTEX-M ARM's systick device driver. -It provides the standard kernel "system clock driver" interfaces. - -The driver utilizes systick to provide kernel ticks. - -\INTERNAL IMPLEMENTATION DETAILS -The systick device provides a 24-bit clear-on-write, decrementing, -wrap-on-zero counter. Only edge sensitive triggered interrupt is supported. - -\INTERNAL PACKAGING DETAILS -The systick device driver is part of the microkernel in both a monolithic kernel -system and a split kernel system; it is not included in the nanokernel portion -of a split kernel. - -The device driver is also part of a nanokernel-only system, but omits more -complex capabilities (such as tickless idle support) that are only used in -conjunction with a microkernel. + * DESCRIPTION + * This module implements the kernel's CORTEX-M ARM's systick device driver. + * It provides the standard kernel "system clock driver" interfaces. + * + * The driver utilizes systick to provide kernel ticks. + * + * \INTERNAL IMPLEMENTATION DETAILS + * The systick device provides a 24-bit clear-on-write, decrementing, + * wrap-on-zero counter. Only edge sensitive triggered interrupt is supported. + * + * \INTERNAL PACKAGING DETAILS + * The systick device driver is part of the microkernel in both a monolithic + * kernel system and a split kernel system; it is not included in the + * nanokernel portion of a split kernel. + * + * The device driver is also part of a nanokernel-only system, but omits more + * complex capabilities (such as tickless idle support) that are only used in + * conjunction with a microkernel. */ #include @@ -477,20 +477,19 @@ void _timer_idle_enter(int32_t ticks /* system ticks */ if ((ticks == -1) || (ticks > max_system_ticks)) { /* * We've been asked to fire the timer so far in the future that - * the - * required count value would not fit in the 24-bit reload + * the required count value would not fit in the 24-bit reload * register. * Instead, we program for the maximum programmable interval - * minus one - * system tick to prevent overflow when the left over count read - * earlier - * is added. + * minus one system tick to prevent overflow when the left over + * count read earlier is added. */ idle_original_count += max_load_value - default_load_value; idle_original_ticks = max_system_ticks - 1; } else { - /* leave one tick of buffer to have to time react when coming - * back */ + /* + * leave one tick of buffer to have to time react when coming + * back + */ idle_original_ticks = ticks - 1; idle_original_count += idle_original_ticks * default_load_value; } diff --git a/drivers/timer/hpet.c b/drivers/timer/hpet.c index 2801180a8a6..6feba9c588d 100644 --- a/drivers/timer/hpet.c +++ b/drivers/timer/hpet.c @@ -17,37 +17,41 @@ */ /* -DESCRIPTION -This module implements a kernel device driver for the Intel High Precision -Event Timer (HPET) device, and provides the standard "system clock driver" -interfaces. - -The driver utilizes HPET timer0 to provide kernel ticks. - -\INTERNAL IMPLEMENTATION DETAILS -The HPET device driver makes no assumption about the initial state of the HPET, -and explicitly puts the device into a reset-like state. It also assumes that -the main up counter never wraps around to 0 during the lifetime of the system. - -The platform can configure the HPET to use level rather than the default edge -sensitive interrupts by enabling the following configuration parameters: -CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW - -When not configured to support tickless idle timer0 is programmed in periodic -mode so it automatically generates a single interrupt per kernel tick interval. - -When configured to support tickless idle timer0 is programmed in one-shot mode. -When the CPU is not idling the timer interrupt handler sets the timer to expire -when the next kernel tick is due, waits for this to occur, and then repeats -this "ad infinitum". When the CPU begins idling the timer driver reprograms -the expiry time for the timer (thereby overriding the previously scheduled -timer interrupt) and waits for the timer to expire or for a non-timer interrupt -to occur. When the CPU ceases idling the driver determines how many complete -ticks have elapsed, reprograms the timer so that it expires on the next tick, -and announces the number of elapsed ticks (if any) to the microkernel. - -In a nanokernel-only system this device driver omits more complex capabilities -(such as tickless idle support) that are only used with a microkernel. + * DESCRIPTION + * This module implements a kernel device driver for the Intel High Precision + * Event Timer (HPET) device, and provides the standard "system clock driver" + * interfaces. + * + * The driver utilizes HPET timer0 to provide kernel ticks. + * + * \INTERNAL IMPLEMENTATION DETAILS + * The HPET device driver makes no assumption about the initial state of the + * HPET, and explicitly puts the device into a reset-like state. It also assumes + * that the main up counter never wraps around to 0 during the lifetime of the + * system. + * + * The platform can configure the HPET to use level rather than the default edge + * sensitive interrupts by enabling the following configuration parameters: + * CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW + * + * When not configured to support tickless idle timer0 is programmed in periodic + * mode so it automatically generates a single interrupt per kernel tick + * interval. + * + * When configured to support tickless idle timer0 is programmed in one-shot + * mode. When the CPU is not idling the timer interrupt handler sets the timer + * to expire when the next kernel tick is due, waits for this to occur, and then + * repeats this "ad infinitum". When the CPU begins idling the timer driver + * reprograms the expiry time for the timer (thereby overriding the previously + * scheduled timer interrupt) and waits for the timer to expire or for a + * non-timer interrupt to occur. When the CPU ceases idling the driver + * determines how many complete ticks have elapsed, reprograms the timer so that + * it expires on the next tick, and announces the number of elapsed ticks (if + * any) to the microkernel. + * + * In a nanokernel-only system this device driver omits more complex + * capabilities (such as tickless idle support) that are only used with a + * microkernel. */ #include @@ -111,21 +115,21 @@ extern struct nano_stack _k_command_stack; */ #define _HPET_GENERAL_INT_STATUS ((volatile uint32_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_INT_STATUS_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_INT_STATUS_REG)) #define _HPET_MAIN_COUNTER_VALUE ((volatile uint64_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG)) #define _HPET_MAIN_COUNTER_LSW ((volatile uint32_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG)) #define _HPET_MAIN_COUNTER_MSW ((volatile uint32_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG + 0x4)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG + 0x4)) #define _HPET_TIMER0_CONFIG_CAPS ((volatile uint64_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_CONFIG_CAPS_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_CONFIG_CAPS_REG)) #define _HPET_TIMER0_COMPARATOR ((volatile uint64_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_COMPARATOR_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_COMPARATOR_REG)) #define _HPET_TIMER0_FSB_INT_ROUTE ((volatile uint64_t *) \ - (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_FSB_INT_ROUTE_REG)) + (CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_FSB_INT_ROUTE_REG)) /* general capabilities register macros */ @@ -193,14 +197,14 @@ extern uint32_t _hw_irq_to_c_handler_latency; extern int32_t _sys_idle_elapsed_ticks; -static uint32_t __noinit counter_load_value; /* main counter units - per system tick */ -static uint64_t counter_last_value = - 0; /* counter value for most recent tick */ -static int32_t programmed_ticks = - 1; /* # ticks timer is programmed for */ -static int stale_irq_check = - 0; /* is stale interrupt possible? */ +/* main counter units per system tick */ +static uint32_t __noinit counter_load_value; +/* counter value for most recent tick */ +static uint64_t counter_last_value = 0; +/* # ticks timer is programmed for */ +static int32_t programmed_ticks = 1; +/* is stale interrupt possible? */ +static int stale_irq_check = 0; /** * @@ -389,23 +393,22 @@ void _timer_idle_exit(void) /* * update # of ticks since last tick event was announced, * so that this value is available to ISRs that run before the - * timer - * interrupt handler runs (which is unlikely, but could happen) + * timer interrupt handler runs (which is unlikely, but could + * happen) */ _sys_idle_elapsed_ticks = programmed_ticks - 1; /* * Announce elapsed ticks to the microkernel. Note we are - * guaranteed - * that the timer ISR will execute first before the tick event - * is - * serviced. + * guaranteed that the timer ISR will execute first before the + * tick event is serviced. */ _sys_clock_tick_announce(); /* timer interrupt handler reprograms the timer for the next - * tick */ + * tick + */ return; } @@ -422,9 +425,8 @@ void _timer_idle_exit(void) * the microkernel, which gets informed of the correct number of elapsed * ticks when the following tick finally occurs; however, any ISRs that * access _sys_idle_elapsed_ticks to determine the current time may be - *misled - * during the (very brief) interval before the tick-in-progress finishes - * and the following tick begins + * misled during the (very brief) interval before the tick-in-progress + * finishes and the following tick begins */ elapsedTicks = @@ -458,10 +460,8 @@ void _timer_idle_exit(void) /* * Any elapsed ticks have been accounted for so simply set the - * programmed - * ticks to 1 since the timer has been programmed to fire on the next - * tick - * boundary. + * programmed ticks to 1 since the timer has been programmed to fire on + * the next tick boundary. */ programmed_ticks = 1; @@ -491,8 +491,7 @@ int _sys_clock_driver_init(struct device *device) /* * Initial state of HPET is unknown, so put it back in a reset-like - * state - * (i.e. set main counter to 0 and disable interrupts) + * state (i.e. set main counter to 0 and disable interrupts) */ *_HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF; @@ -588,9 +587,9 @@ int _sys_clock_driver_init(struct device *device) */ /* - * HPET timers IRQ field is 5 bits wide, and hence, can support only IRQ's - * up to 31. Some platforms, however, use IRQs greater than 31. In this - * case program leaves the IRQ fields blank. + * HPET timers IRQ field is 5 bits wide, and hence, can support only + * IRQ's up to 31. Some platforms, however, use IRQs greater than 31. In + * this case program leaves the IRQ fields blank. */ *_HPET_TIMER0_CONFIG_CAPS = @@ -609,8 +608,7 @@ int _sys_clock_driver_init(struct device *device) /* * Although the stub has already been "connected", the vector number - * still - * has to be programmed into the interrupt controller. + * still has to be programmed into the interrupt controller. */ IRQ_CONFIG(hpet, CONFIG_HPET_TIMER_IRQ, 0); diff --git a/drivers/timer/loapic_timer.c b/drivers/timer/loapic_timer.c index 28180f6c136..6ead3d32675 100644 --- a/drivers/timer/loapic_timer.c +++ b/drivers/timer/loapic_timer.c @@ -132,8 +132,8 @@ IRQ_CONNECT_STATIC(loapic, CONFIG_LOAPIC_TIMER_IRQ, CONFIG_LOAPIC_TIMER_IRQ_PRIORITY, _timer_int_handler, 0); -static uint32_t __noinit cycles_per_tick; /* computed counter 0 - initial count value */ +/* computed counter 0 initial count value */ +static uint32_t __noinit cycles_per_tick; static uint32_t accumulated_cycle_count; #if defined(TIMER_SUPPORTS_TICKLESS) @@ -596,13 +596,13 @@ int _sys_clock_driver_init(struct device *device) /* * Although the stub has already been "connected", the vector number - * still - * has to be programmed into the interrupt controller. + * still has to be programmed into the interrupt controller. */ IRQ_CONFIG(loapic, CONFIG_LOAPIC_TIMER_IRQ, 0); /* Everything has been configured. It is now safe to enable the - * interrupt */ + * interrupt + */ irq_enable(CONFIG_LOAPIC_TIMER_IRQ); return 0; diff --git a/drivers/timer/sys_clock_init.c b/drivers/timer/sys_clock_init.c index 93832c76ac5..fc857a91815 100644 --- a/drivers/timer/sys_clock_init.c +++ b/drivers/timer/sys_clock_init.c @@ -17,14 +17,15 @@ */ /* -DESCRIPTION -Initializing the timer driver is done in this module to reduce code duplication. -Although both nanokernel and microkernel systems initialize the timer driver at -the same point, the two systems differ in when the system can begin to process -system clock ticks. A nanokernel system can process system clock ticks once -the driver has initialized. However, in a microkernel system all system clock -ticks are deferred (and stored on the kernel server command stack) until the -kernel server fiber starts and begins processing any queued ticks. + * DESCRIPTION + * Initializing the timer driver is done in this module to reduce code + * duplication. Although both nanokernel and microkernel systems initialize + * the timer driver at the same point, the two systems differ in when the system + * can begin to process system clock ticks. A nanokernel system can process + * system clock ticks once the driver has initialized. However, in a + * microkernel system all system clock ticks are deferred (and stored on the + * kernel server command stack) until the kernel server fiber starts and begins + * processing any queued ticks. */ #include @@ -32,6 +33,6 @@ kernel server fiber starts and begins processing any queued ticks. #include DECLARE_DEVICE_INIT_CONFIG(sys_clock, "sys_clock", - _sys_clock_driver_init, NULL); + _sys_clock_driver_init, NULL); nano_late_init(sys_clock, NULL); diff --git a/include/arch/arc/arch.h b/include/arch/arc/arch.h index dc4d6712c2f..fc9667dfb2c 100644 --- a/include/arch/arc/arch.h +++ b/include/arch/arc/arch.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This header contains the ARC specific nanokernel interface. It is -included by the nanokernel interface architecture-abstraction header -(nanokernel/cpu.h) + * DESCRIPTION + * This header contains the ARC specific nanokernel interface. It is + * included by the nanokernel interface architecture-abstraction header + * (nanokernel/cpu.h) */ #ifndef _ARC_ARCH__H_ diff --git a/include/arch/arc/v2/aux_regs.h b/include/arch/arc/v2/aux_regs.h index 8c9ba4867be..7d25aaa234c 100644 --- a/include/arch/arc/v2/aux_regs.h +++ b/include/arch/arc/v2/aux_regs.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION - -Definitions for auxiliary registers. + * DESCRIPTION + * + * Definitions for auxiliary registers. */ #ifndef _ARC_V2_AUX_REGS__H_ diff --git a/include/arch/arc/v2/error.h b/include/arch/arc/v2/error.h index cbc282a4ee4..c6d3395d70c 100644 --- a/include/arch/arc/v2/error.h +++ b/include/arch/arc/v2/error.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARC-specific nanokernel error handling interface. Included by ARC/arch.h. + * DESCRIPTION + * ARC-specific nanokernel error handling interface. Included by ARC/arch.h. */ #ifndef _ARCH_ARC_V2_ERROR_H_ diff --git a/include/arch/arc/v2/exc.h b/include/arch/arc/v2/exc.h index dbc1220d327..ffe4a3ef79b 100644 --- a/include/arch/arc/v2/exc.h +++ b/include/arch/arc/v2/exc.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARC-specific nanokernel exception handling interface. Included by ARC/arch.h. + * DESCRIPTION + * ARC-specific nanokernel exception handling interface. Included by ARC/arch.h. */ #ifndef _ARCH_ARC_V2_EXC_H_ diff --git a/include/arch/arc/v2/ffs.h b/include/arch/arc/v2/ffs.h index 2e876221ecf..e6f763eb1b4 100644 --- a/include/arch/arc/v2/ffs.h +++ b/include/arch/arc/v2/ffs.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARC-specific nanokernel ffs interface. Included by ARC/arch.h. + * DESCRIPTION + * ARC-specific nanokernel ffs interface. Included by ARC/arch.h. */ #ifndef _ARCH_ARC_V2_FFS_H_ diff --git a/include/arch/arc/v2/misc.h b/include/arch/arc/v2/misc.h index 581d673e142..63e11c69a7e 100644 --- a/include/arch/arc/v2/misc.h +++ b/include/arch/arc/v2/misc.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h. + * DESCRIPTION + * ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h. */ #ifndef _ARCH_ARC_V2_MISC_H_ diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h index 80c749a7df7..980d23d8585 100644 --- a/include/arch/arm/arch.h +++ b/include/arch/arm/arch.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This header contains the ARM specific nanokernel interface. It is -included by the nanokernel interface architecture-abstraction header -(nanokernel/cpu.h) + * DESCRIPTION + * This header contains the ARM specific nanokernel interface. It is + * included by the nanokernel interface architecture-abstraction header + * (nanokernel/cpu.h) */ #ifndef _ARM_ARCH__H_ diff --git a/include/arch/arm/cortex_m/error.h b/include/arch/arm/cortex_m/error.h index 4a3a68fdc65..aa4d98991b5 100644 --- a/include/arch/arm/cortex_m/error.h +++ b/include/arch/arm/cortex_m/error.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARM-specific nanokernel error handling interface. Included by ARM/arch.h. + * DESCRIPTION + * ARM-specific nanokernel error handling interface. Included by ARM/arch.h. */ #ifndef _ARCH_ARM_CORTEXM_ERROR_H_ diff --git a/include/arch/arm/cortex_m/exc.h b/include/arch/arm/cortex_m/exc.h index 4b7a2350b4c..4674222574a 100644 --- a/include/arch/arm/cortex_m/exc.h +++ b/include/arch/arm/cortex_m/exc.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARM-specific nanokernel exception handling interface. Included by ARM/arch.h. + * DESCRIPTION + * ARM-specific nanokernel exception handling interface. Included by ARM/arch.h. */ #ifndef _ARCH_ARM_CORTEXM_EXC_H_ diff --git a/include/arch/arm/cortex_m/gdb_stub.h b/include/arch/arm/cortex_m/gdb_stub.h index 3dbe7516d10..baf94b52eb4 100644 --- a/include/arch/arm/cortex_m/gdb_stub.h +++ b/include/arch/arm/cortex_m/gdb_stub.h @@ -17,11 +17,11 @@ */ /* - DESCRIPTION - - Prep work done when entering exceptions consists of saving the callee-saved - registers before they get used by exception handlers, and recording the fact - that we are running in an exception. + * DESCRIPTION + * + * Prep work done when entering exceptions consists of saving the callee-saved + * registers before they get used by exception handlers, and recording the fact + * that we are running in an exception. */ #ifndef _GDB_STUB__H_ diff --git a/include/arch/arm/cortex_m/irq.h b/include/arch/arm/cortex_m/irq.h index a017b8b28d5..07151cde874 100644 --- a/include/arch/arm/cortex_m/irq.h +++ b/include/arch/arm/cortex_m/irq.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h. + * DESCRIPTION + * ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h. */ #ifndef _ARCH_ARM_CORTEXM_IRQ_H_ diff --git a/include/arch/arm/cortex_m/memory_map-m3-m4.h b/include/arch/arm/cortex_m/memory_map-m3-m4.h index b1da4a99ba6..738a69e10c0 100644 --- a/include/arch/arm/cortex_m/memory_map-m3-m4.h +++ b/include/arch/arm/cortex_m/memory_map-m3-m4.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -This module contains definitions for the memory map parts specific to the -CORTEX-M3/M4 series of processors. It is included by nanokernel/ARM/memory_map.h - + * DESCRIPTION + * This module contains definitions for the memory map parts specific to the + * CORTEX-M3/M4 series of processors. It is included by + * nanokernel/ARM/memory_map.h */ #ifndef _MEMORY_MAP_M3_M4__H_ diff --git a/include/arch/arm/cortex_m/memory_map.h b/include/arch/arm/cortex_m/memory_map.h index 692537d0c2b..62c23b58b52 100644 --- a/include/arch/arm/cortex_m/memory_map.h +++ b/include/arch/arm/cortex_m/memory_map.h @@ -17,10 +17,9 @@ */ /* -DESCRIPTION -This module contains definitions for the memory map of the CORTEX-M series of -processors. - + * DESCRIPTION + * This module contains definitions for the memory map of the CORTEX-M series of + * processors. */ #ifndef _CORTEXM_MEMORY_MAP__H_ diff --git a/include/arch/arm/cortex_m/misc.h b/include/arch/arm/cortex_m/misc.h index 6e83656cb1d..88da1811966 100644 --- a/include/arch/arm/cortex_m/misc.h +++ b/include/arch/arm/cortex_m/misc.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h. + * DESCRIPTION + * ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h. */ #ifndef _ARCH_ARM_CORTEXM_MISC_H_ diff --git a/include/arch/arm/cortex_m/nvic.h b/include/arch/arm/cortex_m/nvic.h index 8ea8cfb8433..76c6c51e42b 100644 --- a/include/arch/arm/cortex_m/nvic.h +++ b/include/arch/arm/cortex_m/nvic.h @@ -17,21 +17,21 @@ */ /* -DESCRIPTION -Provide an interface to the Nested Vectored Interrupt Controller found on -ARM Cortex-M processors. - -The API does not account for all possible usages of the NVIC, only the -functionalities needed by the kernel. - -The same effect can be achieved by directly writing in the registers of the -NVIC, with the layout available from scs.h, using the __scs.nvic data -structure (or hardcoded values), but these APIs are less error-prone, -especially for registers with multiple instances to account for potentially -240 interrupt lines. If access to a missing functionality is needed, this is -the way to implement it. - -Supports up to 240 IRQs and 256 priority levels. + * DESCRIPTION + * Provide an interface to the Nested Vectored Interrupt Controller found on + * ARM Cortex-M processors. + * + * The API does not account for all possible usages of the NVIC, only the + * functionalities needed by the kernel. + * + * The same effect can be achieved by directly writing in the registers of the + * NVIC, with the layout available from scs.h, using the __scs.nvic data + * structure (or hardcoded values), but these APIs are less error-prone, + * especially for registers with multiple instances to account for potentially + * 240 interrupt lines. If access to a missing functionality is needed, this is + * the way to implement it. + * + * Supports up to 240 IRQs and 256 priority levels. */ #ifndef _NVIC_H_ diff --git a/include/arch/arm/cortex_m/scb.h b/include/arch/arm/cortex_m/scb.h index 55863197ac9..6a70ee8b5cf 100644 --- a/include/arch/arm/cortex_m/scb.h +++ b/include/arch/arm/cortex_m/scb.h @@ -17,22 +17,23 @@ */ /* -DESCRIPTION -Provide an interface to the System Control Block found on ARM Cortex-M -processors. - -The API does not account for all possible usages of the SCB, only the -functionalities needed by the kernel. It does not contain NVIC -functionalities either: these can be found in nvic.h. MPU functionalities -are not implemented. - -The same effect can be achieved by directly writing in the registers of the -SCB, with the layout available from scs.h, using the __scs.scb data -structure (or hardcoded values), but the APIs found here are less error-prone, -especially for registers with multiple instances to account for 16 exceptions. - -If access to a missing functionality is needed, directly writing to the -registers is the way to implement it. + * DESCRIPTION + * Provide an interface to the System Control Block found on ARM Cortex-M + * processors. + * + * The API does not account for all possible usages of the SCB, only the + * functionalities needed by the kernel. It does not contain NVIC + * functionalities either: these can be found in nvic.h. MPU functionalities + * are not implemented. + * + * The same effect can be achieved by directly writing in the registers of the + * SCB, with the layout available from scs.h, using the __scs.scb data + * structure (or hardcoded values), but the APIs found here are less + * error-prone, especially for registers with multiple instances to account + * for 16 exceptions. + * + * If access to a missing functionality is needed, directly writing to the + * registers is the way to implement it. */ #ifndef _SCB__H_ diff --git a/include/arch/arm/cortex_m/scs.h b/include/arch/arm/cortex_m/scs.h index 9ddb3dad6a3..2d404e25dc2 100644 --- a/include/arch/arm/cortex_m/scs.h +++ b/include/arch/arm/cortex_m/scs.h @@ -17,41 +17,41 @@ */ /* -DESCRIPTION -Define the System Control Space for the CORTEX-M series of processors and -provide an interface for miscellaneous SCS functionalities. - -All register and bit-field names come from the - - Cortex-M3 Devices - Generic User Guide - ARM DUI 0552A (ID121610) - -and - - Cortex-M3 - Revision r2p1 - Technical Reference Manual - ARM DDI 0337I (ID072410) - -documents from ARM. - -The API does not account for all possible usages of the SCS, only the -functionalities needed by the kernel. It does not contain NVIC and -SCB functionalities either: these can be found in nvic.h and scb.h. - -MPU functionalities are not implemented. - -The same effect can be achieved by directly writing in the registers of the -SCS, using the __scs data structure (or hardcoded values), but the APIs found -here are less error-prone, especially for registers with multiple instances to -account for 16 exceptions. - -If access to a missing functionality is needed, directly writing to the -registers is the way to implement it. - -Note that the 'stir' register, even if not in the 'nvic' part of the SCB, is -still considered part of the NVIC and an API for it is provided in nvic.h. + * DESCRIPTION + * Define the System Control Space for the CORTEX-M series of processors and + * provide an interface for miscellaneous SCS functionalities. + * + * All register and bit-field names come from the + * + * Cortex-M3 Devices + * Generic User Guide + * ARM DUI 0552A (ID121610) + * + * and + * + * Cortex-M3 + * Revision r2p1 + * Technical Reference Manual + * ARM DDI 0337I (ID072410) + * + * documents from ARM. + * + * The API does not account for all possible usages of the SCS, only the + * functionalities needed by the kernel. It does not contain NVIC and + * SCB functionalities either: these can be found in nvic.h and scb.h. + * + * MPU functionalities are not implemented. + * + * The same effect can be achieved by directly writing in the registers of the + * SCS, using the __scs data structure (or hardcoded values), but the APIs found + * here are less error-prone, especially for registers with multiple instances + * to account for 16 exceptions. + * + * If access to a missing functionality is needed, directly writing to the + * registers is the way to implement it. + * + * Note that the 'stir' register, even if not in the 'nvic' part of the SCB, is + * still considered part of the NVIC and an API for it is provided in nvic.h. */ #ifndef _SCS__H_ @@ -370,12 +370,13 @@ struct __scs { union __scr scr; /* 0xd10 System Control Register */ union __ccr ccr; /* 0xd14 Configuration and Control Register */ uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers - Use ('exception number' - 4) to - get index into array */ + * Use ('exception number' - 4) to + * get index into array + */ union __shcsr shcsr; /* 0xd24 Sys Handler Control and State Reg */ union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register - */ + */ union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */ uint32_t dfsr; /* 0xd30 Debug Fault Status Register */ uint32_t mmfar; /* 0xd34 MemManage Fault Address Register */ @@ -383,7 +384,8 @@ struct __scs { uint32_t afsr; /* 0xd3C Aux Fault Status Register */ } scb; /* offset: 0xd00, size 0x040 */ - /* d40 -> d7f: processor feature ID registers (pp.778-779 in DDI0403D) + /* + * d40 -> d7f: processor feature ID registers (pp.778-779 in DDI0403D) */ uint32_t rsvd__d40_d8f[(0xd90 - 0xd40) / 4]; @@ -394,7 +396,8 @@ struct __scs { union __mpu_rnr mpu_rnr; /* 0xd98 RW Region Number Register */ union __mpu_rbar mpu_rbar; /* 0xd9c RW Region Base Addr Reg. */ union __mpu_rasr mpu_rasr; /* 0xda0 RW Region Attr and Size - Reg.*/ + * Reg. + */ union __mpu_rbar mpu_rbar_a1; /* 0xda4 RW alias of mpu_rbar */ union __mpu_rasr mpu_rasr_a1; /* 0xda8 RW alias of mpu_rasr */ union __mpu_rbar mpu_rbar_a2; /* 0xdac RW alias of mpu_rbar */ @@ -405,9 +408,8 @@ struct __scs { uint32_t rsvd__da4_eff[(0xf00 - 0xdbc) / 4]; - uint32_t - stir; /* 0xf00 WO SW Trigger IRQ Reg. (bit 0-8/IRQ 0-239 only) - */ + /* 0xf00 WO SW Trigger IRQ Reg. (bit 0-8/IRQ 0-239 only) */ + uint32_t stir; uint32_t rsvd__f04_fff[(0x1000 - 0xF04) / 4]; }; @@ -436,8 +438,8 @@ static inline int _ScsNumIrqGet(void) * From the ARM manuals: * * LDM/STM instructions increase the interrupt latency of the processor because - * they must complete before the processor can stack the current state and invoke - * the interrupt handler. + * they must complete before the processor can stack the current state and + * invoke the interrupt handler. * * @return N/A */ @@ -469,7 +471,8 @@ static inline void _ScsIntMultiCycleInstEnable(void) * * Disables write buffer use during default memory map accesses. This causes all * BusFaults to be precise BusFaults but decreases performance because any store - * to memory must complete before the processor can execute the next instruction. + * to memory must complete before the processor can execute the next + * instruction. * * @return N/A */ diff --git a/include/arch/x86/linker-common-sections.h b/include/arch/x86/linker-common-sections.h index d7d1efd7eff..049ad0dda53 100644 --- a/include/arch/x86/linker-common-sections.h +++ b/include/arch/x86/linker-common-sections.h @@ -17,33 +17,34 @@ */ /* -DESCRIPTION -This script defines the memory location of the various sections that make up -a Zephyr Kernel image. This file is used by the linker. - -This script places the various sections of the image according to what features -are enabled by the kernel's configuration options. - -For a build that does not use the execute in place (XIP) feature, the script -generates an image suitable for loading into and executing from RAM by placing -all the sections adjacent to each other. There is also no separate load -address for the DATA section which means it doesn't have to be copied into RAM. - -For builds using XIP, there is a different load memory address (LMA) and -virtual memory address (VMA) for the DATA section. In this case the DATA -section is copied into RAM at runtime. - -When building an XIP image the data section is placed into ROM. In this case, -the LMA is set to __data_rom_start so the data section is concatenated at the -end of the RODATA section. At runtime, the DATA section is copied into the RAM -region so it can be accessed with read and write permission. - -Most symbols defined in the sections below are subject to be referenced in the -Zephyr Kernel image. If a symbol is used but not defined the linker will emit an -undefined symbol error. - -Please do not change the order of the section as the nanokernel expects this -order when programming the MMU. + * DESCRIPTION + * This script defines the memory location of the various sections that make up + * a Zephyr Kernel image. This file is used by the linker. + * + * This script places the various sections of the image according to what + * features are enabled by the kernel's configuration options. + * + * For a build that does not use the execute in place (XIP) feature, the script + * generates an image suitable for loading into and executing from RAM by + * placing all the sections adjacent to each other. There is also no separate + * load address for the DATA section which means it doesn't have to be copied + * into RAM. + * + * For builds using XIP, there is a different load memory address (LMA) and + * virtual memory address (VMA) for the DATA section. In this case the DATA + * section is copied into RAM at runtime. + * + * When building an XIP image the data section is placed into ROM. In this + * case, the LMA is set to __data_rom_start so the data section is concatenated + * at the end of the RODATA section. At runtime, the DATA section is copied + * into the RAM region so it can be accessed with read and write permission. + * + * Most symbols defined in the sections below are subject to be referenced in + * the Zephyr Kernel image. If a symbol is used but not defined the linker will + * emit an undefined symbol error. + * + * Please do not change the order of the section as the nanokernel expects this + * order when programming the MMU. */ #define _LINKER diff --git a/include/arch/x86/linker-defs-arch.h b/include/arch/x86/linker-defs-arch.h index 3e1b8484a17..51e5c45405b 100644 --- a/include/arch/x86/linker-defs-arch.h +++ b/include/arch/x86/linker-defs-arch.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Commonly used macros and defines for linker script. + * DESCRIPTION + * Commonly used macros and defines for linker script. */ #ifndef _LINKERDEFSARCH_H #define _LINKERDEFSARCH_H @@ -35,14 +35,14 @@ Commonly used macros and defines for linker script. #define INTERRUPT_VECTORS_ALLOCATED KEEP(*(int_vector_alloc)) #else /* - * Save space for the real IDT to prevent symbols from shifting. Note that - * an IDT entry is 8 bytes in size. + * Save space for the real IDT to prevent symbols from shifting. Note + * that an IDT entry is 8 bytes in size. */ #define STATIC_IDT . += (8 * CONFIG_IDT_NUM_VECTORS); /* - * Save space for the real _interrupt_vectors_allocated[] array to prevent - * symbols from shifting. + * Save space for the real _interrupt_vectors_allocated[] array to + * prevent symbols from shifting. */ #define INTERRUPT_VECTORS_ALLOCATED . += ((CONFIG_IDT_NUM_VECTORS + 31) / 32); #endif diff --git a/include/arch/x86/segselect.h b/include/arch/x86/segselect.h index 0c833299232..70d63c0d247 100644 --- a/include/arch/x86/segselect.h +++ b/include/arch/x86/segselect.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header contains the IA-32 segment selector defintions. These are extracted -into their own file so they can be shared with the host tools. + * DESCRIPTION + * This header contains the IA-32 segment selector defintions. These are + * extracted into their own file so they can be shared with the host tools. */ #ifndef _SEGSELECT_H @@ -27,9 +27,9 @@ into their own file so they can be shared with the host tools. /* * Segment selector macros for the various entries in the GDT. These are - * actually byte offsets from the start of the entry table (tGdtHeader->pEntries) - * that are loaded into the appropriate CPU segment register (along with the - * appropriate T bit and privilege level bits). + * actually byte offsets from the start of the entry table + * (tGdtHeader->pEntries) that are loaded into the appropriate CPU segment + * register (along with the appropriate T bit and privilege level bits). * * When referencing a specific GDT descriptor via tGdtHeader->pEntries, use * XXX_SEG_SELECTOR/sizeof(tGdtDesc) diff --git a/include/drivers/console/ipi_console.h b/include/drivers/console/ipi_console.h index 692865bcd60..b823857906f 100644 --- a/include/drivers/console/ipi_console.h +++ b/include/drivers/console/ipi_console.h @@ -26,8 +26,10 @@ #define IPI_CONSOLE_STDOUT (1 << 0) #define IPI_CONSOLE_PRINTK (1 << 1) -/* Good way to determine these numbers other than trial-and-error? - * using printf() in the fiber seems to require a lot more stack space */ +/* + * Good way to determine these numbers other than trial-and-error? + * using printf() in the fiber seems to require a lot more stack space + */ #define IPI_CONSOLE_STACK_SIZE 512 #define IPI_CONSOLE_PRI 2 @@ -35,27 +37,35 @@ struct ipi_console_receiver_config_info { /** Name of the low-level IPI driver to bind to */ char *bind_to; - /** Stack for the receiver's fiber, which prints out messages as - * they come in. Should be sized IPI_CONSOLE_STACK_SIZE */ + /** + * Stack for the receiver's fiber, which prints out messages as + * they come in. Should be sized IPI_CONSOLE_STACK_SIZE + */ char *fiber_stack; - /** Ring buffer data area for stashing characters from the interrupt - * callback */ + /** + * Ring buffer data area for stashing characters from the interrupt + * callback + */ uint32_t *ring_buf_data; /** Size of ring_buf_data in 32-bit chunks */ unsigned int rb_size32; - /** Line buffer for incoming messages, characters accumulate here + /** + * Line buffer for incoming messages, characters accumulate here * and then are sent to printk() once full (including a trailing NULL) - * or a carriage return seen */ + * or a carriage return seen + */ char *line_buf; /** Size in bytes of the line buffer. Must be at least 2 */ unsigned int lb_size; - /** Destination for received console messages, one of - * IPI_CONSOLE_STDOUT or IPI_CONSOLE_PRINTK */ + /** + * Destination for received console messages, one of + * IPI_CONSOLE_STDOUT or IPI_CONSOLE_PRINTK + */ unsigned int flags; }; @@ -74,8 +84,10 @@ struct ipi_console_sender_config_info { /** Name of the low-level driver to bind to */ char *bind_to; - /** Source of messages to forward, hooks will be installed. - * Can be IPI_CONSOLE_STDOUT, IPI_CONSOLE_PRINTK, or both */ + /** + * Source of messages to forward, hooks will be installed. + * Can be IPI_CONSOLE_STDOUT, IPI_CONSOLE_PRINTK, or both + */ int flags; }; diff --git a/include/drivers/k20_mcg.h b/include/drivers/k20_mcg.h index 08f307a41dd..82ff58daef6 100644 --- a/include/drivers/k20_mcg.h +++ b/include/drivers/k20_mcg.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module defines the Multipurpose Clock Generator (MCG) and Oscillator (OSC) -registers for the K20 Family of microprocessors. + * DESCRIPTION + * This module defines the Multipurpose Clock Generator (MCG) and Oscillator + * (OSC) registers for the K20 Family of microprocessors. */ #ifndef _K20MCG_H_ #define _K20MCG_H_ diff --git a/include/drivers/k20_pcr.h b/include/drivers/k20_pcr.h index 93ebf51c95c..6f9eae23d50 100644 --- a/include/drivers/k20_pcr.h +++ b/include/drivers/k20_pcr.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module defines the PCR (Port/Pin Control/Configuration Registers) for the -K20 Family of microprocessors + * DESCRIPTION + * This module defines the PCR (Port/Pin Control/Configuration Registers) for + * the K20 Family of microprocessors */ #ifndef _K20PCR_H_ diff --git a/include/drivers/k20_uart.h b/include/drivers/k20_uart.h index 1b5a0d1b92e..43feea8796c 100644 --- a/include/drivers/k20_uart.h +++ b/include/drivers/k20_uart.h @@ -186,8 +186,9 @@ typedef volatile struct { uint8_t u_7816[0x20 - 0x17]; /* 0x017-0x1F UART ISO-7816 standard */ uint8_t u_cea709_1[0x32 - 0x20]; /* 0x020-0x31 UART CEA8709.1 standard */ - uint8_t z_reserv_statused038_03c[0x1000 - 0x32]; /* 0x032-0xFFF - Reserved */ + /* 0x032-0xFFF Reserved */ + uint8_t z_reserv_statused038_03c[0x1000 - 0x32]; + } K20_UART_t; /* K20 Microntroller UART module */ /** Device data structure */ diff --git a/include/drivers/k20_watchdog.h b/include/drivers/k20_watchdog.h index 9e598bfcf9f..72834960817 100644 --- a/include/drivers/k20_watchdog.h +++ b/include/drivers/k20_watchdog.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module defines Watch Dog Registers for the K20 Family of microprocessors + * DESCRIPTION + * This module defines Watch Dog Registers for the K20 Family of microprocessors */ #ifndef _K20WDOG_H_ diff --git a/include/drivers/k6x_mpu.h b/include/drivers/k6x_mpu.h index d9afaf6a49d..37fd3ae7a82 100644 --- a/include/drivers/k6x_mpu.h +++ b/include/drivers/k6x_mpu.h @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This module defines the Memory Protection Unit (MPU) Registers for the -K6x Family of microprocessors. -NOTE: Not all the registers are currently defined here - only those that are -currently used. + * DESCRIPTION + * This module defines the Memory Protection Unit (MPU) Registers for the K6x + * Family of microprocessors. + * NOTE: Not all the registers are currently defined here - only those that are + * currently used. */ #ifndef _K6xMPU_H_ diff --git a/include/drivers/k6x_pmc.h b/include/drivers/k6x_pmc.h index a1743d1eedb..3c3b4768a73 100644 --- a/include/drivers/k6x_pmc.h +++ b/include/drivers/k6x_pmc.h @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This module defines the Power Management Controller (PMC) registers for the -K6x Family of microprocessors. -NOTE: Not all the registers are currently defined here - only those that are -currently used. + * DESCRIPTION + * This module defines the Power Management Controller (PMC) registers for the + * K6x Family of microprocessors. + * NOTE: Not all the registers are currently defined here - only those that are + * currently used. */ #ifndef _K6xPMC_H_ diff --git a/include/drivers/pci/pci.h b/include/drivers/pci/pci.h index 1bdb35826c5..b4d77efaf51 100644 --- a/include/drivers/pci/pci.h +++ b/include/drivers/pci/pci.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Module declares routines of PCI bus initialization and query + * DESCRIPTION + * Module declares routines of PCI bus initialization and query */ #ifndef _PCI_H_ diff --git a/include/drivers/pci/pci_mgr.h b/include/drivers/pci/pci_mgr.h index 42b3a7253c5..94a160f8e35 100644 --- a/include/drivers/pci/pci_mgr.h +++ b/include/drivers/pci/pci_mgr.h @@ -72,30 +72,30 @@ extern "C" { #ifndef _ASMLANGUAGE /* - -PCI Address Register - -The configuration address register is a 32-bit register with the format -shown below. Bit 31 is an enable flag for determining when accesses to -the configuration data should be translated to configuration cycles. Bits -23 through 16 allow the configuration software to choose a specific PCI -bus in the system. Bits 15 through 11 select the specific device on the -PCI Bus. Bits 10 through 8 choose a specific function in a device (if the -device supports multiple functions). Bits 7 through 2 select the specific -32-bit area in the device's configuration space. - -+--------------------------------------------------------+ -| Bit 31 | Bits 30-24 | Bits 23-16 | -+------------------+------------------+------------------+ -| Enable | Reserved | Bus Number | -+--------------------------------------------------------+ - -+---------------------------------------------------------------------------+ -| Bits 15-11 | Bits 10-8 | Bits 7-2 | Bits 1-0 | -+------------------+------------------+------------------+------------------+ -| Device Number | Function Number | Register Number | 00 | -+---------------------------------------------------------------------------+ - + * + * PCI Address Register + * + * The configuration address register is a 32-bit register with the format + * shown below. Bit 31 is an enable flag for determining when accesses to the + * configuration data should be translated to configuration cycles. Bits 23 + * through 16 allow the configuration software to choose a specific PCI bus in + * the system. Bits 15 through 11 select the specific device on the PCI Bus. + * Bits 10 through 8 choose a specific function in a device (if the device + * supports multiple functions). Bits 7 through 2 select the specific 32-bit + * area in the device's configuration space. + * + * +--------------------------------------------------------+ + * | Bit 31 | Bits 30-24 | Bits 23-16 | + * +------------------+------------------+------------------+ + * | Enable | Reserved | Bus Number | + * +--------------------------------------------------------+ + * + * +---------------------------------------------------------------------------+ + * | Bits 15-11 | Bits 10-8 | Bits 7-2 | Bits 1-0 | + * +------------------+------------------+------------------+------------------+ + * | Device Number | Function Number | Register Number | 00 | + * +---------------------------------------------------------------------------+ + * */ union pci_addr_reg { @@ -123,30 +123,29 @@ union pci_addr_reg { /* - -PCI Extended Address Register - -The configuration address register is a 32-bit register with the format -shown below. Bit 31 is an enable flag for determining when accesses to -the configuration data should be translated to configuration cycles. Bits -23 through 16 allow the configuration software to choose a specific PCI -bus in the system. Bits 15 through 11 select the specific device on the -PCI Bus. Bits 10 through 8 choose a specific function in a device (if the -device supports multiple functions). Bits 7 through 2 select the specific -32-bit area in the device's configuration space. - -+--------------------------------------------------------+ -| Bit 31 | Bits 30-24 | Bits 23-16 | -+------------------+------------------+------------------+ -| Enable | Reserved | Bus Number | -+--------------------------------------------------------+ - -+---------------------------------------------------------------------------+ -| Bits 15-11 | Bits 10-8 | Bits 7-2 | Bits 1-0 | -+------------------+------------------+------------------+------------------+ -| Device Number | Function Number | Register Number | 00 | -+---------------------------------------------------------------------------+ - + * + * PCI Extended Address Register + * + * The configuration address register is a 32-bit register with the format + * shown below. Bit 31 is an enable flag for determining when accesses to the9 + * configuration data should be translated to configuration cycles. Bits 23 + * through 16 allow the configuration software to choose a specific PCI bus in + * the system. Bits 15 through 11 select the specific device on the PCI Bus. + * Bits 10 through 8 choose a specific function in a device (if the device + * supports multiple functions). Bits 7 through 2 select the specific 32-bit + * area in the device's configuration space. + * + * +--------------------------------------------------------+ + * | Bit 31 | Bits 30-24 | Bits 23-16 | + * +------------------+------------------+------------------+ + * | Enable | Reserved | Bus Number | + * +--------------------------------------------------------+ + * + * +---------------------------------------------------------------------------+ + * | Bits 15-11 | Bits 10-8 | Bits 7-2 | Bits 1-0 | + * +------------------+------------------+------------------+------------------+ + * | Device Number | Function Number | Register Number | 00 | + * +---------------------------------------------------------------------------+ */ union pcie_addr_reg { @@ -171,98 +170,96 @@ union pcie_addr_reg { }; /* - -PCI Device Structure - -The PCI Specification defines the organization of the 256-byte Configuration -Space registers and imposes a specific template for the space. The table -below shows the layout of the 256-byte Configuration space. All PCI -compliant devices must support the Vendor ID, Device ID, Command and Status, -Revision ID, Class Code and Header Type fields. Implementation of the other -registers is optional, depending upon the devices functionality. - -The PCI devices follow little ENDIAN ordering. The lower addresses contain -the least significant portions of the field. Software to manipulate this -structure must take particular care that the endian-ordering follows the PCI -devices, not the CPUs. - -Header Type 0x00: - -+-----------------------------------------------------------------------------+ -| Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | -+----------+----------------+----------------+----------------+---------------+ -| 00 | Device ID | Vendor ID | -+----------+---------------------------------+--------------------------------+ -| 04 | Status | Command | -+----------+----------------+----------------+--------------------------------+ -| 08 | Class Code | Subclass | Register IF | Revision ID | -+----------+----------------+----------------+----------------+---------------+ -| 0C | BIST | Header type | Latency Timer |Cache Line Size| -+----------+----------------+----------------+----------------+---------------+ -| 10 | Base address #0 (BAR0) | -+----------+------------------------------------------------------------------+ -| 14 | Base address #1 (BAR1) | -+----------+------------------------------------------------------------------+ -| 18 | Base address #2 (BAR2) | -+----------+------------------------------------------------------------------+ -| 1C | Base address #3 (BAR3) | -+----------+------------------------------------------------------------------+ -| 20 | Base address #4 (BAR4) | -+----------+------------------------------------------------------------------+ -| 24 | Base address #5 (BAR5) | -+----------+------------------------------------------------------------------+ -| 28 | Cardbus CIS Pointer | -+----------+---------------------------------+--------------------------------+ -| 2C | Subsystem ID | Subsystem Vendor ID | -+----------+---------------------------------+--------------------------------+ -| 30 | Expansion ROM base address | -+----------+------------------------------------------------------------------+ -| 34 | Reserved | Capability Ptr| -+----------+------------------------------------------------------------------+ -| 38 | Reserved | -+----------+----------------+----------------+----------------+---------------+ -| 3C | Max Latency | Min Grant | Interrupt PIN | Interrupt Line| -+-----------------------------------------------------------------------------+ - - -Header Type 0x01 (PCI-to-PCI bridge): - -+-----------------------------------------------------------------------------+ -| Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | -+----------+----------------+----------------+----------------+---------------+ -| 00 | Device ID | Vendor ID | -+----------+---------------------------------+--------------------------------+ -| 04 | Status | Command | -+----------+----------------+----------------+--------------------------------+ -| 08 | Class Code | Subclass | Revision ID | -+----------+----------------+----------------+----------------+---------------+ -| 0C | BIST | Header type | Latency Timer |Cache Line Size| -+----------+----------------+----------------+----------------+---------------+ -| 10 | Base address #0 (BAR0) | -+----------+------------------------------------------------------------------+ -| 14 | Base address #1 (BAR1) | -+----------+----------------+----------------+----------------+---------------+ -| 18 | Sec Latency | Subordinate Bus| Secondary Bus | Primary Bus | -+----------+----------------+----------------+----------------+---------------+ -| 1C | Secondary Status | I/O Limit | I/O Base | -+----------+---------------------------------+----------------+---------------+ -| 20 | Memory Limit | Memory Base | -+----------+---------------------------------+--------------------------------+ -| 24 | Prefetchable Memory Limit | Prefetchable Memory Base | -+----------+---------------------------------+--------------------------------+ -| 28 | Prefetchable Base Upper 32 Bits | -+----------+------------------------------------------------------------------+ -| 2C | Prefetchable Limit Upper 32 Bits | -+----------+---------------------------------+--------------------------------+ -| 30 | I/O Limit Upper 16 Bits | I/O Base Upper 16 Bits | -+----------+---------------------------------+----------------+---------------+ -| 34 | Reserved | Capability Ptr| -+----------+--------------------------------------------------+---------------+ -| 38 | Expansion ROM base address | -+----------+------------------------------------------------------------------+ -| 3C | Bridge Control | Interrupt PIN | Interrupt Line| -+-----------------------------------------------------------------------------+ - + * PCI Device Structure + * + * The PCI Specification defines the organization of the 256-byte Configuration + * Space registers and imposes a specific template for the space. The table + * below shows the layout of the 256-byte Configuration space. All PCI + * compliant devices must support the Vendor ID, Device ID, Command and Status, + * Revision ID, Class Code and Header Type fields. Implementation of the other + * registers is optional, depending upon the devices functionality. + * + * The PCI devices follow little ENDIAN ordering. The lower addresses contain + * the least significant portions of the field. Software to manipulate this + * structure must take particular care that the endian-ordering follows the PCI + * devices, not the CPUs. + * + * Header Type 0x00: + * + * +---------------------------------------------------------------------------+ + * | Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | + * +----------+---------------+----------------+----------------+--------------+ + * | 00 | Device ID | Vendor ID | + * +----------+--------------------------------+-------------------------------+ + * | 04 | Status | Command | + * +----------+---------------+----------------+-------------------------------+ + * | 08 | Class Code | Subclass | Register IF | Revision ID | + * +----------+---------------+----------------+----------------+--------------+ + * | 0C | BIST | Header type |Latency Timer |Cache Line Size| + * +----------+---------------+----------------+----------------+--------------+ + * | 10 | Base address #0 (BAR0) | + * +----------+----------------------------------------------------------------+ + * | 14 | Base address #1 (BAR1) | + * +----------+----------------------------------------------------------------+ + * | 18 | Base address #2 (BAR2) | + * +----------+----------------------------------------------------------------+ + * | 1C | Base address #3 (BAR3) | + * +----------+----------------------------------------------------------------+ + * | 20 | Base address #4 (BAR4) | + * +----------+----------------------------------------------------------------+ + * | 24 | Base address #5 (BAR5) | + * +----------+----------------------------------------------------------------+ + * | 28 | Cardbus CIS Pointer | + * +----------+--------------------------------+-------------------------------+ + * | 2C | Subsystem ID | Subsystem Vendor ID | + * +----------+--------------------------------+-------------------------------+ + * | 30 | Expansion ROM base address | + * +----------+----------------------------------------------------------------+ + * | 34 | Reserved |Capability Ptr| + * +----------+----------------------------------------------------------------+ + * | 38 | Reserved | + * +----------+---------------+----------------+----------------+--------------+ + * | 3C | Max Latency | Min Grant | Interrupt PIN |Interrupt Line| + * +---------------------------------------------------------------------------+ + * + * + * Header Type 0x01 (PCI-to-PCI bridge): + * + * +---------------------------------------------------------------------------+ + * | Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | + * +----------+----------------+----------------+---------------+--------------+ + * | 00 | Device ID | Vendor ID | + * +----------+---------------------------------+------------------------------+ + * | 04 | Status | Command | + * +----------+----------------+----------------+------------------------------+ + * | 08 | Class Code | Subclass | Revision ID | + * +----------+----------------+----------------+---------------+--------------+ + * | 0C | BIST | Header type | Latency Timer |CacheLine Size| + * +----------+----------------+----------------+---------------+--------------+ + * | 10 | Base address #0 (BAR0) | + * +----------+----------------------------------------------------------------+ + * | 14 | Base address #1 (BAR1) | + * +----------+----------------+----------------+----------------+-------------+ + * | 18 | Sec Latency | Subordinate Bus| Secondary Bus | Primary Bus | + * +----------+----------------+----------------+----------------+-------------+ + * | 1C | Secondary Status | I/O Limit | I/O Base | + * +----------+---------------------------------+----------------+-------------+ + * | 20 | Memory Limit | Memory Base | + * +----------+---------------------------------+------------------------------+ + * | 24 | Prefetchable Memory Limit | Prefetchable Memory Base | + * +----------+---------------------------------+------------------------------+ + * | 28 | Prefetchable Base Upper 32 Bits | + * +----------+----------------------------------------------------------------+ + * | 2C | Prefetchable Limit Upper 32 Bits | + * +----------+---------------------------------+------------------------------+ + * | 30 | I/O Limit Upper 16 Bits | I/O Base Upper 16 Bits | + * +----------+---------------------------------+----------------+-------------+ + * | 34 | Reserved |CapabilityPtr| + * +----------+--------------------------------------------------+-------------+ + * | 38 | Expansion ROM base address | + * +----------+----------------------------------------------------------------+ + * | 3C | Bridge Control | Interrupt PIN |InterruptLine| + * +---------------------------------------------------------------------------+ */ union pci_dev { @@ -540,20 +537,20 @@ union pci_dev { } word; struct { - uint32_t word[PCI_HEADER_WORDS]; /* array of words for the - header */ + /* array of words for the header */ + uint32_t word[PCI_HEADER_WORDS]; } words; }; /* -Generic Capability register set header: - -+-----------------------------------------------------------------------------+ -| Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | -+----------+----------------+----------------+----------------+---------------+ -| 00 | Capability specific data | Next Pointer | Cap ID | -+-----------------------------------------------------------------------------+ + * Generic Capability register set header: + * + * +---------------------------------------------------------------------------+ + * | Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | + * +----------+----------------+----------------+---------------+--------------+ + * | 00 | Capability specific data | Next Pointer | Cap ID | + * +---------------------------------------------------------------------------+ */ union pci_cap_hdr { @@ -582,95 +579,80 @@ union pcie_cap_hdr { }; /* -MSI Capability register set (32-bit): - -+-----------------------------------------------------------------------------+ -| Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | -+----------+----------------+----------------+----------------+---------------+ -| 00 | Message Control Register | Next Pointer | Cap ID | -+----------+---------------------------------+----------------+---------------+ -| 04 | Message Address Register 0 0 | -+----------+---------------------------------+--------------------------------+ -| 0C | | Message Data Register | -+-----------------------------------------------------------------------------+ - -MSI Capability register set (64-bit): - -+-----------------------------------------------------------------------------+ -| Register | Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | -+----------+----------------+----------------+----------------+---------------+ -| 00 | Message Control Register | Next Pointer | Cap ID | -+----------+---------------------------------+----------------+---------------+ -| 04 | Least-Significant 32-bits of Message Address Register 0 0 | -+----------+--------------------------------------------------+---------------+ -| 08 | Most-Significant 32-bits of Message Address Register | -+----------+---------------------------------+--------------------------------+ -| 0C | | Message Data Register | -+-----------------------------------------------------------------------------+ - + * MSI Capability register set (32-bit): + * + * +---------------------------------------------------------------------------+ + * |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | + * +--------+----------------+----------------+----------------+---------------+ + * | 00 | Message Control Register | Next Pointer | Cap ID | + * +--------+---------------------------------+----------------+---------------+ + * | 04 | Message Address Register 0 0 | + * +--------+---------------------------------+--------------------------------+ + * | 0C | | Message Data Register | + * +---------------------------------------------------------------------------+ + * + * MSI Capability register set (64-bit): + * + * +---------------------------------------------------------------------------+ + * |Register| Bits 31-24 | Bits 23-16 | Bits 15-8 | Bits 7-0 | + * +--------+----------------+----------------+----------------+---------------+ + * | 00 | Message Control Register | Next Pointer | Cap ID | + * +--------+---------------------------------+----------------+---------------+ + * | 04 | Least-Significant 32-bits of Message Address Register 0 0 | + * +--------+--------------------------------------------------+---------------+ + * | 08 | Most-Significant 32-bits of Message Address Register | + * +--------+---------------------------------+--------------------------------+ + * | 0C | | Message Data Register | + * +---------------------------------------------------------------------------+ */ struct _pci_msi_hdr { /* common MSI header */ union { struct { - /* offset 00: */ - uint32_t id : 8; /* capability ID */ - uint32_t next_ptr - : 8; /* pointer to next capability */ - uint32_t enabled - : 1; /* MSI enabled */ - uint32_t msg_req - : 3; /* requested message count */ - uint32_t msg_grant - : 3; /* granted message count */ - uint32_t is_64_bit - : 1; /* 64-bit capable */ - uint32_t reserved - : 8; /* */ + /* offset 00: */ + uint32_t id : 8; /* capability ID */ + uint32_t next_ptr : 8; /* pointer to next capability */ + uint32_t enabled : 1; /* MSI enabled */ + uint32_t msg_req : 3; /* requested message count */ + uint32_t msg_grant : 3; /* granted message count */ + uint32_t is_64_bit : 1; /* 64-bit capable */ + uint32_t reserved : 8; /* */ } msi_cap; struct { - /* offset 00: */ - uint32_t id : 8; /* capability ID */ - uint32_t next_ptr - : 8; /* pointer to next capability */ - uint32_t table_size - : 11; /* MSI-x table size */ - uint32_t reserved - : 3; /* */ - uint32_t func_mask - : 1; /* 1 for vectors masked */ - uint32_t enabled - : 1; /* MSI-x enabled */ + /* offset 00: */ + uint32_t id : 8; /* capability ID */ + uint32_t next_ptr : 8; /* pointer to next capability */ + uint32_t table_size : 11; /* MSI-x table size */ + uint32_t reserved : 3; /* */ + uint32_t func_mask : 1; /* 1 for vectors masked */ + uint32_t enabled : 1; /* MSI-x enabled */ } msix_cap; } cap; union { /* 32-bit MSI header */ struct { - /* offset 04: */ - uint32_t addr; /* message address register */ - /* offset 08: */ - uint32_t data : 16; /* message data register - */ - uint32_t spare - : 16; /* */ + /* offset 04: */ + uint32_t addr; /* message address register */ + /* offset 08 */ + uint32_t data : 16; /* message data register */ + uint32_t spare : 16; /* */ } regs32; /* 64-bit MSI header */ struct { - /* offset 04: */ - uint32_t - addr_low; /* message address register (lower) - */ - /* offset 08: */ - uint32_t addr_high; /* message address register - (upper) */ - /* offset 0C: */ - uint32_t data : 16; /* message data register - */ - uint32_t spare - : 16; /* */ + /* offset 04: */ + uint32_t addr_low; /* message address register + * (lower) + */ + /* offset 08: */ + uint32_t addr_high; /* message address register + * (upper) + */ + /* offset 0C: */ + uint32_t data : 16; /* message data register */ + uint32_t spare : 16; /* */ } regs64; } regs; }; @@ -680,10 +662,11 @@ union pci_msi_hdr { uint32_t word[4]; /* array of words for the header */ }; -extern uint32_t pci_controller_cnt; /* number of pci controllers; - * initialized to 0 until - * the controllers have been - * created */ +/* + * number of pci controllers; initialized to 0 until the controllers have been + * created + */ +extern uint32_t pci_controller_cnt; struct pci_msix_table { uint32_t msg_addr; @@ -725,7 +708,8 @@ extern void pci_config_out_long(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint32_t data /* data written to the offset */ ); @@ -733,7 +717,8 @@ extern void pci_config_out_word(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint16_t data /* data written to the offset */ ); @@ -741,7 +726,8 @@ extern void pci_config_out_byte(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint8_t data /* data written to the offset */ ); @@ -749,7 +735,8 @@ extern void pci_config_in_long(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint32_t *data /* return value address */ ); @@ -757,7 +744,8 @@ extern void pci_config_in_word(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint16_t *data /* return value address */ ); @@ -765,7 +753,8 @@ extern void pci_config_in_byte(uint32_t bus, /* bus number */ uint32_t dev, /* device number */ uint32_t func, /* function number */ uint32_t offset, /* offset into the configuration - space */ + * space + */ uint8_t *data /* return value address */ ); @@ -1143,12 +1132,8 @@ extern int pci_config_ext_cap_ptr_find( #define PCI_CFG_MASTER_ABORT 0x20 /* Signal master abort */ #define PCI_CFG_SEC_BUS_RESET 0x40 /* secondary bus reset */ #define PCI_CFG_FAST_BACK 0x80 /* FBB enabled on secondary */ -#define PCI_CFG_PRI_DIS_TO \ - 0x100 /* Primary Discard Timeout: \ - 2^10 PCI cycles */ -#define PCI_CFG_SEC_DIS_TO \ - 0x200 /* 2ndary Discard Timeout: \ - 2^10 PCI cycles */ +#define PCI_CFG_PRI_DIS_TO 0x100 /* Primary Discard Timeout: *2^10 PCI cycles */ +#define PCI_CFG_SEC_DIS_TO 0x200 /* 2ndary Discard Timeout: * 2^10 PCI cycles */ #define PCI_CFG_DIS_TIMER_STAT 0x400 /* Discard Timer status */ #define PCI_CFG_DIS_TIMER_ENABLE 0x800 /* Discard Timer enable */ diff --git a/include/drivers/rand32.h b/include/drivers/rand32.h index 3c742b12776..087b6427a76 100644 --- a/include/drivers/rand32.h +++ b/include/drivers/rand32.h @@ -17,16 +17,17 @@ */ /* -DESCRIPTION -This header file declares prototypes for the kernel's random number generator -APIs. - -Typically, a platform enables the hidden CUSTOM_RANDOM_GENERATOR configuration -option and provide its own driver that implements both sys_rand32_init() and -sys_rand32_get(). If it does not do this, then for projects that require random -numbers, the project must either implement those routines, or (for testing -purposes only) enable the TEST_RANDOM_GENERATOR configuration option. -*/ + * DESCRIPTION + * This header file declares prototypes for the kernel's random number generator + * APIs. + * + * Typically, a platform enables the hidden CUSTOM_RANDOM_GENERATOR + * configuration option and provide its own driver that implements both + * sys_rand32_init() and sys_rand32_get(). If it does not do this, then for + * projects that require random numbers, the project must either implement + * those routines, or (for testing purposes only) enable the + * TEST_RANDOM_GENERATOR configuration option. + */ #ifndef __INCrand32h #define __INCrand32h diff --git a/include/drivers/system_timer.h b/include/drivers/system_timer.h index 3e7ae151545..def8c6bbb19 100644 --- a/include/drivers/system_timer.h +++ b/include/drivers/system_timer.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION - -Declare API implemented by system timer driver and used by kernel components. + * DESCRIPTION + * + * Declare API implemented by system timer driver and used by kernel components. */ #ifndef _TIMER__H_ diff --git a/include/linker-defs.h b/include/linker-defs.h index f7c1016630a..f2681225578 100644 --- a/include/linker-defs.h +++ b/include/linker-defs.h @@ -15,13 +15,15 @@ */ /* -DESCRIPTION -Platform independent, commonly used macros and defines related to linker script. - -This file may be included by: -- Linker script files: for linker section declarations -- C files: for external declaration of address or size of linker section -- Assembly files: for external declaration of address or size of linker section + * DESCRIPTION + * Platform independent, commonly used macros and defines related to linker + * script. + * + * This file may be included by: + * - Linker script files: for linker section declarations + * - C files: for external declaration of address or size of linker section + * - Assembly files: for external declaration of address or size of linker + * section */ #ifndef _LINKERDEFS_H diff --git a/include/linker-tool-gcc.h b/include/linker-tool-gcc.h index 4c23884bacf..0b99fea941f 100644 --- a/include/linker-tool-gcc.h +++ b/include/linker-tool-gcc.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file defines the necessary macros used by the linker script for -use with the GCC linker. + * DESCRIPTION + * This header file defines the necessary macros used by the linker script for + * use with the GCC linker. */ #ifndef __LINKER_TOOL_GCC_H diff --git a/include/linker-tool.h b/include/linker-tool.h index 5792e9cfaa1..0fafcc9bb2e 100644 --- a/include/linker-tool.h +++ b/include/linker-tool.h @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This header file is used to automatically select the proper set of macro -definitions (based on the toolchain) for the linker script. + * DESCRIPTION + * This header file is used to automatically select the proper set of macro + * definitions (based on the toolchain) for the linker script. */ #ifndef __LINKER_TOOL_H diff --git a/include/microkernel/base_api.h b/include/microkernel/base_api.h index 593191f829f..6ed24b04135 100644 --- a/include/microkernel/base_api.h +++ b/include/microkernel/base_api.h @@ -177,9 +177,11 @@ struct _k_pipe_marker_list { typedef enum { BUFF_EMPTY, /* buffer is empty, disregarding the pending data Xfers - (reads) still finishing up */ + * (reads) still finishing up + */ BUFF_FULL, /* buffer is full, disregarding the pending data Xfers - (writes) still finishing up */ + * (writes) still finishing up + */ BUFF_OTHER } _K_PIPE_BUFF_STATE; diff --git a/include/misc/__assert.h b/include/misc/__assert.h index e39cc1fe8fc..acd6f199eee 100644 --- a/include/misc/__assert.h +++ b/include/misc/__assert.h @@ -17,52 +17,55 @@ */ /* -DESCRIPTION - -The __ASSERT() macro can be used inside kernel code. - -Assertions are enabled by setting the __ASSERT_ON symbol to a non-zero value. -There are two ways to do this: - a) Use the ASSERT and ASSERT_LEVEL kconfig options. - b) Add "CFLAGS += -D__ASSERT_ON=" at the end of a project's Makefile. -The Makefile method takes precedence over the kconfig option if both are used. - -Specifying an assertion level of 1 causes the compiler to issue warnings that -the kernel contains debug-type __ASSERT() statements; this reminder is issued -since assertion code is not normally present in a final product. Specifying -assertion level 2 suppresses these warnings. - -The __ASSERT_EVAL() macro can also be used inside kernel code. - -It makes use of the __ASSERT() macro, but has some extra flexibility. It -allows the developer to specify different actions depending whether the -__ASSERT() macro is enabled or not. This can be particularly useful to -prevent the compiler from generating comments (errors, warnings or remarks) -about variables that are only used with __ASSERT() being assigned a value, but -otherwise unused when the __ASSERT() macro is disabled. - -Consider the following example: - - int x; - - x = foo (); - __ASSERT (x != 0, "foo() returned zero!"); - -If __ASSERT() is disabled, then is assigned a value, but never used. -This type of situation can be resolved using the __ASSERT_EVAL() macro. - - __ASSERT_EVAL ((void) foo(), - int x = foo(), - x != 0, - "foo() returned zero!"); - -The first parameter tells __ASSERT_EVAL() what to do if __ASSERT() is disabled. -The second parameter tells __ASSERT_EVAL() what to do if __ASSERT() is enabled. -The third and fourth parameters are the parameters it passes to __ASSERT(). - -The __ASSERT_NO_MSG() macro can be used to perform an assertion that reports -the failed test and its location, but lacks additional debugging information -provided to assist the user in diagnosing the problem; its use is discouraged. + * DESCRIPTION + * + * The __ASSERT() macro can be used inside kernel code. + * + * Assertions are enabled by setting the __ASSERT_ON symbol to a non-zero value. + * There are two ways to do this: + * a) Use the ASSERT and ASSERT_LEVEL kconfig options + * b) Add "CFLAGS += -D__ASSERT_ON=" at the end of a project's Makefile + * The Makefile method takes precedence over the kconfig option if both are + * used. + * + * Specifying an assertion level of 1 causes the compiler to issue warnings that + * the kernel contains debug-type __ASSERT() statements; this reminder is issued + * since assertion code is not normally present in a final product. Specifying + * assertion level 2 suppresses these warnings. + * + * The __ASSERT_EVAL() macro can also be used inside kernel code. + * + * It makes use of the __ASSERT() macro, but has some extra flexibility. It + * allows the developer to specify different actions depending whether the + * __ASSERT() macro is enabled or not. This can be particularly useful to + * prevent the compiler from generating comments (errors, warnings or remarks) + * about variables that are only used with __ASSERT() being assigned a value, + * but otherwise unused when the __ASSERT() macro is disabled. + * + * Consider the following example: + * + * int x; + * + * x = foo (); + * __ASSERT (x != 0, "foo() returned zero!"); + * + * If __ASSERT() is disabled, then is assigned a value, but never used. + * This type of situation can be resolved using the __ASSERT_EVAL() macro. + * + * __ASSERT_EVAL ((void) foo(), + * int x = foo(), + * x != 0, + * "foo() returned zero!"); + * + * The first parameter tells __ASSERT_EVAL() what to do if __ASSERT() is + * disabled. The second parameter tells __ASSERT_EVAL() what to do if + * __ASSERT() is enabled. The third and fourth parameters are the parameters + * it passes to __ASSERT(). + * + * The __ASSERT_NO_MSG() macro can be used to perform an assertion that reports + * the failed test and its location, but lacks additional debugging information + * provided to assist the user in diagnosing the problem; its use is + * discouraged. */ #ifndef ___ASSERT__H_ diff --git a/include/misc/dlist.h b/include/misc/dlist.h index ea86d19801d..2d65c5e479a 100644 --- a/include/misc/dlist.h +++ b/include/misc/dlist.h @@ -17,12 +17,12 @@ */ /* -DESCRIPTION -Doubly-linked list implementation. - -The lists are expected to be initialized such that both the head and tail -pointers point to the list itself. Initializing the lists in such a fashion -simplifies the adding and removing of nodes to/from the list. + * DESCRIPTION + * Doubly-linked list implementation. + * + * The lists are expected to be initialized such that both the head and tail + * pointers point to the list itself. Initializing the lists in such a fashion + * simplifies the adding and removing of nodes to/from the list. */ #ifndef _misc_dlist__h_ diff --git a/include/misc/lists_c.h b/include/misc/lists_c.h index 8d5c9e811c4..ddf11c205e6 100644 --- a/include/misc/lists_c.h +++ b/include/misc/lists_c.h @@ -24,8 +24,8 @@ extern "C" { #endif /** -Example code from list insertion etc - *******************************************************************************/ + * Example code from list insertion etc + ******************************************************************************/ #include diff --git a/include/misc/ring_buffer.h b/include/misc/ring_buffer.h index c0cc2a6ee7c..8c17ddad4af 100644 --- a/include/misc/ring_buffer.h +++ b/include/misc/ring_buffer.h @@ -33,7 +33,8 @@ struct ring_buf { uint32_t head; /**< Index in buf for the head element */ uint32_t tail; /**< Index in buf for the tail element */ uint32_t dropped_put_count; /**< Running tally of the number of failed - * put attempts */ + * put attempts + */ uint32_t size; /**< Size of buf in 32-bit chunks */ uint32_t *buf; /**< Memory region for stored entries */ uint32_t mask; /**< Modulo mask if size is a power of 2 */ @@ -46,7 +47,8 @@ struct ring_buf { * will not need to use expensive modulo operations. * * @param name File-scoped name of the ring buffer to declare - * @param pow Create a buffer of 2^pow 32-bit elements */ + * @param pow Create a buffer of 2^pow 32-bit elements + */ #define SYS_RING_BUF_DECLARE_POW2(name, pow) \ static uint32_t _ring_buffer_data_##name[1 << (pow)]; \ struct ring_buf name = { \ @@ -62,7 +64,8 @@ struct ring_buf { * but will use more expensive modulo operations to maintain itself. * * @param name File-scoped name of the ring buffer to declare - * @param size32 Size of buffer in 32-bit elements */ + * @param size32 Size of buffer in 32-bit elements + */ #define SYS_RING_BUF_DECLARE_SIZE(name, size32) \ static uint32_t _ring_buffer_data_##name[size32]; \ struct ring_buf name = { \ @@ -100,7 +103,8 @@ static inline void sys_ring_buf_init(struct ring_buf *buf, uint32_t size, /** * @brief Determine if a ring buffer is empty * - * @return nonzero if the buffer is empty */ + * @return nonzero if the buffer is empty + */ static inline int sys_ring_buf_is_empty(struct ring_buf *buf) { return (buf->head == buf->tail); diff --git a/include/misc/util.h b/include/misc/util.h index 8e34f94765f..d147c50b34e 100644 --- a/include/misc/util.h +++ b/include/misc/util.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Misc utilities usable by nanokernel, microkernel, and application code. + * DESCRIPTION + * Misc utilities usable by nanokernel, microkernel, and application code. */ #ifndef _UTIL__H_ @@ -31,7 +31,8 @@ extern "C" { #ifndef _ASMLANGUAGE /* Helper to pass a int as a pointer or vice-versa. - * Those are available for 32 bits architectures: */ + * Those are available for 32 bits architectures: + */ #define POINTER_TO_UINT(x) ((uint32_t) (x)) #define UINT_TO_POINTER(x) ((void *) (x)) #define POINTER_TO_INT(x) ((int32_t) (x)) diff --git a/include/net/net_buf.h b/include/net/net_buf.h index 183cc8d4a89..26c13c6c361 100644 --- a/include/net/net_buf.h +++ b/include/net/net_buf.h @@ -1,8 +1,7 @@ /** @file - @brief Network buffer API - - Network data is passed between application and IP stack via - a net_buf struct. + * @brief Network buffer API + * + * Network data is passed between application and IP stack via a net_buf struct. */ /* diff --git a/include/net/net_core.h b/include/net/net_core.h index 970f41034da..d19d09652f4 100644 --- a/include/net/net_core.h +++ b/include/net/net_core.h @@ -1,7 +1,7 @@ /** @file - @brief Network core definitions - - Definitions for networking support. + * @brief Network core definitions + * + * Definitions for networking support. */ /* diff --git a/include/net/net_ip.h b/include/net/net_ip.h index a1819b0294c..d20353f7d34 100644 --- a/include/net/net_ip.h +++ b/include/net/net_ip.h @@ -1,7 +1,7 @@ /** @file - @brief IPv6 and IPv4 definitions - - Generic IPv6 and IPv4 address definitions. + * @brief IPv6 and IPv4 definitions + * + * Generic IPv6 and IPv4 address definitions. */ /* diff --git a/include/net/net_socket.h b/include/net/net_socket.h index 7a6f5ac50d4..fb44d37ec8a 100644 --- a/include/net/net_socket.h +++ b/include/net/net_socket.h @@ -1,8 +1,8 @@ /** @file - @brief Simple socket API - - Simple socket API for applications to connection establishment and - disconnection. + * @brief Simple socket API + * + * Simple socket API for applications to connection establishment and + * disconnection. */ /* diff --git a/include/net/tinydtls.h b/include/net/tinydtls.h index a1e5ea190a6..9dfb8a9405a 100644 --- a/include/net/tinydtls.h +++ b/include/net/tinydtls.h @@ -1,7 +1,7 @@ /** @file - @brief tinyDTLS API - - API providing DTLS functionality. + * @brief tinyDTLS API + * + * API providing DTLS functionality. */ /* diff --git a/include/sections.h b/include/sections.h index a1995f12a38..d98f15b1c0c 100644 --- a/include/sections.h +++ b/include/sections.h @@ -17,8 +17,9 @@ */ /* - DESCRIPTION - Linker Section declarations used by linker script, C files and Assembly files. + * DESCRIPTION + * Linker Section declarations used by linker script, C files and Assembly + * files. */ #ifndef _SECTIONS_H diff --git a/include/sw_isr_table.h b/include/sw_isr_table.h index 77efa58467e..793c26505fa 100644 --- a/include/sw_isr_table.h +++ b/include/sw_isr_table.h @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -Data types for a software-managed ISR table, with a parameter per-ISR. + * DESCRIPTION + * Data types for a software-managed ISR table, with a parameter per-ISR. */ #ifndef _SW_ISR_TABLE__H_ diff --git a/include/sys_clock.h b/include/sys_clock.h index aada8d77031..2bf6eabda48 100644 --- a/include/sys_clock.h +++ b/include/sys_clock.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION - -Declare variables used by both system timer device driver and kernel components -that use timer functionality. + * DESCRIPTION + * + * Declare variables used by both system timer device driver and kernel + * components that use timer functionality. */ #ifndef _SYS_CLOCK__H_ diff --git a/include/toolchain.h b/include/toolchain.h index 46812a289ed..2dad077da1f 100644 --- a/include/toolchain.h +++ b/include/toolchain.h @@ -17,11 +17,11 @@ */ /* -DESCRIPTION -This file contains various macros to abstract compiler capabilities that -utilize toolchain specific attributes and/or pragmas. - -\NOMANUAL + * DESCRIPTION + * This file contains various macros to abstract compiler capabilities that + * utilize toolchain specific attributes and/or pragmas. + * + * \NOMANUAL */ #ifndef _TOOLCHAIN_H diff --git a/include/toolchain/common.h b/include/toolchain/common.h index 2530c80e3a8..38fda6b9361 100644 --- a/include/toolchain/common.h +++ b/include/toolchain/common.h @@ -17,10 +17,10 @@ */ /* -DESCRIPTION -Macros to abstract compiler capabilities (common to all toolchains). - -\NOMANUAL + * DESCRIPTION + * Macros to abstract compiler capabilities (common to all toolchains). + * + * \NOMANUAL */ /* diff --git a/include/toolchain/gcc.h b/include/toolchain/gcc.h index 191594ccc31..ad0a39c6a97 100644 --- a/include/toolchain/gcc.h +++ b/include/toolchain/gcc.h @@ -17,10 +17,10 @@ */ /* - DESCRIPTION - Macros to abstract compiler capabilities for GCC toolchain. - - \NOMANUAL + * DESCRIPTION + * Macros to abstract compiler capabilities for GCC toolchain. + * + * \NOMANUAL */ #include diff --git a/kernel/microkernel/include/micro_private_types.h b/kernel/microkernel/include/micro_private_types.h index 2354e0b3dcc..3e492673ab2 100644 --- a/kernel/microkernel/include/micro_private_types.h +++ b/kernel/microkernel/include/micro_private_types.h @@ -185,8 +185,7 @@ struct _pipe_req_arg { struct _pipe_xfer_req_arg { struct req_info req_info; - void *data_ptr; /* if NULL, data is embedded in - cmd packet */ + void *data_ptr; /* if NULL, data is embedded in cmd packet */ int total_size; /* total size of data/free space */ int xferred_size; /* size of data ALREADY Xferred */ PIPE_REQUEST_STATUS status; /* status of processing of request */ @@ -206,11 +205,14 @@ struct _pipe_xfer_ack_arg { struct _k_pipe_struct *pipe_ptr; XFER_TYPE xfer_type; /* W2B, B2R or W2R */ struct k_args *writer_ptr; /* if there's a writer involved, - this is the link to it */ + * this is the link to it + */ struct k_args *reader_ptr; /* if there's a reader involved, - this is the link to it */ - int id; /* if it is a Xfer to/from a buffer, - this is the registered Xfer's ID */ + * this is the link to it + */ + int id; /* if it is a Xfer to/from a buffer, this is the registered + * Xfer's ID + */ int size; /* amount of data Xferred */ }; diff --git a/kernel/microkernel/k_event.c b/kernel/microkernel/k_event.c index 6d597bfd45d..54f9519c599 100644 --- a/kernel/microkernel/k_event.c +++ b/kernel/microkernel/k_event.c @@ -112,9 +112,8 @@ void _k_event_test(struct k_args *A) } #endif } else { - A->Time.rcode = RC_FAIL; /* already a - waiter - present */ + /* already a waiter present */ + A->Time.rcode = RC_FAIL; } } else { /* Caller will not wait for the event */ diff --git a/kernel/microkernel/k_idle.c b/kernel/microkernel/k_idle.c index a2869c95158..be01adab248 100644 --- a/kernel/microkernel/k_idle.c +++ b/kernel/microkernel/k_idle.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -Microkernel idle logic. Different forms of idling are performed by the idle -task, depending on how the kernel is configured. + * DESCRIPTION + * Microkernel idle logic. Different forms of idling are performed by the idle + * task, depending on how the kernel is configured. */ #include @@ -369,9 +369,10 @@ static void _power_save(void) _sys_power_save_idle(_get_next_timer_expiry()); #else /* - * nano_cpu_idle() is invoked here directly only if APM is - * disabled. Otherwise the microkernel decides either to invoke - * it or to implement advanced idle functionality + * nano_cpu_idle() is invoked here directly only if APM + * is disabled. Otherwise the microkernel decides + * either to invoke it or to implement advanced idle + * functionality */ nano_cpu_idle(); @@ -420,8 +421,8 @@ int _k_kernel_idle(void) } /* - * Code analyzers may complain that _k_kernel_idle() uses an infinite loop - * unless we indicate that this is intentional + * Code analyzers may complain that _k_kernel_idle() uses an infinite + * loop unless we indicate that this is intentional */ CODE_UNREACHABLE; diff --git a/kernel/microkernel/k_memory_pool.c b/kernel/microkernel/k_memory_pool.c index 25e85787829..84c6d503961 100644 --- a/kernel/microkernel/k_memory_pool.c +++ b/kernel/microkernel/k_memory_pool.c @@ -332,7 +332,8 @@ static char *get_block_recusive(struct pool_struct *P, int index, int startindex defrag(P, P->nr_of_frags - 1, /* start from the smallest blocks */ startindex); /* but only until the requested blocksize - (fragmentation level) !! */ + * (fragmentation level) !! + */ found = search_block_on_frag_level(&(fr_table[index]), &i); if (found != NULL) { @@ -344,8 +345,9 @@ static char *get_block_recusive(struct pool_struct *P, int index, int startindex /* end of list and i is index of first empty entry in blocktable */ { + /* get a block of one size larger */ larger_block = get_block_recusive( - P, index - 1, startindex); /* get a block of one size larger */ + P, index - 1, startindex); } if (larger_block != NULL) { @@ -366,7 +368,8 @@ static char *get_block_recusive(struct pool_struct *P, int index, int startindex defrag(P, P->nr_of_frags - 1, /* start from the smallest blocks */ startindex); /* but only until the requested blocksize - (fragmentation level) !! */ + * (fragmentation level) !! + */ found = search_block_on_frag_level(&(fr_table[index]), &i); if (found != NULL) { @@ -398,7 +401,8 @@ void _k_block_waiters_get(struct k_args *A) int start_size, offset; curr_task = P->waiters; - prev_task = (struct k_args *)&(P->waiters); /* forw is first field in struct */ + /* forw is first field in struct */ + prev_task = (struct k_args *)&(P->waiters); /* loop all waiters */ while (curr_task != NULL) { diff --git a/kernel/microkernel/k_move_data.c b/kernel/microkernel/k_move_data.c index 93a52c559eb..1a45125cab2 100644 --- a/kernel/microkernel/k_move_data.c +++ b/kernel/microkernel/k_move_data.c @@ -73,21 +73,19 @@ void _k_movedata_request(struct k_args *Req) SIZEOFUNIT_TO_OCTET(1))); /* must be a multiple of size_t */ __ASSERT_NO_MSG(!(ReqArgs->action & MVDACT_INVALID)); - /* If no data is to be transferred, just execute the continuation - packet, - if any, and get out: + /* + * If no data is to be transferred, just execute the continuation + * packet, if any, and get out: */ if (0 == ReqArgs->total_size) { if (ReqArgs->action & MVDACT_SNDACK) + /* Send ack continuation */ mvdreq_docont( - ReqArgs->extra.setup.continuation_send); /* Send ack - continuation - */ + ReqArgs->extra.setup.continuation_send); if (ReqArgs->action & MVDACT_RCVACK) + /* Recv ack continuation */ mvdreq_docont( - ReqArgs->extra.setup.continuation_receive); /* Recv ack - continuation - */ + ReqArgs->extra.setup.continuation_receive); return; } diff --git a/kernel/microkernel/k_mutex.c b/kernel/microkernel/k_mutex.c index 9baf5ed9059..107be0ed9ad 100644 --- a/kernel/microkernel/k_mutex.c +++ b/kernel/microkernel/k_mutex.c @@ -153,7 +153,8 @@ void _k_mutex_lock_reply_timeout(struct k_args *A) * @return N/A */ void _k_mutex_lock_request(struct k_args *A /* pointer to mutex lock - request arguments */ + * request arguments + */ ) { struct _k_mutex_struct *Mutex; /* pointer to internal mutex structure */ @@ -174,9 +175,9 @@ void _k_mutex_lock_request(struct k_args *A /* pointer to mutex lock Mutex->owner = A->args.l1.task; /* - * Assign the current owner's priority from the priority found in the - * current task's task object: the priority stored there may be more - * recent than the one stored in struct k_args. + * Assign the current owner's priority from the priority found + * in the current task's task object: the priority stored there + * may be more recent than the one stored in struct k_args. */ Mutex->current_owner_priority = _k_current_task->priority; @@ -203,8 +204,10 @@ void _k_mutex_lock_request(struct k_args *A /* pointer to mutex lock #endif if (likely(A->Time.ticks != TICKS_NONE)) { - /* A non-zero timeout was specified. */ - /* ensure the priority saved in the request is up to date */ + /* + * A non-zero timeout was specified. Ensure the + * priority saved in the request is up to date + */ A->Ctxt.task = _k_current_task; A->priority = _k_current_task->priority; _k_state_bit_set(_k_current_task, TF_LOCK); @@ -346,8 +349,9 @@ void _k_mutex_unlock(struct k_args *A) #ifdef CONFIG_SYS_CLOCK_EXISTS if (X->Time.timer) { /* - * Trigger a call to _k_mutex_lock_reply()--it will - * send a reply with a return code of RC_OK. + * Trigger a call to _k_mutex_lock_reply()--it + * will send a reply with a return code of + * RC_OK. */ _k_timeout_cancel(X); X->Comm = _K_SVC_MUTEX_LOCK_REPLY; @@ -388,5 +392,3 @@ void _task_mutex_unlock(kmutex_t mutex) A.args.l1.task = _k_current_task->id; KERNEL_ENTRY(&A); } - - diff --git a/kernel/microkernel/k_nop.c b/kernel/microkernel/k_nop.c index 828535be19a..e748deadadf 100644 --- a/kernel/microkernel/k_nop.c +++ b/kernel/microkernel/k_nop.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION -This module provides a "do nothing" kernel service. - -This service is primarily used by other kernel services that need a way to -resume the execution of a kernel request that could not be completed in a -single invocation of the _k_server fiber. However, it can also be used by -a task to measure the overhead involved in issuing a kernel service request. + * DESCRIPTION + * This module provides a "do nothing" kernel service. + * + * This service is primarily used by other kernel services that need a way to + * resume the execution of a kernel request that could not be completed in a + * single invocation of the _k_server fiber. However, it can also be used by + * a task to measure the overhead involved in issuing a kernel service request. */ #include diff --git a/kernel/microkernel/k_pipe.c b/kernel/microkernel/k_pipe.c index c76c1838874..1e6fd79eeae 100644 --- a/kernel/microkernel/k_pipe.c +++ b/kernel/microkernel/k_pipe.c @@ -62,10 +62,12 @@ int _task_pipe_get(kpipe_t Id, void *pBuffer, { struct k_args A; - /* some users do not check the FUNCTION return value, - but immediately use iNbrBytesRead; make sure it always - has a good value, even when we return failure immediately - (see below) */ + /* + * some users do not check the FUNCTION return value, + * but immediately use iNbrBytesRead; make sure it always + * has a good value, even when we return failure immediately + * (see below) + */ *piNbrBytesRead = 0; @@ -73,8 +75,10 @@ int _task_pipe_get(kpipe_t Id, void *pBuffer, return RC_ALIGNMENT; } if (unlikely(0 == iNbrBytesToRead)) { - /* not allowed because enlisted requests with zero size - will hang in _k_pipe_process() */ + /* + * not allowed because enlisted requests with zero size + * will hang in _k_pipe_process() + */ return RC_FAIL; } if (unlikely(_0_TO_N == Option && TICKS_NONE != TimeOut)) { @@ -112,10 +116,12 @@ int _task_pipe_put(kpipe_t Id, void *pBuffer, { struct k_args A; - /* some users do not check the FUNCTION return value, - but immediately use iNbrBytesWritten; make sure it always - has a good value, even when we return failure immediately - (see below) */ + /* + * some users do not check the FUNCTION return value, + * but immediately use iNbrBytesWritten; make sure it always + * has a good value, even when we return failure immediately + * (see below) + */ *piNbrBytesWritten = 0; @@ -123,8 +129,10 @@ int _task_pipe_put(kpipe_t Id, void *pBuffer, return RC_ALIGNMENT; } if (unlikely(0 == iNbrBytesToWrite)) { - /* not allowed because enlisted requests with zero size - will hang in _k_pipe_process() */ + /* + * not allowed because enlisted requests with zero size + * will hang in _k_pipe_process() + */ return RC_FAIL; } if (unlikely(_0_TO_N == Option && TICKS_NONE != TimeOut)) { @@ -169,8 +177,10 @@ int _task_pipe_block_put(kpipe_t Id, struct k_block Block, return RC_ALIGNMENT; } if (unlikely(0 == iSize2Xfer)) { - /* not allowed because enlisted requests with zero size - will hang in _k_pipe_process() */ + /* + * not allowed because enlisted requests with zero size + * will hang in _k_pipe_process() + */ return RC_FAIL; } diff --git a/kernel/microkernel/k_pipe_buffer.c b/kernel/microkernel/k_pipe_buffer.c index 860a43be26a..4ca05d0ca8c 100644 --- a/kernel/microkernel/k_pipe_buffer.c +++ b/kernel/microkernel/k_pipe_buffer.c @@ -18,8 +18,8 @@ /* Implementation remarks: -- when using a floating end pointer: do not use pipe_desc->iBuffsize for - (pipe_desc->end_ptr - pipe_desc->begin_ptr) + * - when using a floating end pointer: do not use pipe_desc->iBuffsize for + * (pipe_desc->end_ptr - pipe_desc->begin_ptr) */ #include @@ -31,21 +31,17 @@ #define STORE_NBR_MARKERS /* NOTE: the number of pending write and read Xfers is always stored, - as it is required for the pipes to function properly. It is stored in the - pipe descriptor fields num_pending_writes and num_pending_reads. - - In the Writer and Reader MarkersList, the number of markers (==nbr. of - unreleased Xfers) - is monitored as well. They actually equal num_pending_writes and - num_pending_reads. - Their existence depends on STORE_NBR_MARKERS. A reason to have them - additionally is that - some extra consistency checking is performed in the markers manipulation - functionality - itself. - Drawback: double storage of nbr. of pending write Xfers (but for test - purposes this is - acceptable I think) + * as it is required for the pipes to function properly. It is stored in the + * pipe descriptor fields num_pending_writes and num_pending_reads. + * + * In the Writer and Reader MarkersList, the number of markers (==nbr. of + * unreleased Xfers) is monitored as well. They actually equal + * num_pending_writes and num_pending_reads. + * Their existence depends on STORE_NBR_MARKERS. A reason to have them + * additionally is that some extra consistency checking is performed in the + * markers manipulation functionality itself. + * Drawback: double storage of nbr. of pending write Xfers (but for test + * purposes this is acceptable I think) */ #define CHECK_BUFFER_POINTER(data_ptr) \ @@ -206,28 +202,29 @@ static void MarkersClear(struct _k_pipe_marker_list *pMarkerList) /**/ /* note on setting/clearing markers/guards: - - If there is at least one marker, there is a guard and equals one of the - markers; if there are no markers (*), there is no guard. - Consequently, if a marker is add when there were none, the guard will equal - it. If additional markers are add, the guard will not change. - However, if a marker is deleted: - if it equals the guard a new guard must be selected (**) - if not, guard doesn't change - - (*) we need to housekeep how much markers there are or we can inspect the - guard - (**) for this, the complete markers table needs to be investigated + * + * If there is at least one marker, there is a guard and equals one of the + * markers; if there are no markers (*), there is no guard. + * Consequently, if a marker is add when there were none, the guard will equal + * it. If additional markers are add, the guard will not change. + * However, if a marker is deleted: + * if it equals the guard a new guard must be selected (**) + * if not, guard doesn't change + * + * (*) we need to housekeep how much markers there are or we can inspect the + * guard + * (**) for this, the complete markers table needs to be investigated */ /**/ -/* This function will see if one or more 'areas' in the buffer - can be made available (either for writing xor reading). - Note: such a series of areas starts from the beginning. +/* + * This function will see if one or more 'areas' in the buffer can be made + * available (either for writing xor reading). + * Note: such a series of areas starts from the beginning. */ static int ScanMarkers(struct _k_pipe_marker_list *pMarkerList, - int *piSizeBWA, int *piSizeAWA, int *piNbrPendingXfers) + int *piSizeBWA, int *piSizeAWA, int *piNbrPendingXfers) { struct _k_pipe_marker *pM; bool bMarkersAreNowAWA; @@ -244,7 +241,8 @@ static int ScanMarkers(struct _k_pipe_marker_list *pMarkerList, __ASSERT_NO_MSG(index == pMarkerList->first_marker); if (index == pMarkerList->post_wrap_around_marker) { - bMarkersAreNowAWA = true; /* from now on, everything is AWA */ + /* from now on, everything is AWA */ + bMarkersAreNowAWA = true; } pM = &(pMarkerList->markers[index]); @@ -333,7 +331,8 @@ int CalcFreeSpace(struct _k_pipe_desc *desc, int *free_space_count_ptr, } else { /* * if buffer_state==BUFF_EMPTY but we have a WriteGuard, - * we still need to calculate it as a normal [Start,Stop] interval + * we still need to calculate it as a normal [Start,Stop] + * interval */ if (BUFF_EMPTY == desc->buffer_state) { @@ -345,8 +344,8 @@ int CalcFreeSpace(struct _k_pipe_desc *desc, int *free_space_count_ptr, } /* - * on the other hand, if buffer_state is full, we do not need a special flow; - * it will be correct as (pStop - pStart) equals 0 + * on the other hand, if buffer_state is full, we do not need a special + * flow; it will be correct as (pStop - pStart) equals 0 */ if (pStop >= pStart) { @@ -416,8 +415,8 @@ int CalcAvailData(struct _k_pipe_desc *desc, int *available_data_count_ptr, } /* - * on the other hand, if buffer_state is empty, we do not need a special flow; - * it will be correct as (pStop - pStart) equals 0 + * on the other hand, if buffer_state is empty, we do not need a + * special flow; it will be correct as (pStop - pStart) equals 0 */ if (pStop >= pStart) { @@ -690,7 +689,7 @@ void BuffDeQA_End(struct _k_pipe_desc *desc, int iTransferID, */ static bool AreasCheck4Intrusion(unsigned char *pBegin1, int iSize1, - unsigned char *pBegin2, int iSize2) + unsigned char *pBegin2, int iSize2) { unsigned char *pEnd1; unsigned char *pEnd2; @@ -709,8 +708,10 @@ static bool AreasCheck4Intrusion(unsigned char *pBegin1, int iSize1, /* intrusion!! */ return true; } else { - /* pBegin2 lies outside and to the right of the first area, - intrusion is impossible */ + /* + * pBegin2 lies outside and to the right of the first + * area, intrusion is impossible + */ return false; } } else { @@ -721,7 +722,8 @@ static bool AreasCheck4Intrusion(unsigned char *pBegin1, int iSize1, return true; } else { /* pEnd2 lies outside and to the left of the first area, - intrusion is impossible */ + * intrusion is impossible + */ return false; } } diff --git a/kernel/microkernel/k_pipe_get.c b/kernel/microkernel/k_pipe_get.c index 1deff996cc7..3cdee292943 100644 --- a/kernel/microkernel/k_pipe_get.c +++ b/kernel/microkernel/k_pipe_get.c @@ -44,8 +44,8 @@ void _k_pipe_get_request(struct k_args *RequestOrig) mycopypacket(&Request, RequestOrig); /* Now, we need a new packet for processing of the request; - the Request package is too small b/c of space lost due to possible - embedded local data + * the Request package is too small b/c of space lost due to possible + * embedded local data */ mycopypacket(&RequestProc, Request); @@ -151,8 +151,8 @@ void _k_pipe_get_request(struct k_args *RequestOrig) } } else { /* call is non-blocking; - Check if we don't have to queue it b/c it could not - be processed at once + * Check if we don't have to queue it b/c it could not + * be processed at once */ RequestProc->Time.timer = NULL; diff --git a/kernel/microkernel/k_pipe_put.c b/kernel/microkernel/k_pipe_put.c index 5ed003ff1c3..62ee20992e9 100644 --- a/kernel/microkernel/k_pipe_put.c +++ b/kernel/microkernel/k_pipe_put.c @@ -56,8 +56,8 @@ void _k_pipe_put_request(struct k_args *RequestOrig) mycopypacket(&Request, RequestOrig); /* Now, we need a new packet for processing of the request; the - Request package is too small b/c of space lost due to possible - embedded local data + * Request package is too small b/c of space lost due to possible + * embedded local data */ mycopypacket(&RequestProc, Request); @@ -130,8 +130,10 @@ void _k_pipe_put_request(struct k_args *RequestOrig) /* check if request was processed */ if (TERM_XXX & RequestProc->args.pipe_xfer_req.status) { - RequestProc->Time.timer = NULL; /* not really required */ - return; /* not listed anymore --> completely processed */ + /* not really required */ + RequestProc->Time.timer = NULL; + /* not listed anymore --> completely processed */ + return; } } while (0); @@ -146,8 +148,8 @@ void _k_pipe_put_request(struct k_args *RequestOrig) INSERT_ELM(pipe_ptr->writers, RequestProc); /* * NOTE: It is both faster and simpler to blindly assign the - * PIPE_PUT_TIMEOUT microkernel command to the packet even though it - * is only useful to the finite timeout case. + * PIPE_PUT_TIMEOUT microkernel command to the packet even + * though it is only useful to the finite timeout case. */ RequestProc->Comm = _K_SVC_PIPE_PUT_TIMEOUT; if (_TIME_B == _k_pipe_time_type_get(&RequestProc->args)) { @@ -170,8 +172,8 @@ void _k_pipe_put_request(struct k_args *RequestOrig) } } else { /* call is non-blocking; - Check if we don't have to queue it b/c it could not - be processed at once + * Check if we don't have to queue it b/c it could not + * be processed at once */ RequestProc->Time.timer = NULL; diff --git a/kernel/microkernel/k_pipe_xfer.c b/kernel/microkernel/k_pipe_xfer.c index eb21921efb2..4eb319e186b 100644 --- a/kernel/microkernel/k_pipe_xfer.c +++ b/kernel/microkernel/k_pipe_xfer.c @@ -31,12 +31,9 @@ /* * - artefacts: ??? * - non-optimal: - * from single requester to multiple requesters : basic function is -pipe_read_write() - pipe_read_write() copies remaining data into buffer; better would be to -possibly copy the remaining data - to the next requester (if there is one) - * ... + * from single requester to multiple requesters : basic function is + * pipe_read_write() - copies remaining data into buffer; better would be to + * possibly copy the remaining data to the next requester (if there is one) */ @@ -314,7 +311,8 @@ static int ReaderInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, K_PIPE_OPTION option; /* first condition: request cannot wait any longer: must be - - * (non-blocked) or a finite timed wait with a killed timer */ + * (non-blocked) or a finite timed wait with a killed timer + */ TimeType = _k_pipe_time_type_get(&reader_ptr->args); option = _k_pipe_option_get(&reader_ptr->args); @@ -325,8 +323,10 @@ static int ReaderInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, || ((_TIME_BT == TimeType) && reader_ptr->Time.timer) #endif ) { - /* requester can still wait (for some time or forever), - no problem for now */ + /* + * requester can still wait (for some time or forever), no + * problem for now + */ return 0; } @@ -334,7 +334,10 @@ static int ReaderInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, if (0 != pipe_ptr->desc.num_pending_writes || 0 != pipe_ptr->desc.num_pending_reads) { - /* buffer activity detected, can't say now that processing is blocked */ + /* + * buffer activity detected, can't say now that processing is + * blocked + */ return 0; } @@ -359,8 +362,10 @@ static int WriterInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, TIME_TYPE TimeType; K_PIPE_OPTION option; - /* first condition: request cannot wait any longer: must be - - * (non-blocked) or a finite timed wait with a killed timer */ + /* + * first condition: request cannot wait any longer: must be - + * (non-blocked) or a finite timed wait with a killed timer + */ TimeType = _k_pipe_time_type_get(&writer_ptr->args); option = _k_pipe_option_get(&writer_ptr->args); @@ -371,8 +376,10 @@ static int WriterInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, || ((_TIME_BT == TimeType) && writer_ptr->Time.timer) #endif ) { - /* requester can still wait (for some time or forever), - no problem for now */ + /* + * requester can still wait (for some time or forever), no + * problem for now + */ return 0; } @@ -380,7 +387,10 @@ static int WriterInProgressIsBlocked(struct _k_pipe_struct *pipe_ptr, if (0 != pipe_ptr->desc.num_pending_writes || 0 != pipe_ptr->desc.num_pending_reads) { - /* buffer activity detected, can't say now that processing is blocked */ + /* + * buffer activity detected, can't say now that processing is + * blocked + */ return 0; } @@ -687,8 +697,9 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, __ASSERT_NO_MSG(!(pNLWriter && pNLReader)); /* both a pNLWriter and pNLReader, is that allowed? - Code below has not been designed for that. - Anyway, this will not happen in current version. */ + * Code below has not been designed for that. + * Anyway, this will not happen in current version. + */ struct k_args *pNextReader; struct k_args *pNextWriter; @@ -711,7 +722,8 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, if (TERM_XXX & reader_ptr->args.pipe_xfer_req.status) { pNextReader = NULL; } else { - pNextReader = reader_ptr; /* == pNLReader */ + /* == pNLReader */ + pNextReader = reader_ptr; } } } else { @@ -823,25 +835,31 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, continue; } else { /* we could break as well, - but then nothing else will happen */ + * but then nothing else will happen + */ return; } } else { #ifdef FORCE_XFER_ON_STALL if (reader_ptr && (_TIME_NB != _k_pipe_time_type_get(&writer_ptr->args))) { - /* force transfer - (we make exception for non-blocked writer) */ + /* force transfer (we make exception + * for non-blocked writer) + */ pipe_read_write(pipe_ptr, writer_ptr, reader_ptr); continue; } else #endif /* we could break as well, - but then nothing else will happen */ + * but then nothing else will happen + */ return; } } else if (bALLNReaderNoGo) { - /* investigate if we must force a transfer to avoid a stall */ + /* + * investigate if we must force a transfer to avoid a + * stall + */ if (!BuffFull(&pipe_ptr->desc)) { if (writer_ptr) { pipe_write(pipe_ptr, writer_ptr); @@ -853,8 +871,9 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, #ifdef FORCE_XFER_ON_STALL if (writer_ptr && (_TIME_NB != _k_pipe_time_type_get(&reader_ptr->args))) { - /* force transfer - (we make exception for non-blocked reader) */ + /* force transfer (we make exception + * for non-blocked reader) + */ pipe_read_write(pipe_ptr, writer_ptr, reader_ptr); continue; } else @@ -862,13 +881,13 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, return; } } else { - /* no blocked reader and no blocked writer - (if there are any of them) - == NOMINAL operation + /* no blocked reader and no blocked writer (if there + * are any of them) == NOMINAL operation */ if (reader_ptr) { if (writer_ptr) { - pipe_read_write(pipe_ptr, writer_ptr, reader_ptr); + pipe_read_write(pipe_ptr, writer_ptr, + reader_ptr); continue; } else { pipe_read(pipe_ptr, reader_ptr); @@ -888,66 +907,65 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, } while (1); /* We stopped processing because nothing changed anymore (stall) - Let's examine the situation a little bit further - */ + * Let's examine the situation a little bit further + */ reader_ptr = pNextReader; writer_ptr = pNextWriter; /* if we come here, it is b/c reader_ptr and writer_ptr did not change - anymore. - - Normally one of them is NULL, which means only a writer, resp. a - reader remained. - - The case that none of them is NULL is a special case which 'normally' - does not occur. - A remaining reader_ptr and/or writer_ptr are expected to be not-completed. - - Note that in the case there is only a reader or there is only a - writer, it can be a ALL_N request. - This happens when his request has not been processed completely yet - (b/c of a copy in and copy out - conflict in the buffer e.g.), but is expected to be processed - completely somewhat later (must be !) - */ + * anymore. + * - Normally one of them is NULL, which means only a writer, resp. a + * reader remained. + * - The case that none of them is NULL is a special case which + * 'normally' does not occur. + * A remaining reader_ptr and/or writer_ptr are expected to be + * not-completed. + * + * Note that in the case there is only a reader or there is only a + * writer, it can be a ALL_N request. + * This happens when his request has not been processed completely yet + * (b/c of a copy in and copy out conflict in the buffer e.g.), but is + * expected to be processed completely somewhat later (must be !) + */ /* in the sequel, we will: - 1. check the hypothesis that an existing reader_ptr/writer_ptr is not - completed - 2. check if we can force the termination of a X_TO_N request when - some data transfer took place - 3. check if we have to cancel a timer when the (first) data has been - Xferred - 4. Check if we have to kick out a queued request because its - processing is really blocked (for some reason) + * 1. check the hypothesis that an existing reader_ptr/writer_ptr is + * not completed + * 2. check if we can force the termination of a X_TO_N request when + * some data transfer took place + * 3. check if we have to cancel a timer when the (first) data has been + * Xferred + * 4. Check if we have to kick out a queued request because its + * processing is really blocked (for some reason) */ if (reader_ptr && writer_ptr) { __ASSERT_NO_MSG(!(TERM_XXX & reader_ptr->args.pipe_xfer_req.status) && !(TERM_XXX & writer_ptr->args.pipe_xfer_req.status)); - /* this could be possible when data Xfer operations are jammed - (out of data Xfer resources e.g.) */ + /* + * this could be possible when data Xfer operations are jammed + * (out of data Xfer resources e.g.) + */ /* later on, at least one of them will be completed. - Force termination of X_TO_N request? - - If one of the requesters is X_TO_N and the other one is - ALL_N, we cannot force termination - of the X_TO_N request - - If they are both X_TO_N, we can do so (but can this - situation be?) - - In this version, we will NOT do so and try to transfer data - as much as possible as - there are now 2 parties present to exchange data, possibly - directly - (this is an implementation choice, but I think it is best for - overall application performance) + * Force termination of X_TO_N request? + * - If one of the requesters is X_TO_N and the other one is + * ALL_N, we cannot force termination of the X_TO_N request + * - If they are both X_TO_N, we can do so (but can this + * situation be?) + * In this version, we will NOT do so and try to transfer data + * as much as possible as there are now 2 parties present to + * exchange data, possibly directly (this is an implementation + * choice, but I think it is best for overall application + * performance) */ ; } else if (reader_ptr) { __ASSERT_NO_MSG(!(TERM_XXX & reader_ptr->args.pipe_xfer_req.status)); /* check if this lonely reader is really blocked, then we will - delist him - (if he was listed uberhaupt) == EMERGENCY BREAK */ + * delist him (if he was listed uberhaupt) == EMERGENCY BREAK + */ if (ReaderInProgressIsBlocked(pipe_ptr, reader_ptr)) { if (_X_TO_N & _k_pipe_option_get(&reader_ptr->args) && (reader_ptr->args.pipe_xfer_req.xferred_size != 0)) { @@ -965,19 +983,25 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, } if (0 == reader_ptr->args.pipe_xfer_req.num_pending_xfers) { reader_ptr->Comm = _K_SVC_PIPE_GET_REPLY; - /* if terminated and no pending Xfers anymore, - we have to reply */ + /* + * if terminated and no pending Xfers anymore, + * we have to reply + */ _k_pipe_get_reply(reader_ptr); } } else { - /* temporary stall (must be, processing will continue - * later on) */ + /* + * temporary stall (must be, processing will continue + * later on) + */ } } else if (writer_ptr) { __ASSERT_NO_MSG(!(TERM_SATISFIED & writer_ptr->args.pipe_xfer_req.status)); - /* check if this lonely Writer is really blocked, then we will - delist him (if he was listed uberhaupt) == EMERGENCY BREAK */ + /* + * check if this lonely Writer is really blocked, then we will + * delist him (if he was listed uberhaupt) == EMERGENCY BREAK + */ if (WriterInProgressIsBlocked(pipe_ptr, writer_ptr)) { if (_X_TO_N & _k_pipe_option_get(&writer_ptr->args) && (writer_ptr->args.pipe_xfer_req.xferred_size != 0)) { @@ -995,14 +1019,18 @@ void _k_pipe_process(struct _k_pipe_struct *pipe_ptr, struct k_args *pNLWriter, } if (0 == writer_ptr->args.pipe_xfer_req.num_pending_xfers) { writer_ptr->Comm = _K_SVC_PIPE_PUT_REPLY; - /* if terminated and no pending Xfers anymore, - we have to reply */ + /* + * if terminated and no pending Xfers anymore, + * we have to reply + */ _k_pipe_put_reply(writer_ptr); } } else { - /* temporary stall (must be, processing will continue - * later on) */ + /* + * temporary stall (must be, processing will continue + * later on) + */ } } else { __ASSERT_NO_MSG(1 == 0); /* we should not come ... here :-) */ diff --git a/kernel/microkernel/k_server.c b/kernel/microkernel/k_server.c index 33a0a1ff025..dc11c2aab54 100644 --- a/kernel/microkernel/k_server.c +++ b/kernel/microkernel/k_server.c @@ -17,12 +17,12 @@ */ /* -DESCRIPTION -This module implements the microkernel server, which processes service requests -from tasks (and, less commonly, fibers and ISRs). The requests are service by -a high priority fiber, thereby ensuring that requests are processed in a timely -manner and in a single threaded manner that prevents simultaneous requests from -interfering with each other. + * DESCRIPTION + * This module implements the microkernel server, which processes service + * requests from tasks (and, less commonly, fibers and ISRs). The requests are + * service by a high priority fiber, thereby ensuring that requests are + * processed in a timely manner and in a single threaded manner that prevents + * simultaneous requests from interfering with each other. */ #include @@ -117,8 +117,10 @@ FUNC_NORETURN void _k_server(int unused1, int unused2) (*pArgs->Comm)(pArgs); } - /* check if another fiber (of equal or greater priority) - * needs to run */ + /* + * check if another fiber (of equal or greater priority) + * needs to run + */ if (_nanokernel.fiber) { fiber_yield(); @@ -129,7 +131,10 @@ FUNC_NORETURN void _k_server(int unused1, int unused2) if (_k_current_task != pNextTask) { - /* switch from currently selected task to a different one */ + /* + * switch from currently selected task to a different + * one + */ #ifdef CONFIG_WORKLOAD_MONITOR if (pNextTask->id == 0x00000000) { diff --git a/kernel/microkernel/k_ticker.c b/kernel/microkernel/k_ticker.c index 87b3f1514a5..72f9abf4a83 100644 --- a/kernel/microkernel/k_ticker.c +++ b/kernel/microkernel/k_ticker.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module implements the microkernel's tick event handler. + * DESCRIPTION + * This module implements the microkernel's tick event handler. */ #include diff --git a/kernel/nanokernel/compiler_stack_protect.c b/kernel/nanokernel/compiler_stack_protect.c index ad7907a8e5a..3efc44dbc8b 100644 --- a/kernel/nanokernel/compiler_stack_protect.c +++ b/kernel/nanokernel/compiler_stack_protect.c @@ -17,13 +17,13 @@ */ /* -DESCRIPTION -This module provides functions to support compiler stack protection -using canaries. This feature is enabled with configuration -CONFIG_STACK_CANARIES=y. - -When this feature is enabled, the compiler generated code refers to -function __stack_chk_fail and global variable __stack_chk_guard. + * DESCRIPTION + * This module provides functions to support compiler stack protection + * using canaries. This feature is enabled with configuration + * CONFIG_STACK_CANARIES=y. + * + * When this feature is enabled, the compiler generated code refers to + * function __stack_chk_fail and global variable __stack_chk_guard. */ #include /* compiler specific configurations */ diff --git a/kernel/nanokernel/ctors.c b/kernel/nanokernel/ctors.c index 51730af333e..075f56fbb8b 100644 --- a/kernel/nanokernel/ctors.c +++ b/kernel/nanokernel/ctors.c @@ -17,16 +17,16 @@ */ /* -DESCRIPTION -This module provides the C++ style constructor mechanism used by various -components to initialize themselves automatically. - -The _Ctors() routine is called from the nanokernel's _Cstart() routine after -hardware initialization has completed. - -Although ctors are traditionally a C++ feature, normal C code can use them too -through the appropriate use of GCC's constructor attribute. -No destructor support (dtors) is provided. + * DESCRIPTION + * This module provides the C++ style constructor mechanism used by various + * components to initialize themselves automatically. + * + * The _Ctors() routine is called from the nanokernel's _Cstart() routine after + * hardware initialization has completed. + * + * Although ctors are traditionally a C++ feature, normal C code can use them + * too through the appropriate use of GCC's constructor attribute. + * No destructor support (dtors) is provided. */ /* What a constructor function pointer looks like */ diff --git a/kernel/nanokernel/idle.c b/kernel/nanokernel/idle.c index a3205e38d64..8e36a9b5578 100644 --- a/kernel/nanokernel/idle.c +++ b/kernel/nanokernel/idle.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides routines to set the idle field in the nanokernel -data structure. + * DESCRIPTION + * This module provides routines to set the idle field in the nanokernel + * data structure. */ #ifdef CONFIG_ADVANCED_POWER_MANAGEMENT diff --git a/kernel/nanokernel/include/gen_offset.h b/kernel/nanokernel/include/gen_offset.h index 6e3bd5666e2..b62c12168ad 100644 --- a/kernel/nanokernel/include/gen_offset.h +++ b/kernel/nanokernel/include/gen_offset.h @@ -17,74 +17,69 @@ */ /* -DESCRIPTION -This header contains macros to allow a nanokernel implementation to -generate absolute symbols whose values represents the member offsets for -various nanokernel structures. These absolute symbols are typically -utilized by assembly source files rather than hardcoding the values in -some local header file. - -WARNING: Absolute symbols can potentially be utilized by external tools -- -for example, to locate a specific field within a data structure. Consequently, -changes made to such symbols may require modifications to the associated -tool(s). Typically, relocating a member of a structure merely requires -that a tool be rebuilt; however, moving a member to another structure -(or to a new sub-structure within an existing structure) may require that -the tool itself be modified. Likewise, deleting, renaming, or changing the -meaning of an absolute symbol may require modifications to a tool. - - -The macro "GEN_OFFSET_SYM(structure, member)" is used to generate a single -absolute symbol. The absolute symbol will appear in the object module -generated from the source file that utilizes the GEN_OFFSET_SYM() macro. -Absolute symbols representing a structure member offset have the following -form: - - ____OFFSET - - -This header also defines the GEN_ABSOLUTE_SYM macro to simply define an -absolute symbol, irrespective of whether the value represents a structure -or offset. - -The following sample file illustrates the usage of the macros available -in this file: - - - -#include - -/@ include struct definitions for which offsets symbols are to be generated @/ - -#include - -GEN_ABS_SYM_BEGIN (_OffsetAbsSyms) /@ the name parameter is arbitrary @/ - -/@ tNANO structure member offsets @/ - -GEN_OFFSET_SYM (tNANO, fiber); -GEN_OFFSET_SYM (tNANO, task); -GEN_OFFSET_SYM (tNANO, current); -GEN_OFFSET_SYM (tNANO, nested); -GEN_OFFSET_SYM (tNANO, common_isp); - -GEN_ABSOLUTE_SYM (__tNANO_SIZEOF, sizeof(tNANO)); - -GEN_ABS_SYM_END - - - -Compiling the sample offsets.c results in the following symbols in offsets.o: - -$ nm offsets.o -00000010 A __tNANO_common_isp_OFFSET -00000008 A __tNANO_current_OFFSET -0000000c A __tNANO_nested_OFFSET -00000000 A __tNANO_fiber_OFFSET -00000004 A __tNANO_task_OFFSET - - -\NOMANUAL + * DESCRIPTION + * This header contains macros to allow a nanokernel implementation to + * generate absolute symbols whose values represents the member offsets for + * various nanokernel structures. These absolute symbols are typically + * utilized by assembly source files rather than hardcoding the values in + * some local header file. + * + * WARNING: Absolute symbols can potentially be utilized by external tools -- + * for example, to locate a specific field within a data structure. + * Consequently, changes made to such symbols may require modifications to the + * associated tool(s). Typically, relocating a member of a structure merely + * requires that a tool be rebuilt; however, moving a member to another + * structure (or to a new sub-structure within an existing structure) may + * require that the tool itself be modified. Likewise, deleting, renaming, or + * changing the meaning of an absolute symbol may require modifications to a + * tool. + * + * The macro "GEN_OFFSET_SYM(structure, member)" is used to generate a single + * absolute symbol. The absolute symbol will appear in the object module + * generated from the source file that utilizes the GEN_OFFSET_SYM() macro. + * Absolute symbols representing a structure member offset have the following + * form: + * + * ____OFFSET + * + * This header also defines the GEN_ABSOLUTE_SYM macro to simply define an + * absolute symbol, irrespective of whether the value represents a structure + * or offset. + * + * The following sample file illustrates the usage of the macros available + * in this file: + * + * + * + * #include + * /@ include struct definitions for which offsets symbols are to be + * generated @/ + * + * #include + * GEN_ABS_SYM_BEGIN (_OffsetAbsSyms) /@ the name parameter is arbitrary @/ + * /@ tNANO structure member offsets @/ + * + * GEN_OFFSET_SYM (tNANO, fiber); + * GEN_OFFSET_SYM (tNANO, task); + * GEN_OFFSET_SYM (tNANO, current); + * GEN_OFFSET_SYM (tNANO, nested); + * GEN_OFFSET_SYM (tNANO, common_isp); + * + * GEN_ABSOLUTE_SYM (__tNANO_SIZEOF, sizeof(tNANO)); + * + * GEN_ABS_SYM_END + * + * + * Compiling the sample offsets.c results in the following symbols in offsets.o: + * + * $ nm offsets.o + * 00000010 A __tNANO_common_isp_OFFSET + * 00000008 A __tNANO_current_OFFSET + * 0000000c A __tNANO_nested_OFFSET + * 00000000 A __tNANO_fiber_OFFSET + * 00000004 A __tNANO_task_OFFSET + * + * \NOMANUAL */ #ifndef _GEN_OFFSET_H diff --git a/kernel/nanokernel/include/nano_internal.h b/kernel/nanokernel/include/nano_internal.h index 5090ab09918..bbbccf5e506 100644 --- a/kernel/nanokernel/include/nano_internal.h +++ b/kernel/nanokernel/include/nano_internal.h @@ -17,8 +17,9 @@ */ /* -DESCRIPTION -This file contains private nanokernel APIs that are not architecture-specific. + * DESCRIPTION + * This file contains private nanokernel APIs that are not + * architecture-specific. */ #ifndef _NANO_INTERNAL__H_ diff --git a/kernel/nanokernel/include/timeout_q.h b/kernel/nanokernel/include/timeout_q.h index cfc6cd17d7e..000dd814786 100644 --- a/kernel/nanokernel/include/timeout_q.h +++ b/kernel/nanokernel/include/timeout_q.h @@ -1,7 +1,7 @@ /** @file - @brief timeout queue for fibers on nanokernel objects - - This file is meant to be included by nanokernel/include/wait_q.h only + * @brief timeout queue for fibers on nanokernel objects + * + * This file is meant to be included by nanokernel/include/wait_q.h only */ /* diff --git a/kernel/nanokernel/int_latency_bench.c b/kernel/nanokernel/int_latency_bench.c index 33c7c945662..59070a5efdb 100644 --- a/kernel/nanokernel/int_latency_bench.c +++ b/kernel/nanokernel/int_latency_bench.c @@ -152,7 +152,8 @@ void int_latency_init(void) timeToReadTime = _sys_clock_cycle_get() - timeToReadTime; /* measure time to call intLatencyStart() and intLatencyStop - * takes */ + * takes + */ initial_start_delay = _sys_clock_cycle_get(); _int_latency_start(); initial_start_delay = diff --git a/kernel/nanokernel/nano_context.c b/kernel/nanokernel/nano_context.c index 51b0b3ef73d..9d85a5c543f 100644 --- a/kernel/nanokernel/nano_context.c +++ b/kernel/nanokernel/nano_context.c @@ -17,9 +17,9 @@ */ /* -DESCRIPTION -This module provides general purpose thread support, with applies to both -tasks or fibers. + * DESCRIPTION + * This module provides general purpose thread support, with applies to both + * tasks or fibers. */ #include diff --git a/kernel/nanokernel/nano_fiber.c b/kernel/nanokernel/nano_fiber.c index fe8e0205688..71b3fdd48c8 100644 --- a/kernel/nanokernel/nano_fiber.c +++ b/kernel/nanokernel/nano_fiber.c @@ -88,8 +88,10 @@ void _fiber_start(char *pStack, priority, options); - /* _new_thread() has already set the flags depending on the 'options' - * and 'priority' parameters passed to it */ + /* + * _new_thread() has already set the flags depending on the 'options' + * and 'priority' parameters passed to it + */ /* lock interrupts to prevent corruption of the runnable fiber list */ diff --git a/kernel/nanokernel/nano_init.c b/kernel/nanokernel/nano_init.c index a3e56afc4ba..1306458b69a 100644 --- a/kernel/nanokernel/nano_init.c +++ b/kernel/nanokernel/nano_init.c @@ -17,8 +17,8 @@ */ /* -DESCRIPTION -This module contains routines that are used to initialize the nanokernel. + * DESCRIPTION + * This module contains routines that are used to initialize the nanokernel. */ #include diff --git a/kernel/nanokernel/nano_timer.c b/kernel/nanokernel/nano_timer.c index 400dc0f0fca..29fe6d56661 100644 --- a/kernel/nanokernel/nano_timer.c +++ b/kernel/nanokernel/nano_timer.c @@ -52,7 +52,8 @@ FUNC_ALIAS(_timer_start, nano_task_timer_start, void); */ void _timer_start(struct nano_timer *timer, /* timer to start */ int ticks /* number of system ticks - before expiry */ + * before expiry + */ ) { unsigned int imask; diff --git a/lib/libc/minimal/source/stdlib/atoi.c b/lib/libc/minimal/source/stdlib/atoi.c index 50a7dee5c6c..e63516cab9b 100644 --- a/lib/libc/minimal/source/stdlib/atoi.c +++ b/lib/libc/minimal/source/stdlib/atoi.c @@ -1,25 +1,25 @@ /* -Copyright © 2005-2014 Rich Felker, et al. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice shall be -included in all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ + * Copyright © 2005-2014 Rich Felker, et al. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ /* From: http://fossies.org/dox/musl-1.0.5/atoi_8c_source.html */ diff --git a/lib/libc/minimal/source/stdout/prf.c b/lib/libc/minimal/source/stdout/prf.c index 03d1b57f8d9..9665d9964d5 100644 --- a/lib/libc/minimal/source/stdout/prf.c +++ b/lib/libc/minimal/source/stdout/prf.c @@ -198,8 +198,8 @@ static void _rlrshift(uint32_t value[]) } /* - 64 bit divide by 5 function for _to_float. - The result is ROUNDED, not TRUNCATED. + * 64 bit divide by 5 function for _to_float. + * The result is ROUNDED, not TRUNCATED. */ static void _ldiv5(uint32_t value[]) diff --git a/lib/libc/minimal/source/string/strncasecmp.c b/lib/libc/minimal/source/string/strncasecmp.c index 47fb0992148..93f29e451f6 100644 --- a/lib/libc/minimal/source/string/strncasecmp.c +++ b/lib/libc/minimal/source/string/strncasecmp.c @@ -11,13 +11,12 @@ */ /* -@deftypefn Supplemental int strncasecmp (const char *@var{s1}, const char *@var{s2}) - -A case-insensitive @code{strncmp}. - -@end deftypefn - -*/ + * @deftypefn Supplemental int strncasecmp (const char *@var{s1}, const char *@var{s2}) + * + * A case-insensitive @code{strncmp}. + * + * @end deftypefn + */ /* From: * http://opensource.apple.com/source/gcc_os/gcc_os-1671/libiberty/strncasecmp.c