checkpatch: warning - block_comment_style

Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

arch/arc/core/fatal.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module implements the routines necessary for handling fatal faults on
+ * This module implements the routines necessary for handling fatal faults on
-ARCv2 CPUs.
+ * ARCv2 CPUs.
  */
 
 #include <nano_private.h>

arch/arc/core/offsets/offsets.c

@@ -17,21 +17,20 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module is responsible for the generation of the absolute symbols whose
+ * This module is responsible for the generation of the absolute symbols whose
-value represents the member offsets for various ARCv2 nanokernel
+ * value represents the member offsets for various ARCv2 nanokernel
-structures.
+ * structures.
-
+ *
-All of the absolute symbols defined by this module will be present in the
+ * All of the absolute symbols defined by this module will be present in the
-final microkernel or nanokernel ELF image (due to the linker's reference to
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
-the _OffsetAbsSyms symbol).
+ * the _OffsetAbsSyms symbol).
-
+ *
-INTERNAL
+ * INTERNAL
-It is NOT necessary to define the offset for every member of a structure.
+ * It is NOT necessary to define the offset for every member of a structure.
-Typically, only those members that are accessed by assembly language routines
+ * Typically, only those members that are accessed by assembly language routines
-are defined; however, it doesn't hurt to define all fields for the sake of
+ * are defined; however, it doesn't hurt to define all fields for the sake of
-completeness.
+ * completeness.
-
  */
 
 #include <gen_offset.h>

arch/arc/core/prep_c.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Initialization of full C support: zero the .bss, copy the .data if XIP,
+ * Initialization of full C support: zero the .bss, copy the .data if XIP,
-call _Cstart().
+ * call _Cstart().
-
+ *
-Stack is available in this module, but not the global data/bss until their
+ * Stack is available in this module, but not the global data/bss until their
-initialization is performed.
+ * initialization is performed.
  */
 
 #include <stdint.h>

arch/arc/core/sys_fatal_error_handler.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
+ * This module provides the _SysFatalErrorHandler() routine for ARCv2 BSPs.
  */
 
 #include <nanokernel.h>

arch/arc/core/vector_table.c

@@ -17,20 +17,20 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Vector table with exceptions filled in. The reset vector is the system entry
+ * Vector table with exceptions filled in. The reset vector is the system entry
-point, ie. the first instruction executed.
+ * point, ie. the first instruction executed.
-
+ *
-The table is populated with all the system exception handlers. No exception
+ * The table is populated with all the system exception handlers. No exception
-should not be triggered until the kernel is ready to handle them.
+ * should not be triggered until the kernel is ready to handle them.
-
+ *
-We are using a C file instead of an assembly file (like the ARM vector table)
+ * We are using a C file instead of an assembly file (like the ARM vector table)
-to work around an issue with the assembler where:
+ * to work around an issue with the assembler where:
-
+ *
-  .word <function>
+ *   .word <function>
-
+ *
-statements would end up with the two half-words of the functions' addresses
+ * statements would end up with the two half-words of the functions' addresses
-swapped.
+ * swapped.
  */
 
 #include <stdint.h>

arch/arc/include/nano_private.h

@@ -17,14 +17,14 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains private nanokernel structures definitions and various other
+ * This file contains private nanokernel structures definitions and various
-definitions for the ARCv2 processor architecture.
+ * other definitions for the ARCv2 processor architecture.
-
+ *
-This file is also included by assembly language files which must #define
+ * This file is also included by assembly language files which must #define
-_ASMLANGUAGE before including this header file.  Note that nanokernel assembly
+ * _ASMLANGUAGE before including this header file.  Note that nanokernel
-source files obtains structure offset values via "absolute symbols" in the
+ * assembly source files obtains structure offset values via "absolute
-offsets.o module.
+ * symbols" in the offsets.o module.
  */
 
 #ifndef _NANO_PRIVATE_H
@@ -160,15 +160,16 @@ typedef struct firq_regs tFirqRegs;
 #ifndef _ASMLANGUAGE
 
 struct tcs {
-	struct tcs *link;          /* node in singly-linked list
+	struct tcs *link;         /* node in singly-linked list
-								* _nanokernel.fibers */
+				   * _nanokernel.fibers
-	uint32_t flags;            /* bitmask of flags above */
+				   */
-	uint32_t intlock_key;      /* interrupt key when relinquishing control */
+	uint32_t flags;           /* bitmask of flags above */
-	int relinquish_cause;      /* one of the _CAUSE_xxxx definitions above */
+	uint32_t intlock_key;     /* interrupt key when relinquishing control */
-	unsigned int return_value; /* return value from _Swap */
+	int relinquish_cause;     /* one of the _CAUSE_xxxx definitions above */
-	int prio;                  /* fiber priority, -1 for a task */
+	unsigned int return_value;/* return value from _Swap */
+	int prio;                 /* fiber priority, -1 for a task */
 #ifdef CONFIG_THREAD_CUSTOM_DATA
-	void *custom_data;         /* available for custom use */
+	void *custom_data;        /* available for custom use */
 #endif
 	struct coop coopReg;
 	struct preempt preempReg;

arch/arc/include/vector_table.h

@@ -17,15 +17,15 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Definitions for the boot vector table.
+ * Definitions for the boot vector table.
-
+ *
-System exception handler names all have the same format:
+ * System exception handler names all have the same format:
-
+ *
-  __<exception name with underscores>
+ *   __<exception name with underscores>
-
+ *
-Refer to the ARCv2 manual for an explanation of the exceptions.
+ * Refer to the ARCv2 manual for an explanation of the exceptions.
  */
 
 #ifndef _VECTOR_TABLE__H_

arch/arc/platforms/generic_arc/board.h

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for the
+ * This header file is used to specify and describe board-level aspects for the
-generic arc BSP.
+ * generic arc BSP.
-*/
+ */
 
 #ifndef _BOARD__H_
 #define _BOARD__H_

arch/arc/platforms/generic_arc/irq_vector_table.c

@@ -17,16 +17,16 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains the IRQ part of the vector table. It is meant to be used
+ * This file contains the IRQ part of the vector table. It is meant to be used
-for one of two cases:
+ * for one of two cases:
-
+ *
-a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
+ * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
-   binds _IsrWrapper() to all the IRQ entries in the vector table.
+ *    binds _IsrWrapper() to all the IRQ entries in the vector table.
-
+ *
-b) When the BSP is written so that device ISRs are installed directly in the
+ * b) When the BSP is written so that device ISRs are installed directly in the
-   vector table, they are enumerated here.
+ *    vector table, they are enumerated here.
-*/
+ */
 
 #include <toolchain.h>
 #include <sections.h>

arch/arc/platforms/generic_arc/sw_isr_table.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This contains the ISR table meant to be used for ISRs that take a parameter.
+ * This contains the ISR table meant to be used for ISRs that take a parameter.
-It is also used when ISRs are to be connected at runtime, and in this case
+ * It is also used when ISRs are to be connected at runtime, and in this case
-provides a table that is filled with _SpuriousIRQ bindings.
+ * provides a table that is filled with _SpuriousIRQ bindings.
-*/
+ */
 
 #include <toolchain.h>
 #include <sections.h>

arch/arc/platforms/generic_arc/system.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level hardware
-for the generic arc platform.
+ * for the generic arc platform.
-*/
+ */
 
 #include <nanokernel.h>
 #include <board.h>

arch/arm/core/cortex_m/nmi.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Provides a boot time handler that simply hangs in a sleep loop, and a run time
+ * Provides a boot time handler that simply hangs in a sleep loop, and a run
-handler that resets the CPU. Also provides a mechanism for hooking a custom
+ * time handler that resets the CPU. Also provides a mechanism for hooking a
-run time handler.
+ * custom run time handler.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/prep_c.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Initialization of full C support: zero the .bss, copy the .data if XIP,
+ * Initialization of full C support: zero the .bss, copy the .data if XIP,
-call _Cstart().
+ * call _Cstart().
-
+ *
-Stack is available in this module, but not the global data/bss until their
+ * Stack is available in this module, but not the global data/bss until their
-initialization is performed.
+ * initialization is performed.
  */
 
 #include <stdint.h>

arch/arm/core/cortex_m/scb.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Most of the SCB interface consists of simple bit-flipping methods, and is
+ * Most of the SCB interface consists of simple bit-flipping methods, and is
-implemented as inline functions in scb.h. This module thus contains only data
+ * implemented as inline functions in scb.h. This module thus contains only data
-definitions and more complex routines, if needed.
+ * definitions and more complex routines, if needed.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/scs.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Most of the SCS interface consists of simple bit-flipping methods, and is
+ * Most of the SCS interface consists of simple bit-flipping methods, and is
-implemented as inline functions in scs.h. This module thus contains only data
+ * implemented as inline functions in scs.h. This module thus contains only data
-definitions and more complex routines, if needed.
+ * definitions and more complex routines, if needed.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/vector_table.h

@@ -17,15 +17,15 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Definitions for the boot vector table.
+ * Definitions for the boot vector table.
-
+ *
-System exception handler names all have the same format:
+ * System exception handler names all have the same format:
-
+ *
-  __<exception name with underscores>
+ *   __<exception name with underscores>
-
+ *
-No other symbol has the same format, so they are easy to spot.
+ * No other symbol has the same format, so they are easy to spot.
  */
 
 #ifndef _VECTOR_TABLE__H_

arch/arm/core/fatal.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
+ * This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
  */
 
 #include <toolchain.h>

arch/arm/core/fault.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Common fault handler for ARM Cortex-M processors.
+ * Common fault handler for ARM Cortex-M processors.
  */
 
 #include <toolchain.h>

arch/arm/core/fiber_abort.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-The ARM Cortex-M architecture provides its own fiber_abort() to deal with
+ * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
-different CPU modes (handler vs thread) when a fiber aborts. When its entry
+ * different CPU modes (handler vs thread) when a fiber aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
+ * point returns or when it aborts itself, the CPU is in thread mode and must
-call _Swap() (which triggers a service call), but when in handler mode, the
+ * call _Swap() (which triggers a service call), but when in handler mode, the
-CPU must exit handler mode to cause the context switch, and thus must queue
+ * CPU must exit handler mode to cause the context switch, and thus must queue
-the PendSV exception.
+ * the PendSV exception.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/arm/core/gdb_stub_irq_vector_table.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-When GDB is enabled, the static IRQ vector table needs to install the
+ * When GDB is enabled, the static IRQ vector table needs to install the
-_irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
+ * _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
-user-installed ISRs.
+ * user-installed ISRs.
  */
 
 #include <toolchain.h>

arch/arm/core/irq_init.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-The ARM Cortex-M architecture provides its own fiber_abort() to deal with
+ * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
-different CPU modes (handler vs thread) when a fiber aborts. When its entry
+ * different CPU modes (handler vs thread) when a fiber aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
+ * point returns or when it aborts itself, the CPU is in thread mode and must
-call _Swap() (which triggers a service call), but when in handler mode, the
+ * call _Swap() (which triggers a service call), but when in handler mode, the
-CPU must exit handler mode to cause the context switch, and thus must queue
+ * CPU must exit handler mode to cause the context switch, and thus must queue
-the PendSV exception.
+ * the PendSV exception.
  */
 
 #include <toolchain.h>

arch/arm/core/irq_manage.c

@@ -17,10 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Interrupt management: enabling/disabling and dynamic ISR connecting/replacing.
+ * Interrupt management: enabling/disabling and dynamic ISR
-SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime.
+ * connecting/replacing.  SW_ISR_TABLE_DYNAMIC has to be enabled for
+ * connecting ISRs at runtime.
  */
 
 #include <nanokernel.h>

arch/arm/core/offsets/offsets.c

@@ -17,21 +17,20 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module is responsible for the generation of the absolute symbols whose
+ * This module is responsible for the generation of the absolute symbols whose
-value represents the member offsets for various ARM nanokernel
+ * value represents the member offsets for various ARM nanokernel
-structures.
+ * structures.
-
+ *
-All of the absolute symbols defined by this module will be present in the
+ * All of the absolute symbols defined by this module will be present in the
-final microkernel or nanokernel ELF image (due to the linker's reference to
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
-the _OffsetAbsSyms symbol).
+ * the _OffsetAbsSyms symbol).
-
+ *
-INTERNAL
+ * INTERNAL
-It is NOT necessary to define the offset for every member of a structure.
+ * It is NOT necessary to define the offset for every member of a structure.
-Typically, only those members that are accessed by assembly language routines
+ * Typically, only those members that are accessed by assembly language routines
-are defined; however, it doesn't hurt to define all fields for the sake of
+ * are defined; however, it doesn't hurt to define all fields for the sake of
-completeness.
+ * completeness.
-
  */
 
 #include <gen_offset.h>

arch/arm/core/sys_fatal_error_handler.c

@@ -17,8 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the _SysFatalErrorHandler() routine for Cortex-M platforms.
+ * This module provides the _SysFatalErrorHandler() routine for Cortex-M
+ * platforms.
  */
 
 #include <nanokernel.h>

arch/arm/core/task_abort.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
+ * The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
-different CPU modes (handler vs thread) when a task aborts. When its entry
+ * different CPU modes (handler vs thread) when a task aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
+ * point returns or when it aborts itself, the CPU is in thread mode and must
-call the equivalent of task_abort(<self>), but when in handler mode, the
+ * call the equivalent of task_abort(<self>), but when in handler mode, the
-CPU must queue a packet to _k_server(), then exit handler mode to queue the
+ * CPU must queue a packet to _k_server(), then exit handler mode to queue the
-PendSV exception and cause the immediate context switch to _k_server.
+ * PendSV exception and cause the immediate context switch to _k_server.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/arm/core/thread.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Core nanokernel fiber related primitives for the ARM Cortex-M processor
+ * Core nanokernel fiber related primitives for the ARM Cortex-M processor
-architecture.
+ * architecture.
  */
 
 #include <nanokernel.h>
@@ -57,8 +57,9 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
 	unsigned int key;
 
 	/*
-	 * Add the newly initialized thread to head of the list of threads.  This
+	 * Add the newly initialized thread to head of the list of threads.
-	 * singly linked list of threads maintains ALL the threads in the system:
+	 * This singly linked list of threads maintains ALL the threads in the
+	 * system:
 	 * both tasks and fibers regardless of whether they are runnable.
 	 */
 

arch/arm/include/cortex_m/exc.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Exception/interrupt context helpers.
+ * Exception/interrupt context helpers.
  */
 
 #ifndef _ARM_CORTEXM_ISR__H_

arch/arm/include/cortex_m/stack.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Stack helper functions.
+ * Stack helper functions.
  */
 
 #ifndef _ARM_CORTEXM_STACK__H_

arch/arm/include/nano_private.h

@@ -17,14 +17,14 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains private nanokernel structures definitions and various other
+ * This file contains private nanokernel structures definitions and various
-definitions for the ARM Cortex-M3 processor architecture.
+ * other definitions for the ARM Cortex-M3 processor architecture.
-
+ *
-This file is also included by assembly language files which must #define
+ * This file is also included by assembly language files which must #define
-_ASMLANGUAGE before including this header file.  Note that nanokernel assembly
+ * _ASMLANGUAGE before including this header file.  Note that nanokernel
-source files obtains structure offset values via "absolute symbols" in the
+ * assembly source files obtains structure offset values via "absolute symbols"
-offsets.o module.
+ * in the offsets.o module.
  */
 
 #ifndef _NANO_PRIVATE_H

arch/arm/include/start_task_arch.h

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARM-specific parts of start_task().
+ * ARM-specific parts of start_task().
-
+ *
-Currently empty, only here for abstraction.
+ * Currently empty, only here for abstraction.
  */
 
 #ifndef _START_TASK_ARCH__H_

arch/arm/platforms/fsl_frdm_k64f/board.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for the
+ * This header file is used to specify and describe board-level aspects for the
-'fsl_frdm_k64f' platform.
+ * 'fsl_frdm_k64f' platform.
  */
 
 #ifndef _BOARD__H_

arch/arm/platforms/fsl_frdm_k64f/irq_vector_table.c

@@ -17,15 +17,15 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains the IRQ part of the vector table. It is meant to be used
+ * This file contains the IRQ part of the vector table. It is meant to be used
-for one of two cases:
+ * for one of two cases:
-
+ *
-a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
+ * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
-   binds _isr_wrapper() to all the IRQ entries in the vector table.
+ *    binds _isr_wrapper() to all the IRQ entries in the vector table.
-
+ *
-b) When the platform is written so that device ISRs are installed directly in
+ * b) When the platform is written so that device ISRs are installed directly in
-   the vector table, they are enumerated here.
+ *    the vector table, they are enumerated here.
  */
 
 #include <toolchain.h>

arch/arm/platforms/fsl_frdm_k64f/system.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level
-for the fsl_frdm_k64f platform.
+ * hardware for the fsl_frdm_k64f platform.
  */
 
 #include <nanokernel.h>
@@ -67,7 +67,7 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
 	/* Backdoor Comparison Key (unused) */
 	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 	/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
-	   */
+	 */
 	0xFF, 0xFF, 0xFF, 0xFF,
 	/*
 	 * Flash security: Backdoor key disabled, Mass erase enabled,
@@ -89,7 +89,8 @@ uint8_t __security_frdm_k64f_section __security_frdm_k64f[] = {
  * that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
  * It transitions through the FLL Bypassed External (FBE) and
  * PLL Bypassed External (PBE) modes to get to the desired
- * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system clock.
+ * PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
+ * clock.
  *
  * @return N/A
  *
@@ -152,15 +153,19 @@ static void clkInit(void)
 
 	mcg_p->c1 = temp_reg;
 
-	/* Confirm that the external reference clock is the FLL reference source
+	/*
+	 * Confirm that the external reference clock is the FLL reference
+	 * source
 	 */
 
 	while ((mcg_p->s & MCG_S_IREFST_MASK) != 0)
 		;
 	;
 
-	/* Confirm the external ref. clock is the system clock source
+	/*
-	 * (MCGOUTCLK) */
+	 * Confirm the external ref. clock is the system clock source
+	 * (MCGOUTCLK)
+	 */
 
 	while ((mcg_p->s & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXT_REF)
 		;
@@ -298,10 +303,14 @@ static int fsl_frdm_k64f_init(struct device *arg)
 				(SIM_CLKDIV(3) << SIM_CLKDIV1_OUTDIV3_SHIFT) |
 				(SIM_CLKDIV(5) << SIM_CLKDIV1_OUTDIV4_SHIFT));
 
-	clkInit(); /* Initialize PLL/system clock to 120 MHz */
+	/* Initialize PLL/system clock to 120 MHz */
+	clkInit();
 
-	NMI_INIT(); /* install default handler that simply resets the CPU
+	/*
-		     * if configured in the kernel, NOP otherwise */
+	 * install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise 
+	 */
+	NMI_INIT();
 
 	/* restore interrupt state */
 	irq_unlock(oldLevel);

arch/arm/platforms/ti_lm3s6965/board.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for
+ * This header file is used to specify and describe board-level aspects for
-the 'ti_lm3s6965' platform.
+ * the 'ti_lm3s6965' platform.
  */
 
 #ifndef _BOARD__H_

arch/arm/platforms/ti_lm3s6965/irq_vector_table.c

@@ -17,15 +17,15 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains the IRQ part of the vector table. It is meant to be used
+ * This file contains the IRQ part of the vector table. It is meant to be used
-for one of two cases:
+ * for one of two cases:
-
+ *
-a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
+ * a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
-   binds _isr_wrapper() to all the IRQ entries in the vector table.
+ *    binds _isr_wrapper() to all the IRQ entries in the vector table.
-
+ *
-b) When the platform is written so that device ISRs are installed directly in
+ * b) When the platform is written so that device ISRs are installed directly in
-   the vector table, they are enumerated here.
+ *    the vector table, they are enumerated here.
  */
 
 #include <toolchain.h>

arch/arm/platforms/ti_lm3s6965/scp.c

@@ -17,12 +17,12 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Library for controlling target-specific devices present in the 0x400fe000
+ * Library for controlling target-specific devices present in the 0x400fe000
-peripherals memory region.
+ * peripherals memory region.
-
+ *
-Currently, only enabling the main OSC with default value is implemented.
+ * Currently, only enabling the main OSC with default value is implemented.
  */
 
 #include <stdint.h>

arch/arm/platforms/ti_lm3s6965/scp.h

@@ -17,21 +17,21 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module defines the System Control Peripheral Registers for TI LM3S6965
+ * This module defines the System Control Peripheral Registers for TI LM3S6965
-processor. The registers defined are in region 0x400fe000.
+ * processor. The registers defined are in region 0x400fe000.
-
+ *
-  System Control	0x400fe000
+ *   System Control	0x400fe000
-
+ *
-These modules are not defined:
+ * These modules are not defined:
-
+ *
-  Hibernation Module	0x400fc000
+ *   Hibernation Module	0x400fc000
-  Internal Memory	0x400fd000
+ *   Internal Memory	0x400fd000
-  Hibernation Module	0x400fc000
+ *   Hibernation Module	0x400fc000
-
+ *
-The registers and bit field names are taken from the 'Stellaris LM3S6965
+ * The registers and bit field names are taken from the 'Stellaris LM3S6965
-Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
+ * Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document,
-section 5.4/5.5, pp .184-200.
+ * section 5.4/5.5, pp .184-200.
  */
 
 #ifndef _SCP_H_

arch/arm/platforms/ti_lm3s6965/system.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level hardware
-for the ti_lm3s6965 platform.
+ * for the ti_lm3s6965 platform.
  */
 
 #include <nanokernel.h>

arch/x86/core/atomic_nolock.c

@@ -17,18 +17,18 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the atomic operators for IA-32 architectures on platforms
+ * This module provides the atomic operators for IA-32 architectures on
-that do not support the LOCK prefix instruction.
+ * platforms that do not support the LOCK prefix instruction.
-
+ *
-The atomic operations are guaranteed to be atomic with respect to interrupt
+ * The atomic operations are guaranteed to be atomic with respect to interrupt
-service routines. However, they are NOT guaranteed to be atomic with respect
+ * service routines. However, they are NOT guaranteed to be atomic with respect
-to operations performed by peer processors, unlike the versions of these
+ *to operations performed by peer processors, unlike the versions of these
-operators that do utilize the LOCK prefix instruction.
+ * operators that do utilize the LOCK prefix instruction.
-
+ *
-INTERNAL
+ * INTERNAL
-These operators are currently unavailable to user space applications
+ * These operators are currently unavailable to user space applications
-as there is no requirement for this capability.
+ * as there is no requirement for this capability.
  */
 
 #if defined(CONFIG_LOCK_INSTRUCTION_UNSUPPORTED)

arch/x86/core/cache.c

@@ -16,8 +16,8 @@
  * limitations under the License.
  */
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module contains functions for manipulation caches.
+ * This module contains functions for manipulation caches.
  */
 
 #include <nanokernel.h>

arch/x86/core/excconnect.c

@@ -17,49 +17,49 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to manage exceptions (synchronous interrupts)
+ * This module provides routines to manage exceptions (synchronous interrupts)
-on the IA-32 architecture.
+ * on the IA-32 architecture.
-
+ *
-This module provides the public routine nanoCpuExcConnect().
+ * This module provides the public routine nanoCpuExcConnect().
-
+ *
-INTERNAL
+ * INTERNAL
-An exception is defined as a synchronous interrupt, i.e. an interrupt
+ * An exception is defined as a synchronous interrupt, i.e. an interrupt
-asserted as a direct result of program execution as opposed to a
+ * asserted as a direct result of program execution as opposed to a
-hardware device asserting an interrupt.
+ * hardware device asserting an interrupt.
-
+ *
-Many (but not all) exceptions are handled by an "exception stub" whose code
+ * Many (but not all) exceptions are handled by an "exception stub" whose code
-is generated by the system itself.  The stub performs various actions before
+ * is generated by the system itself.  The stub performs various actions before
-and after invoking the application (or operating system) specific exception
+ * and after invoking the application (or operating system) specific exception
-handler; for example, a thread or ISR context save is performed prior to
+ * handler; for example, a thread or ISR context save is performed prior to
-invoking the exception handler.
+ * invoking the exception handler.
-
+ *
-The IA-32 code that makes up a "full" exception stub is shown below.  A full
+ * The IA-32 code that makes up a "full" exception stub is shown below.  A full
-exception stub is one that pushes a dummy error code at the start of
+ * exception stub is one that pushes a dummy error code at the start of
-exception processing.  Exception types where the processor automatically
+ * exception processing.  Exception types where the processor automatically
-pushes an error code when handling an exception utilize similar exception
+ * pushes an error code when handling an exception utilize similar exception
-stubs, however the first instruction is omitted.  The use of the dummy error
+ * stubs, however the first instruction is omitted.  The use of the dummy error
-code means that _ExcEnt() and _ExcExit() do not have to worry about whether
+ * code means that _ExcEnt() and _ExcExit() do not have to worry about whether
-an error code is present on the stack or not.
+ * an error code is present on the stack or not.
-
+ *
-
+ *
-  0x00   pushl   $0			/@ push dummy error code @/
+ *   0x00   pushl   $0			/@ push dummy error code @/
-  Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
+ *   Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
-
+ *
-  0x05   call    _ExcEnt		/@ inform kernel of exception @/
+ *   0x05   call    _ExcEnt		/@ inform kernel of exception @/
-  Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
+ *   Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
-
+ *
-  0x0a   call    ExcHandler		/@ invoke exception handler @/
+ *   0x0a   call    ExcHandler		/@ invoke exception handler @/
-  Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
+ *   Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
-
+ *
-  /@ _ExcExit() will adjust the stack to discard the error code @/
+ *   /@ _ExcExit() will adjust the stack to discard the error code @/
-
+ *
-  0x0f  jmp	   _ExcExit		/@ restore thread context @/
+ *   0x0f  jmp	   _ExcExit		/@ restore thread context @/
-  Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
+ *   Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
-
+ *
-NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE
+ * NOTE: Be sure to update the arch specific definition of the _EXC_STUB_SIZE
-macro to reflect the size of the full exception stub (as shown above).
+ * macro to reflect the size of the full exception stub (as shown above).
-The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h.
+ * The _EXC_STUB_SIZE macro is defined in arch/x86/include/nano_private.h.
  */
 
 
@@ -105,7 +105,8 @@ void _NanoCpuExcConnectAtDpl(unsigned int vector,
  */
 
 void nanoCpuExcConnect(unsigned int vector, /* interrupt vector: 0 to 255 on
-					       IA-32 */
+					     * IA-32
+					     */
 		       void (*routine)(NANO_ESF * pEsf),
 		       NANO_EXC_STUB pExcStubMem)
 {

arch/x86/core/fatal.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the _NanoFatalErrorHandler() routine.
+ * This module provides the _NanoFatalErrorHandler() routine.
  */
 
 #include <toolchain.h>

arch/x86/core/float.c

@@ -17,61 +17,63 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module allows multiple tasks and fibers to safely share the system's
+ * This module allows multiple tasks and fibers to safely share the system's
-floating point resources, by allowing the system to save FPU state information
+ * floating point resources, by allowing the system to save FPU state
-in a task or fiber's stack region when a pre-emptive context switch occurs.
+ * information in a task or fiber's stack region when a pre-emptive context
-
+ * switch occurs.
-The floating point resource sharing mechanism is designed for minimal
+ *
-intrusiveness.  Floating point thread saving is only performed for tasks and
+ * The floating point resource sharing mechanism is designed for minimal
-fibers that explicitly enable FP resource sharing, to avoid impacting the stack
+ * intrusiveness.  Floating point thread saving is only performed for tasks and
-size requirements of all other tasks and fibers.  For those tasks and fibers
+ * fibers that explicitly enable FP resource sharing, to avoid impacting the
-that do require FP resource sharing, a "lazy save/restore" mechanism is employed
+ * stack size requirements of all other tasks and fibers.  For those tasks and
-so that the FPU's register sets are only switched in and out when absolutely
+ * fibers that do require FP resource sharing, a "lazy save/restore" mechanism
-necessary; this avoids wasting effort preserving them when there is no risk
+ * is employed so that the FPU's register sets are only switched in and out
-that they will be altered, or when there is no need to preserve their contents.
+ * when absolutely necessary; this avoids wasting effort preserving them when
-
+ * there is no risk that they will be altered, or when there is no need to
-The following APIs are provided to allow floating point resource sharing to be
+ * preserve their contents.
-enabled or disabled at run-time:
+ *
-
+ * The following APIs are provided to allow floating point resource sharing to
-	void fiber_float_enable  (nano_thread_id_t thread_id, unsigned int options)
+ * be enabled or disabled at run-time:
-	void task_float_enable   (nano_thread_id_t thread_id, unsigned int options)
+ *
-	void fiber_float_disable (nano_thread_id_t thread_id)
+ * 	void fiber_float_enable  (nano_thread_id_t thread_id, unsigned int options)
-	void task_float_disable  (nano_thread_id_t thread_id)
+ * 	void task_float_enable   (nano_thread_id_t thread_id, unsigned int options)
-
+ * 	void fiber_float_disable (nano_thread_id_t thread_id)
-The 'options' parameter is used to specify what non-integer capabilities are
+ * 	void task_float_disable  (nano_thread_id_t thread_id)
-being used.  The same options accepted by fiber_fiber_start() are used in the
+ *
-aforementioned APIs, namely USE_FP and USE_SSE.
+ * The 'options' parameter is used to specify what non-integer capabilities are
-
+ * being used.  The same options accepted by fiber_fiber_start() are used in the
-If the nanokernel has been built without SSE instruction support
+ * aforementioned APIs, namely USE_FP and USE_SSE.
-(CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
+ *
-
+ * If the nanokernel has been built without SSE instruction support
-If the nanokernel has been built without floating point resource
+ * (CONFIG_SSE), the system treats USE_SSE as if it was USE_FP.
-sharing support (CONFIG_FP_SHARING), the aforementioned APIs and
+ * 
-capabilities do not exist.
+ * If the nanokernel has been built without floating point resource sharing
-
+ * support (CONFIG_FP_SHARING), the aforementioned APIs and capabilities do not
-NOTE
+ * exist.
-It is possible for a single task or fiber to utilize floating instructions
+ *
-_without_ enabling the FP resource sharing feature.  Since no other task or
+ * NOTE
-fiber uses the FPU the FP registers won't change when the FP-capable task or
+ * It is possible for a single task or fiber to utilize floating instructions
-fiber isn't executing, meaning there is no need to save the registers.
+ * _without_ enabling the FP resource sharing feature.  Since no other task or
-
+ * fiber uses the FPU the FP registers won't change when the FP-capable task or
-WARNING
+ * fiber isn't executing, meaning there is no need to save the registers.
-The use of floating point instructions by ISRs is not supported by the kernel.
+ *
-
+ * WARNING
-INTERNAL
+ * The use of floating point instructions by ISRs is not supported by the
-If automatic enabling of floating point resource sharing _is not_ configured
+ * kernel.  
-the system leaves CR0[TS] = 0 for all tasks and fibers.  This means that any
+ *
-task or fiber can perform floating point operations at any time without causing
+ * INTERNAL
-an exception, and the system won't stop a task or fiber that shouldn't be
+ * If automatic enabling of floating point resource sharing _is not_ configured
-doing FP stuff from doing it.
+ * the system leaves CR0[TS] = 0 for all tasks and fibers.  This means that any
-
+ * task or fiber can perform floating point operations at any time without
-If automatic enabling of floating point resource sharing _is_ configured the
+ * causing an exception, and the system won't stop a task or fiber that
-system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to perform
+ * shouldn't be doing FP stuff from doing it.
-FP operations.  All other tasks and fibers have CR0[TS] = 1 so that an attempt
+ *
-to perform an FP operation will cause an exception, allowing the system to
+ * If automatic enabling of floating point resource sharing _is_ configured
-enable FP resource sharing on its behalf.
+ * the system leaves CR0[TS] = 0 only for tasks and fibers that are allowed to
-
+ * perform FP operations.  All other tasks and fibers have CR0[TS] = 1 so that
+ * an attempt to perform an FP operation will cause an exception, allowing the
+ * system to enable FP resource sharing on its behalf.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/x86/core/gdt.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module contains routines for updating the global descriptor table (GDT)
+ * This module contains routines for updating the global descriptor table (GDT)
-for the IA-32 architecture.
+ * for the IA-32 architecture.
  */
 
 #include <linker-defs.h>

arch/x86/core/intconnect.c

@@ -17,60 +17,61 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to manage asynchronous interrupts
+ * This module provides routines to manage asynchronous interrupts
-on the IA-32 architecture.
+ * on the IA-32 architecture.
-
+ * 
-This module provides the public routine irq_connect(), the private
+ * This module provides the public routine irq_connect(), the private
-routine _IntVecSet(), and the support routines _IntVecAlloc(),
+ * routine _IntVecSet(), and the support routines _IntVecAlloc(),
-_IntVecMarkAllocated() and _IntVecMarkFree().
+ * _IntVecMarkAllocated() and _IntVecMarkFree().
-
+ * 
-INTERNAL
+ * INTERNAL
-The _idt_base_address symbol is used to determine the base address of the IDT.
+ * The _idt_base_address symbol is used to determine the base address of the
-(It is generated by the linker script, and doesn't correspond to an actual
+ * IDT.  (It is generated by the linker script, and doesn't correspond to an
-global variable.)
+ * actual global variable.)
-
+ * 
-Interrupts are handled by an "interrupt stub" whose code is generated by the
+ * Interrupts are handled by an "interrupt stub" whose code is generated by the
-system itself.  The stub performs various actions before and after invoking
+ * system itself.  The stub performs various actions before and after invoking
-the application (or operating system) specific interrupt handler; for example,
+ * the application (or operating system) specific interrupt handler; for
-a thread context save is performed prior to invoking the interrupt handler.
+ * example, a thread context save is performed prior to invoking the interrupt
-
+ * handler.
-The IA-32 code that makes up a "full" interrupt stub is shown below.  A full
+ * 
-interrupt stub is one that is associated with an interrupt vector that requires
+ * The IA-32 code that makes up a "full" interrupt stub is shown below.  A full
-a "beginning of interrupt" (BOI) callout and an "end of interrupt" (EOI) callout
+ * interrupt stub is one that is associated with an interrupt vector that
-(both of which require a parameter).
+ * requires a "beginning of interrupt" (BOI) callout and an "end of interrupt"
-
+ * (EOI) callout (both of which require a parameter).
-  0x00   call    _IntEnt         /@ inform kernel of interrupt @/
+ *
-  Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
+ * 0x00   call    _IntEnt         /@ inform kernel of interrupt @/
-
+ * Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
-  0x05   pushl   $BoiParameter   /@ optional: push BOI handler parameter @/
+ *
-  Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
+ * 0x05   pushl   $BoiParameter   /@ optional: push BOI handler parameter @/
-
+ * Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
-  0x0a   call    BoiRoutine      /@ optional: callout to BOI rtn @/
+ *
-  Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
+ * 0x0a   call    BoiRoutine      /@ optional: callout to BOI rtn @/
-
+ * Machine code:  0xe8, 0x00, 0x00, 0x00, 0x00
-  0x0f   pushl   $IsrParameter   /@ push ISR parameter @/
+ *
-  Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
+ * 0x0f   pushl   $IsrParameter   /@ push ISR parameter @/
-
+ * Machine code:  0x68, 0x00, 0x00, 0x00, 0x00
-  0x14   call    IsrRoutine      /@ invoke ISR @/
+ *
-  Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
+ * 0x14   call    IsrRoutine      /@ invoke ISR @/
-
+ * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
-  0x19   pushl   $EoiParameter   /@ optional: push EOI handler parameter @/
+ *
-  Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
+ * 0x19   pushl   $EoiParameter   /@ optional: push EOI handler parameter @/
-
+ * Machine code: 0x68, 0x00, 0x00, 0x00, 0x00
-  0x1e   call    EoiRoutine      /@ optional: callout to EOI rtn @/
+ *
-  Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
+ * 0x1e   call    EoiRoutine      /@ optional: callout to EOI rtn @/
-
+ * Machine code: 0xe8, 0x00, 0x00, 0x00, 0x00
-  0x23   addl    $(4 * numParams), %esp    /@ pop parameters @/
+ *
-  Machine code: 0x83, 0xc4, (4 * numParams)
+ * 0x23   addl    $(4 * numParams), %esp    /@ pop parameters @/
-
+ * Machine code: 0x83, 0xc4, (4 * numParams)
-  0x26  jmp      _IntExit        /@ restore thread or reschedule @/
+ *
-  Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
+ * 0x26  jmp      _IntExit        /@ restore thread or reschedule @/
-
+ * Machine code: 0xe9, 0x00, 0x00, 0x00, 0x00
-NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE macro
+ *
-to reflect the maximum potential size of the interrupt stub (as shown above).
+ * NOTE: Be sure to update the arch specific definition of the _INT_STUB_SIZE
-The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h.
+ * macro to reflect the maximum potential size of the interrupt stub (as shown
-
+ * above).
+ * The _INT_STUB_SIZE macro is defined in include/nanokernel/x86/arch.h.
  */
 
 #ifndef CONFIG_NO_ISRS

arch/x86/core/offsets/offsets.c

@@ -17,20 +17,19 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module is responsible for the generation of the absolute symbols whose
+ * This module is responsible for the generation of the absolute symbols whose
-value represents the member offsets for various IA-32 nanokernel structures.
+ * value represents the member offsets for various IA-32 nanokernel structures.
-
+ *
-All of the absolute symbols defined by this module will be present in the
+ * All of the absolute symbols defined by this module will be present in the
-final microkernel or nanokernel ELF image (due to the linker's reference to
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
-the _OffsetAbsSyms symbol).
+ * the _OffsetAbsSyms symbol).
-
+ *
-INTERNAL
+ * INTERNAL
-It is NOT necessary to define the offset for every member of a structure.
+ * It is NOT necessary to define the offset for every member of a structure.
-Typically, only those members that are accessed by assembly language routines
+ * Typically, only those members that are accessed by assembly language routines
-are defined; however, it doesn't hurt to define all fields for the sake of
+ * are defined; however, it doesn't hurt to define all fields for the sake of
-completeness.
+ * completeness.
-
  */
 
 #include <gen_offset.h> /* located in kernel/arch/common/include */

arch/x86/core/strtask.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Intel-specific parts of start_task(). Only FP functionality currently.
+ * Intel-specific parts of start_task(). Only FP functionality currently.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/x86/core/sys_fatal_error_handler.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides the _SysFatalErrorHandler() routine which is common to
+ * This module provides the _SysFatalErrorHandler() routine which is common to
-supported platforms.
+ * supported platforms.
  */
 
 #include <nanokernel.h>

arch/x86/core/thread.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides core nanokernel fiber related primitives for the IA-32
+ * This module provides core nanokernel fiber related primitives for the IA-32
-processor architecture.
+ * processor architecture.
  */
 
 #ifdef CONFIG_MICROKERNEL
@@ -257,7 +257,8 @@ static void _new_thread_internal(char *pStackMem, unsigned stackSize,
 __asm__("\t.globl _thread_entry\n"
 	"\t.section .text\n"
 	"_thread_entry_wrapper:\n" /* should place this func .S file and use
-				     SECTION_FUNC */
+				    * SECTION_FUNC
+				    */
 	"\tmovl $0, (%esp)\n" /* zero initialEFLAGS location */
 	"\tjmp _thread_entry\n");
 #endif /* CONFIG_GDB_INFO */

arch/x86/include/advidle.h

@@ -16,11 +16,11 @@
  * limitations under the License.
  */
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file specifies the custom advanced idle management interface.
+ * This header file specifies the custom advanced idle management interface.
-All of the APIs declared here must be supplied by the custom advanced idle
+ * All of the APIs declared here must be supplied by the custom advanced idle
-management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc()
+ * management system, namely the _AdvIdleCheckSleep(), _AdvIdleFunc()
-and _AdvIdleStart() functions.
+ * and _AdvIdleStart() functions.
  */
 
 #ifndef __INCadvidle

arch/x86/include/gdt.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file provides definitions for the Global Descriptor Table (GDT) for the
+ * This file provides definitions for the Global Descriptor Table (GDT) for the
-IA-32 architecture.
+ * IA-32 architecture.
  */
 
 #ifndef _GDT_H

arch/x86/include/idtEnt.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file provides code for constructing an IA-32 interrupt descriptor.
+ * This header file provides code for constructing an IA-32 interrupt
-
+ * descriptor.
  */
 
 #ifndef _IDTENT_H

arch/x86/include/nano_private.h

@@ -17,17 +17,18 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file contains private nanokernel structures definitions and various other
+ * This file contains private nanokernel structures definitions and various
-definitions for the Intel Architecture 32 bit (IA-32) processor architecture.
+ * other definitions for the Intel Architecture 32 bit (IA-32) processor
-The header include/nanokernel.h contains the public nanokernel interface
+ * architecture.
-definitions, with include/arch/nanokernel/x86/arch.h supplying the
+ * The header include/nanokernel.h contains the public nanokernel interface
-IA-32 specific portions of the public nanokernel interface.
+ * definitions, with include/arch/nanokernel/x86/arch.h supplying the
-
+ * IA-32 specific portions of the public nanokernel interface.
-This file is also included by assembly language files which must #define
+ *
-_ASMLANGUAGE before including this header file.  Note that nanokernel assembly
+ * This file is also included by assembly language files which must #define
-source files obtains structure offset values via "absolute symbols" in the
+ * _ASMLANGUAGE before including this header file.  Note that nanokernel
-offsets.o module.
+ * assembly source files obtains structure offset values via "absolute symbols"
+ * in the offsets.o module.
  */
 
 #ifndef _NANO_PRIVATE_H
@@ -602,9 +603,10 @@ typedef struct s_coopFloatReg {
 
 typedef struct s_preempFloatReg {
 	union {
-		tFpRegSet fpRegs; /* threads with USE_FP utilize this format */
+		/* threads with USE_FP utilize this format */
-		tFpRegSetEx fpRegsEx; /* threads with USE_SSE utilize this
+		tFpRegSet fpRegs;
-					 format */
+		/* threads with USE_SSE utilize this format */
+		tFpRegSetEx fpRegsEx;
 	} floatRegsUnion;
 } tPreempFloatReg;
 
@@ -618,9 +620,8 @@ typedef struct s_preempFloatReg {
 struct tcs {
 	/*
 	 * Link to next thread in singly-linked thread list (such as
-	 * prioritized
+	 * prioritized list of runnable fibers, or list of fibers waiting on a
-	 * list of runnable fibers, or list of fibers waiting on a nanokernel
+	 * nanokernel FIFO).
-	 * FIFO).
 	 */
 
 	struct tcs *link;
@@ -656,8 +657,7 @@ struct tcs {
 	/*
 	 * Nested exception count to maintain setting of EXC_ACTIVE flag across
 	 * outermost exception.  EXC_ACTIVE is used by _Swap() lazy FP
-	 * save/restore
+	 * save/restore and by debug tools.
-	 * and by debug tools.
 	 */
 	unsigned excNestCount; /* nested exception count */
 #endif /* CONFIG_FP_SHARING || CONFIG_GDB_INFO */
@@ -673,19 +673,15 @@ struct tcs {
 	/*
 	 * The location of all floating point related structures/fields MUST be
 	 * located at the end of struct tcs.  This way only the
-	 *fibers/tasks
+	 * fibers/tasks that actually utilize non-integer capabilities need to
-	 * that actually utilize non-integer capabilities need to account for
+	 * account for the increased memory required for storing FP state when
-	 * the increased memory required for storing FP state when sizing
+	 * sizing stacks.
-	 *stacks.
 	 *
-	 * Given that stacks "grow down" on IA-32, and the TCS is
+	 * Given that stacks "grow down" on IA-32, and the TCS is located
-	 *located
 	 * at the start of a thread's "workspace" memory, the stacks of
-	 *fibers/tasks
+	 * fibers/tasks that do not utilize floating point instruction can
-	 * that do not utilize floating point instruction can effectively
+	 * effectively consume the memory occupied by the 'tCoopFloatReg' and
-	 *consume
+	 * 'tPreempFloatReg' structures without ill effect.
-	 * the memory occupied by the 'tCoopFloatReg' and 'tPreempFloatReg'
-	 * structures without ill effect.
 	 */
 
 	tCoopFloatReg coopFloatReg; /* non-volatile float register storage */
@@ -716,11 +712,10 @@ typedef struct s_NANO {
 	/*
 	 * A 'current_sse' field does not exist in addition to the 'current_fp'
 	 * field since it's not possible to divide the IA-32 non-integer
-	 * registers
+	 * registers into 2 distinct blocks owned by differing threads.  In
-	 * into 2 distinct blocks owned by differing threads.  In other words,
+	 * other words, given that the 'fxnsave/fxrstor' instructions
-	 * given that the 'fxnsave/fxrstor' instructions save/restore both the
+	 * save/restore both the X87 FPU and XMM registers, it's not possible
-	 * X87 FPU and XMM registers, it's not possible for a thread to only
+	 * for a thread to only "own" the XMM registers.
-	 * "own" the XMM registers.
 	 */
 
 	struct tcs *current_fp; /* thread (fiber or task) that owns the FP regs */
@@ -787,16 +782,16 @@ static inline void nanoArchInit(void)
 
 	/*
 	 * Forces the inclusion of the spurious interrupt handlers. If a
-	 * reference
+	 * reference isn't made then intconnect.o is never pulled in by the
-	 * isn't made then intconnect.o is never pulled in by the linker.
+	 * linker.
 	 */
 
 	_dummy_spurious_interrupt = &__isr___SpuriousIntHandler;
 
 	/*
 	 * Forces the inclusion of the exception vector stub code. If a
-	 * reference
+	 * reference isn't made then excstubs.o is never pulled in by the
-	 * isn't made then excstubs.o is never pulled in by the linker.
+	 * linker.
 	 */
 
 	_dummy_exception_vector_stub = &_ExcEnt;
@@ -811,8 +806,8 @@ static inline void nanoArchInit(void)
  * @param fiber pointer to fiber
  * @param value value to set as return value
  *
- * The register used to store the return value from a function call invocation is
+ * The register used to store the return value from a function call invocation
- * set to <value>.  It is assumed that the specified <fiber> is pending, and
+ * is set to <value>.  It is assumed that the specified <fiber> is pending, and
  * thus the fibers context is stored in its TCS.
  *
  * @return N/A

arch/x86/include/start_task_arch.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Intel-specific parts of start_task(). Only FP functionality currently.
+ * Intel-specific parts of start_task(). Only FP functionality currently.
  */
 
 #ifndef _START_TASK_ARCH__H_

arch/x86/include/swapstk.h

@@ -17,14 +17,14 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This file details the stack frame generated by _Swap() when it saves a task
+ * This file details the stack frame generated by _Swap() when it saves a task
-or fiber's context. This is specific to the IA-32 processor architecture.
+ * or fiber's context. This is specific to the IA-32 processor architecture.
-
+ *
-NOTE: _Swap() does not use this file as it uses the push instruction to save a
+ * NOTE: _Swap() does not use this file as it uses the push instruction to
-context. Changes to the file will not automatically be picked up by _Swap().
+ * save a context. Changes to the file will not automatically be picked up by
-Conversely, changes to _Swap() should be mirrored here if the stack frame is
+ * _Swap().  Conversely, changes to _Swap() should be mirrored here if the
-modified.
+ * stack frame is modified.
  */
 
 #ifndef _SWAPSTK_H

arch/x86/platforms/galileo/board.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for
+ * This header file is used to specify and describe board-level aspects for
-the 'galileo' platform.
+ * the 'galileo' platform.
  */
 
 #ifndef __INCboardh

arch/x86/platforms/galileo/galileo.c

@@ -17,12 +17,12 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level hardware
-for the galileo platform.
+ * for the galileo platform.
-
+ *
-Implementation Remarks:
+ * Implementation Remarks:
-Handlers for the secondary serial port have not been added.
+ * Handlers for the secondary serial port have not been added.
  */
 
 #include <nanokernel.h>

arch/x86/platforms/galileo/galileo_pinmux.c

@@ -552,8 +552,11 @@ uint8_t _galileo_set_pin(struct device *port, uint8_t pin, uint8_t func)
 
 	/* NUM_PIN_FUNCS being the number of alt functions */
 	mux_index = NUM_PIN_FUNCS * pin;
-	mux_index += func; /* functions are in numeric order, we can just
+	/*
-			      skip to the index needed */
+	 * functions are in numeric order, we can just skip to the index
+	 * needed
+	 */
+	mux_index += func;
 
 	enable = &_galileo_path[mux_index];
 

arch/x86/platforms/ia32/board.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for
+ * This header file is used to specify and describe board-level aspects for
-the 'ia32' platform.
+ * the 'ia32' platform.
  */
 
 #ifndef __INCboardh

arch/x86/platforms/ia32/ia32.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level hardware
-for the ia32 platform.
+ * for the ia32 platform.
  */
 
 #include <nanokernel.h>

arch/x86/platforms/ia32_pci/board.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header file is used to specify and describe board-level aspects for
+ * This header file is used to specify and describe board-level aspects for
-the 'ia32_pci' platform.
+ * the 'ia32_pci' platform.
  */
 
 #ifndef __INCboardh

arch/x86/platforms/ia32_pci/ia32_pci.c

@@ -17,12 +17,12 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides routines to initialize and support board-level hardware
+ * This module provides routines to initialize and support board-level hardware
-for the ia32_pci platform.
+ * for the ia32_pci platform.
-
+ *
-Implementation Remarks:
+ * Implementation Remarks:
-Handlers for the secondary serial port have not been added.
+ * Handlers for the secondary serial port have not been added.
  */
 
 #include <nanokernel.h>

drivers/adc/adc_ti_adc108s102.c

@@ -173,9 +173,11 @@ static void _ti_adc108s102_spi_cb(struct device *spi_dev,
 
 static void ti_adc108s102_enable(struct device *dev)
 {
-	/* There is nothing to be done. If there is no sampling going on,
+	/*
+	 * There is nothing to be done. If there is no sampling going on,
 	 * the chip will put itself on power-saving mode (that is because
-	 * SPI will release CS) */
+	 * SPI will release CS)
+	 */
 }
 
 static void ti_adc108s102_disable(struct device *dev)

drivers/bluetooth/uart.c

@@ -263,6 +263,7 @@ static void bt_uart_setup(struct device *uart, struct uart_init_info *info)
 	/* Drain the fifo */
 	while (uart_irq_rx_ready(uart)) {
 		unsigned char c;
+
 		uart_fifo_read(uart, &c, 1);
 	}
 

drivers/console/ipi_console_sender.c

@@ -29,8 +29,10 @@ static int consoleOut(int character)
 		return character;
 	}
 
-	/* We just stash the character into the id field and don't supply
+	/*
-	 * any extra data */
+	 * We just stash the character into the id field and don't supply
+	 * any extra data
+	 */
 	ipi_send(ipi_console_device, 1, character, NULL, 0);
 
 	return character;

drivers/console/uart_console.c

@@ -17,10 +17,10 @@
  */
 
 /*
-  DESCRIPTION
+ * DESCRIPTION
-
+ *
-  Serial console driver.
+ * Serial console driver.
-  Hooks into the printk and fputc (for printf) modules. Poll driven.
+ * Hooks into the printk and fputc (for printf) modules. Poll driven.
  */
 
 #include <nanokernel.h>
@@ -51,6 +51,7 @@ static int consoleIn(void)
 {
 #ifdef UART_CONSOLE_DEV
 	unsigned char c;
+
 	if (uart_poll_in(UART_CONSOLE_DEV, &c) < 0)
 		return EOF;
 	else

drivers/grove/lcd_rgb.c

@@ -302,8 +302,10 @@ int glcd_initialize(struct device *port)
 	 */
 
 
-	/* We're here!  Let's just make sure we've had enough time for the
+	/*
-	 * VDD to power on, so pause a little here, 30 ms min, so we go 50 */
+	 * We're here!  Let's just make sure we've had enough time for the
+	 * VDD to power on, so pause a little here, 30 ms min, so we go 50
+	 */
 	DBG("Grove LCD: delay 50 ms while the VDD powers on\n");
 	_sleep(50);
 

drivers/i2c/i2c_dw.c

@@ -64,9 +64,10 @@ static inline void _i2c_dw_data_ask(struct device *dev, uint8_t restart)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
+	uint32_t data;
+
 	volatile struct i2c_dw_registers * const regs =
 		(struct i2c_dw_registers *)rom->base_address;
-	uint32_t data;
 
 	/* No more bytes to request */
 	if (dw->request_bytes == 0) {
@@ -95,6 +96,7 @@ static void _i2c_dw_data_read(struct device *dev)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
+
 	volatile struct i2c_dw_registers * const regs =
 		(struct i2c_dw_registers *)rom->base_address;
 
@@ -123,9 +125,10 @@ static void _i2c_dw_data_send(struct device *dev)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
+	uint32_t data = 0;
+
 	volatile struct i2c_dw_registers * const regs =
 		(struct i2c_dw_registers *)rom->base_address;
-	uint32_t data = 0;
 
 	/* Nothing to send anymore, mask the interrupt */
 	if (dw->tx_len == 0) {
@@ -170,11 +173,12 @@ static inline void _i2c_dw_transfer_complete(struct device *dev)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
-	volatile struct i2c_dw_registers * const regs =
-		(struct i2c_dw_registers *)rom->base_address;
 	uint32_t cb_type = 0;
 	uint32_t value;
 
+	volatile struct i2c_dw_registers * const regs =
+		(struct i2c_dw_registers *)rom->base_address;
+
 	if (dw->state == I2C_DW_CMD_ERROR) {
 		cb_type = I2C_CB_ERROR;
 	} else if (dw->tx_buffer && !dw->tx_len) {
@@ -200,11 +204,11 @@ void i2c_dw_isr(struct device *port)
 {
 	struct i2c_dw_rom_config const * const rom = port->config->config_info;
 	struct i2c_dw_dev_config * const dw = port->driver_data;
+	uint32_t value = 0;
+
 	volatile struct i2c_dw_registers * const regs =
 		(struct i2c_dw_registers *)rom->base_address;
 
-	uint32_t value = 0;
-
 #if CONFIG_SHARED_IRQ
 	/* If using with shared IRQ, this function will be called
 	 * by the shared IRQ driver. So check here if the interrupt
@@ -390,11 +394,12 @@ static int _i2c_dw_transfer_init(struct device *dev,
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
-	volatile struct i2c_dw_registers * const regs =
-		(struct i2c_dw_registers *)rom->base_address;
 	uint32_t value = 0;
 	int ret;
 
+	volatile struct i2c_dw_registers * const regs =
+		(struct i2c_dw_registers *)rom->base_address;
+
 	dw->state |= I2C_DW_BUSY;
 	if (write_len > 0) {
 		dw->state |= I2C_DW_CMD_SEND;
@@ -440,9 +445,10 @@ static int i2c_dw_transfer(struct device *dev,
 			   uint16_t slave_address, uint32_t flags)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
+	int ret;
+
 	volatile struct i2c_dw_registers * const regs =
 		(struct i2c_dw_registers *)rom->base_address;
-	int ret;
 
 	/* First step, check if there is current activity */
 	if (regs->ic_status.bits.activity) {
@@ -481,12 +487,13 @@ static int i2c_dw_poll_transfer(struct device *dev,
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
-	volatile struct i2c_dw_registers * const regs =
-		(struct i2c_dw_registers *)rom->base_address;
 	uint32_t value = 0;
 	uint32_t start_time;
 	int ret = DEV_OK;
 
+	volatile struct i2c_dw_registers * const regs =
+		(struct i2c_dw_registers *)rom->base_address;
+
 	if (!regs->ic_con.bits.master_mode) {
 		/* Only acting as master is supported */
 		return DEV_INVALID_OP;
@@ -592,11 +599,12 @@ static int i2c_dw_runtime_configure(struct device *dev, uint32_t config)
 {
 	struct i2c_dw_rom_config const * const rom = dev->config->config_info;
 	struct i2c_dw_dev_config * const dw = dev->driver_data;
-	volatile struct i2c_dw_registers * const regs =
-		(struct i2c_dw_registers *)rom->base_address;
 	uint32_t	value = 0;
 	uint32_t	rc = DEV_OK;
 
+	volatile struct i2c_dw_registers * const regs =
+		(struct i2c_dw_registers *)rom->base_address;
+
 	dw->app_config.raw = config;
 
 	/* Make sure we have a supported speed for the DesignWare model */
@@ -758,6 +766,7 @@ int i2c_dw_initialize(struct device *port)
 {
 	struct i2c_dw_rom_config const * const rom = port->config->config_info;
 	struct i2c_dw_dev_config * const dev = port->driver_data;
+
 	volatile struct i2c_dw_registers *regs;
 
 	if (!i2c_dw_pci_setup(port)) {

drivers/interrupt_controller/i8259.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module disables the Intel 8259A PIC (Programmable Interrupt Controller)
+ * This module disables the Intel 8259A PIC (Programmable Interrupt Controller)
-to prevent it from generating spurious interrupts.
+ * to prevent it from generating spurious interrupts.
-*/
+ */
 
 
 #include <nanokernel.h>

drivers/interrupt_controller/loapic_intr.c

@@ -17,74 +17,74 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module is a driver for the local APIC/xAPIC (Advanced Programmable
+ * This module is a driver for the local APIC/xAPIC (Advanced Programmable
-Interrupt Controller) in P6 (PentiumPro, II, III) family processors
+ * Interrupt Controller) in P6 (PentiumPro, II, III) family processors
-and P7 (Pentium4) family processors.  The local APIC/xAPIC is included
+ * and P7 (Pentium4) family processors.  The local APIC/xAPIC is included
-in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors.
+ * in selected P6 (PentiumPro, II, III) and P7 (Pentium4) family processors.
-Beginning with the P6 family processors, the presence or absence of an
+ * Beginning with the P6 family processors, the presence or absence of an
-on-chip local APIC can be detected using the CPUID instruction.  When the
+ * on-chip local APIC can be detected using the CPUID instruction.  When the
-CPUID instruction is executed, bit 9 of the feature flags returned in the
+ * CPUID instruction is executed, bit 9 of the feature flags returned in the
-EDX register indicates the presence (set) or absence (clear) of an on-chip
+ * EDX register indicates the presence (set) or absence (clear) of an on-chip
-local APIC.
+ * local APIC.
-
+ *
-The local APIC performs two main functions for the processor:
+ * The local APIC performs two main functions for the processor:
- - It processes local external interrupts that the processor receives at its
+ *  - It processes local external interrupts that the processor receives at its
-   interrupt pins and local internal interrupts that software generates.
+ *    interrupt pins and local internal interrupts that software generates.
- - It communicates with an external IO APIC
+ *  - It communicates with an external IO APIC
-   chip.  The external IO APIC receives external interrupt events from
+ *    chip.  The external IO APIC receives external interrupt events from
-   peripheral and direct them to the local APIC.  The IO APIC is
+ *    peripheral and direct them to the local APIC.  The IO APIC is
-   part of Intel's system chip set.
+ *    part of Intel's system chip set.
-The local APIC controls the dispatching of interrupts (to its associated
+ * The local APIC controls the dispatching of interrupts (to its associated
-processor) that it receives either locally or from the IO APIC.  It provides
+ * processor) that it receives either locally or from the IO APIC.  It provides
-facilities for queuing, nesting and masking of interrupts.  It handles the
+ * facilities for queuing, nesting and masking of interrupts.  It handles the
-interrupt delivery protocol with its local processor and accesses to APIC
+ * interrupt delivery protocol with its local processor and accesses to APIC
-registers.
+ * registers.
-A timer on the local APIC allows local generation of interrupts, and
+ * A timer on the local APIC allows local generation of interrupts, and
-local interrupt pins permit local reception of processor-specific interrupts.
+ * local interrupt pins permit local reception of processor-specific interrupts.
-The local APIC can be disabled and used in conjunction with a standard 8259A
+ * The local APIC can be disabled and used in conjunction with a standard 8259A
-style interrupt controller.  Disabling the local APIC can be done in hardware
+ * style interrupt controller.  Disabling the local APIC can be done in hardware
-for the Pentium processors or in software for the P6 and P7 (Pentium4) family
+ * for the Pentium processors or in software for the P6 and P7 (Pentium4) family
-processors.
+ * processors.
-
+ *
-The local APIC in the Pentium4 processors (called the xAPIC) is an extension
+ * The local APIC in the Pentium4 processors (called the xAPIC) is an extension
-of the local APIC found in the P6 family processors.  The primary difference
+ * of the local APIC found in the P6 family processors.  The primary difference
-between the APIC architecture and xAPIC architecture is that with Pentium4
+ * between the APIC architecture and xAPIC architecture is that with Pentium4
-processors, the local xAPICs and IO xAPIC communicate with one another through
+ * processors, the local xAPICs and IO xAPIC communicate with one another
-the processors system bus; whereas, with the P6 family processors, communication
+ * through the processors system bus; whereas, with the P6 family processors,
-between the local APICs and the IO APIC is handled through a dedicated 3-wire
+ * communication between the local APICs and the IO APIC is handled through a
-APIC bus.  Also, some of the architectural features of the local APIC have been
+ * dedicated 3-wire APIC bus.  Also, some of the architectural features of the
-extended and/or modified in the local xAPIC.
+ * local APIC have been extended and/or modified in the local xAPIC.
-
+ *
-This driver contains three routines for use.  They are:
+ * This driver contains three routines for use.  They are:
-_loapic_init() initializes the Local APIC for the interrupt mode chosen.
+ * _loapic_init() initializes the Local APIC for the interrupt mode chosen.
-_loapic_enable()/disable() enables / disables the Local APIC.
+ * _loapic_enable()/disable() enables / disables the Local APIC.
-
+ *
-Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT.
+ * Local APIC is used in the Virtual Wire Mode: delivery mode ExtINT.
-
+ *
-Virtual Wire Mode is one of three interrupt modes defined by the MP
+ * Virtual Wire Mode is one of three interrupt modes defined by the MP
-specification.  In this mode, interrupts are generated by the 8259A equivalent
+ * specification.  In this mode, interrupts are generated by the 8259A
-PICs (if present) and delivered to the Boot Strap Processor by
+ * equivalent PICs (if present) and delivered to the Boot Strap Processor by
-the local APIC that is programmed to act as a "virtual Wire"; that
+ * the local APIC that is programmed to act as a "virtual Wire"; that
-is, the local APIC is logically indistinguishable from a hardware
+ * is, the local APIC is logically indistinguishable from a hardware
-connection.  This is a uniprocessor compatibility mode.
+ * connection.  This is a uniprocessor compatibility mode.
-
+ *
-The local and IO APICs support interrupts in the range of 32 to 255.
+ * The local and IO APICs support interrupts in the range of 32 to 255.
-Interrupt priority is implied by its vector, according to the following
+ * Interrupt priority is implied by its vector, according to the following
-relationship:  "priority = vector / 16".
+ * relationship:  "priority = vector / 16".
-Here the quotient is rounded down to the nearest integer value to determine
+ * Here the quotient is rounded down to the nearest integer value to determine
-the priority, with 1 being the lowest and 15 is the highest.  Because vectors
+ * the priority, with 1 being the lowest and 15 is the highest.  Because vectors
-0 through 31 are reserved for exclusive use by the processor, the priority of
+ * 0 through 31 are reserved for exclusive use by the processor, the priority of
-user defined interrupts range from 2 to 15.  A value of 15 in the Interrupt
+ * user defined interrupts range from 2 to 15.  A value of 15 in the Interrupt
-Class field of the Task Priority Register (TPR) will mask off all interrupts,
+ * Class field of the Task Priority Register (TPR) will mask off all interrupts,
-which require interrupt service.
+ * which require interrupt service.
-The P6 family processor's local APIC includes an in-service entry and a holding
+ * The P6 family processor's local APIC includes an in-service entry and a
-entry for each priority level.  To avoid losing interrupts, software should
+ * holding entry for each priority level.  To avoid losing interrupts, software
-allocate no more than 2 interrupt vectors per priority.  The Pentium4 processor
+ * should allocate no more than 2 interrupt vectors per priority.  The Pentium4
-expands this support of all acceptance of two interrupts per vector rather than
+ * processor expands this support of all acceptance of two interrupts per vector
-per priority level.
+ * rather than per priority level.
-
+ * 
-INCLUDE FILES: loapic.h
+ * INCLUDE FILES: loapic.h
  */
 
 #include <nanokernel.h>

drivers/interrupt_controller/system_apic.c

@@ -143,8 +143,10 @@ int _SysIntVecAlloc(unsigned int irq, unsigned int priority,
 		} else {
 			_loapic_int_vec_set(irq - CONFIG_IOAPIC_NUM_RTES, vector);
 
-			/* specify that the EOI handler in loApicIntr.c driver
+			/*
-			 * be invoked */
+			 * specify that the EOI handler in loApicIntr.c driver
+			 * be invoked
+			 */
 
 			*eoiRtn = (NANO_EOI_GET_FUNC)_loapic_eoi;
 			*eoiParamRequired = 0;

drivers/pci/pci.c

@@ -17,67 +17,66 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Module implements routines for PCI bus initialization and query.
+ * Module implements routines for PCI bus initialization and query.
-
+ *
-USAGE
+ * USAGE
-To use the driver, the platform must define:
+ * To use the driver, the platform must define:
-- Numbers of BUSes:
+ * - Numbers of BUSes:
-    - PCI_BUS_NUMBERS;
+ *     - PCI_BUS_NUMBERS;
-- Register addresses:
+ * - Register addresses:
-    - PCI_CTRL_ADDR_REG;
+ *     - PCI_CTRL_ADDR_REG;
-    - PCI_CTRL_DATA_REG;
+ *     - PCI_CTRL_DATA_REG;
-- pci_pin2irq() - the routine that converts the PCI interrupt pin
+ * - pci_pin2irq() - the routine that converts the PCI interrupt pin
-  number to IRQ number.
+ *   number to IRQ number.
-
+ *
-About scanning the PCI buses:
+ * About scanning the PCI buses:
-At every new usage of this API, the code should call pci_bus_scan_init().
+ * At every new usage of this API, the code should call pci_bus_scan_init().
-It should own a struct pci_dev_info, filled in with the parameters it is
+ * It should own a struct pci_dev_info, filled in with the parameters it is
-interested to look for: class and/or vendor_id/device_id.
+ * interested to look for: class and/or vendor_id/device_id.
-
+ *
-Then it can loop on pci_bus_scan() providing a pointer on that structure.
+ * Then it can loop on pci_bus_scan() providing a pointer on that structure.
-Such function can be called as long as it returns 1. At every successful
+ * Such function can be called as long as it returns 1. At every successful
-return of pci_bus_scan() it means the provided structure pointer will have
+ * return of pci_bus_scan() it means the provided structure pointer will have
-been updated with the current scan result which the code might be interested
+ * been updated with the current scan result which the code might be interested
-in. On pci_bus_scan() returning 0, the code should discard the result and
+ * in. On pci_bus_scan() returning 0, the code should discard the result and
-stop calling pci_bus_scan(). If it wants to retrieve the result, it will
+ * stop calling pci_bus_scan(). If it wants to retrieve the result, it will
-have to restart the procedure all over again.
+ * have to restart the procedure all over again.
-
+ *
-EXAMPLE
+ * EXAMPLE
-struct pci_dev_info info = {
+ * struct pci_dev_info info = {
-	.class = PCI_CLASS_COMM_CTLR
+ * 	.class = PCI_CLASS_COMM_CTLR
-};
+ * };
-
+ *
-pci_bus_scan_init();
+ * pci_bus_scan_init();
-
+ *
-while (pci_bus_scan(&info) {
+ * while (pci_bus_scan(&info) {
-	// do something with "info" which holds a valid result, i.e. some
+ * 	// do something with "info" which holds a valid result, i.e. some
-	// device information matching the PCI class PCI_CLASS_COMM_CTLR
+ * 	// device information matching the PCI class PCI_CLASS_COMM_CTLR
-}
+ * }
-
+ *
-INTERNALS
+ * INTERNALS
-The whole logic runs around a structure: struct lookup_data, which exists
+ * The whole logic runs around a structure: struct lookup_data, which exists
-on one instanciation called 'lookup'.
+ * on one instanciation called 'lookup'.
-Such structure is used for 2 distinct roles:
+ * Such structure is used for 2 distinct roles:
-- to match devices the caller is looking for
+ * - to match devices the caller is looking for
-- to loop on PCI bus, devices, function and BARs
+ * - to loop on PCI bus, devices, function and BARs
-
+ *
-The search criterias are the class and/or the vendor_id/device_id of a PCI
+ * The search criterias are the class and/or the vendor_id/device_id of a PCI
-device. The caller first initializes the lookup structure by calling
+ * device. The caller first initializes the lookup structure by calling
-pci_bus_scan_init(), which will reset the search criterias as well as the
+ * pci_bus_scan_init(), which will reset the search criterias as well as the
-loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
+ * loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
-the lookup structure will store the search criterias. Then the loop starts.
+ * the lookup structure will store the search criterias. Then the loop starts.
-For each bus it will run through each device on which it will loop on each
+ * For each bus it will run through each device on which it will loop on each
-function and BARs, as long as the criterias does not match or until it hit
+ * function and BARs, as long as the criterias does not match or until it hit
-the limit of bus/dev/functions to scan.
+ * the limit of bus/dev/functions to scan.
-
+ * 
-On a successful match, it will stop the loop, fill in the caller's
+ * On a successful match, it will stop the loop, fill in the caller's
-pci_dev_info structure with the found device information, and return 1.
+ * pci_dev_info structure with the found device information, and return 1.
-Hopefully, the lookup structure still remembers where it stopped and the
+ * Hopefully, the lookup structure still remembers where it stopped and the
-original search criterias. Thus, when the caller asks to scan again for
+ * original search criterias. Thus, when the caller asks to scan again for
-a possible result next, the loop will restart where it stopped.
+ * a possible result next, the loop will restart where it stopped.
-That will work as long as there are relevant results found.
+ * That will work as long as there are relevant results found.
-
  */
 
 #include <nanokernel.h>

drivers/pci/pci_config.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-This module implements the PCI config space access functions
+ * This module implements the PCI config space access functions
-
+ *
  */
 
 #include <nanokernel.h>

drivers/pci/pci_interface.c

@@ -17,10 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-This module implements the PCI H/W access functions.
+ * This module implements the PCI H/W access functions.
-
  */
 
 #include <nanokernel.h>

drivers/pci/pci_legacy_bridge.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Module provides routines for utilizing the PCI legacy bridge, including
+ * Module provides routines for utilizing the PCI legacy bridge, including
-detection of the bridge and using the bridge to configure the routing between
+ * detection of the bridge and using the bridge to configure the routing between
-PCI interrupt pins and IRQs.
+ * PCI interrupt pins and IRQs.
-*/
+ */
 #include <nanokernel.h>
 #include <arch/cpu.h>
 

drivers/random/rand32_timer.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides a non-random implementation of sys_rand32_get(), which is
+ * This module provides a non-random implementation of sys_rand32_get(), which
-not meant to be used in a final product as a truly random number generator. It
+ * is not meant to be used in a final product as a truly random number
-was provided to allow testing on a platform that does not (yet) provide a
+ * generator. It was provided to allow testing on a platform that does not (yet)
-random number generator.
+ * provide a random number generator.
  */
 
 #include <drivers/rand32.h>

drivers/random/rand32_timestamp.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module provides a non-random implementation of sys_rand32_get(), which is
+ * This module provides a non-random implementation of sys_rand32_get(), which
-not meant to be used in a final product as a truly random number generator. It
+ * is not meant to be used in a final product as a truly random number
-was provided to allow testing on a platform that does not (yet) provide a
+ * generator. It was provided to allow testing on a platform that does not (yet)
-random number generator.
+ * provide a random number generator.
  */
 
 #include <nanokernel.h>

drivers/serial/stellarisUartDrv.c

@@ -163,15 +163,19 @@ static void baudrate_set(struct device *dev,
 	div = (16 * baudrate);
 	rem = sys_clk_freq_hz % div;
 
-	/* floating part of baud rate (LM3S6965 p.433), equivalent to
+	/*
-	 * [float part of (SYSCLK / div)] * 64 + 0.5 */
+	 * floating part of baud rate (LM3S6965 p.433), equivalent to
+	 * [float part of (SYSCLK / div)] * 64 + 0.5
+	 */
 	brdf = ((((rem * 64) << 1) / div) + 1) >> 1;
 
 	/* integer part of baud rate (LM3S6965 p.433) */
 	brdi = sys_clk_freq_hz / div;
 
-	/* those registers are 32-bit, but the reserved bits should be
+	/*
-	 * preserved */
+	 * those registers are 32-bit, but the reserved bits should be
+	 * preserved
+	 */
 	uart->ibrd = (uint16_t)(brdi & 0xffff); /* 16 bits */
 	uart->fbrd = (uint8_t)(brdf & 0x3f);    /* 6 bits */
 }

drivers/simple/uart.c

@@ -82,6 +82,7 @@ static void uart_simple_setup(struct device *uart, struct uart_init_info *info)
 	/* Drain the fifo */
 	while (uart_irq_rx_ready(uart)) {
 		unsigned char c;
+
 		uart_fifo_read(uart, &c, 1);
 	}
 

drivers/timer/arcv2_timer0.c

@@ -17,12 +17,13 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module implements a kernel device driver for the ARCv2 processor timer 0
+ * This module implements a kernel device driver for the ARCv2 processor timer 0
-and provides the standard "system clock driver" interfaces.
+ * and provides the standard "system clock driver" interfaces.
-
+ *
-\INTERNAL IMPLEMENTATION DETAILS
+ * \INTERNAL IMPLEMENTATION DETAILS
-The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero counter.
+ * The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero
+ * counter.
  */
 
 #include <nanokernel.h>

drivers/timer/cortex_m_systick.c

@@ -17,24 +17,24 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module implements the kernel's CORTEX-M ARM's systick device driver.
+ * This module implements the kernel's CORTEX-M ARM's systick device driver.
-It provides the standard kernel "system clock driver" interfaces.
+ * It provides the standard kernel "system clock driver" interfaces.
-
+ * 
-The driver utilizes systick to provide kernel ticks.
+ * The driver utilizes systick to provide kernel ticks.
-
+ * 
-\INTERNAL IMPLEMENTATION DETAILS
+ * \INTERNAL IMPLEMENTATION DETAILS
-The systick device provides a 24-bit clear-on-write, decrementing,
+ * The systick device provides a 24-bit clear-on-write, decrementing,
-wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
+ * wrap-on-zero counter. Only edge sensitive triggered interrupt is supported.
-
+ * 
-\INTERNAL PACKAGING DETAILS
+ * \INTERNAL PACKAGING DETAILS
-The systick device driver is part of the microkernel in both a monolithic kernel
+ * The systick device driver is part of the microkernel in both a monolithic
-system and a split kernel system; it is not included in the nanokernel portion
+ * kernel system and a split kernel system; it is not included in the
-of a split kernel.
+ * nanokernel portion of a split kernel.
-
+ *
-The device driver is also part of a nanokernel-only system, but omits more
+ * The device driver is also part of a nanokernel-only system, but omits more
-complex capabilities (such as tickless idle support) that are only used in
+ * complex capabilities (such as tickless idle support) that are only used in
-conjunction with a microkernel.
+ * conjunction with a microkernel.
  */
 
 #include <nanokernel.h>
@@ -477,20 +477,19 @@ void _timer_idle_enter(int32_t ticks /* system ticks */
 	if ((ticks == -1) || (ticks > max_system_ticks)) {
 		/*
 		 * We've been asked to fire the timer so far in the future that
-		 * the
+		 * the required count value would not fit in the 24-bit reload
-		 * required count value would not fit in the 24-bit reload
 		 * register.
 		 * Instead, we program for the maximum programmable interval
-		 * minus one
+		 * minus one system tick to prevent overflow when the left over
-		 * system tick to prevent overflow when the left over count read
+		 * count read earlier is added.
-		 * earlier
-		 * is added.
 		 */
 		idle_original_count += max_load_value - default_load_value;
 		idle_original_ticks = max_system_ticks - 1;
 	} else {
-		/* leave one tick of buffer to have to time react when coming
+		/*
-		 * back */
+		 * leave one tick of buffer to have to time react when coming
+		 * back
+		 */
 		idle_original_ticks = ticks - 1;
 		idle_original_count += idle_original_ticks * default_load_value;
 	}

drivers/timer/hpet.c

@@ -17,37 +17,41 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module implements a kernel device driver for the Intel High Precision
+ * This module implements a kernel device driver for the Intel High Precision
-Event Timer (HPET) device, and provides the standard "system clock driver"
+ * Event Timer (HPET) device, and provides the standard "system clock driver"
-interfaces.
+ * interfaces.
-
+ * 
-The driver utilizes HPET timer0 to provide kernel ticks.
+ * The driver utilizes HPET timer0 to provide kernel ticks.
-
+ * 
-\INTERNAL IMPLEMENTATION DETAILS
+ * \INTERNAL IMPLEMENTATION DETAILS
-The HPET device driver makes no assumption about the initial state of the HPET,
+ * The HPET device driver makes no assumption about the initial state of the
-and explicitly puts the device into a reset-like state. It also assumes that
+ * HPET, and explicitly puts the device into a reset-like state. It also assumes
-the main up counter never wraps around to 0 during the lifetime of the system.
+ * that the main up counter never wraps around to 0 during the lifetime of the
-
+ * system.
-The platform can configure the HPET to use level rather than the default edge
+ *
-sensitive interrupts by enabling the following configuration parameters:
+ * The platform can configure the HPET to use level rather than the default edge
-CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW
+ * sensitive interrupts by enabling the following configuration parameters:
-
+ * CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW
-When not configured to support tickless idle timer0 is programmed in periodic
+ *
-mode so it automatically generates a single interrupt per kernel tick interval.
+ * When not configured to support tickless idle timer0 is programmed in periodic
-
+ * mode so it automatically generates a single interrupt per kernel tick
-When configured to support tickless idle timer0 is programmed in one-shot mode.
+ * interval.
-When the CPU is not idling the timer interrupt handler sets the timer to expire
+ *
-when the next kernel tick is due, waits for this to occur, and then repeats
+ * When configured to support tickless idle timer0 is programmed in one-shot
-this "ad infinitum". When the CPU begins idling the timer driver reprograms
+ * mode.  When the CPU is not idling the timer interrupt handler sets the timer
-the expiry time for the timer (thereby overriding the previously scheduled
+ * to expire when the next kernel tick is due, waits for this to occur, and then
-timer interrupt) and waits for the timer to expire or for a non-timer interrupt
+ * repeats this "ad infinitum". When the CPU begins idling the timer driver
-to occur. When the CPU ceases idling the driver determines how many complete
+ * reprograms the expiry time for the timer (thereby overriding the previously
-ticks have elapsed, reprograms the timer so that it expires on the next tick,
+ * scheduled timer interrupt) and waits for the timer to expire or for a
-and announces the number of elapsed ticks (if any) to the microkernel.
+ * non-timer interrupt to occur. When the CPU ceases idling the driver
-
+ * determines how many complete ticks have elapsed, reprograms the timer so that
-In a nanokernel-only system this device driver omits more complex capabilities
+ * it expires on the next tick, and announces the number of elapsed ticks (if
-(such as tickless idle support) that are only used with a microkernel.
+ * any) to the microkernel.
+ *
+ * In a nanokernel-only system this device driver omits more complex
+ * capabilities (such as tickless idle support) that are only used with a
+ * microkernel.
  */
 
 #include <nanokernel.h>
@@ -111,21 +115,21 @@ extern struct nano_stack _k_command_stack;
  */
 
 #define _HPET_GENERAL_INT_STATUS ((volatile uint32_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_INT_STATUS_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_INT_STATUS_REG))
 
 #define _HPET_MAIN_COUNTER_VALUE ((volatile uint64_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
 #define _HPET_MAIN_COUNTER_LSW ((volatile uint32_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
 #define _HPET_MAIN_COUNTER_MSW ((volatile uint32_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG + 0x4))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG + 0x4))
 
 #define _HPET_TIMER0_CONFIG_CAPS ((volatile uint64_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_CONFIG_CAPS_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_CONFIG_CAPS_REG))
 #define _HPET_TIMER0_COMPARATOR ((volatile uint64_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_COMPARATOR_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_COMPARATOR_REG))
 #define _HPET_TIMER0_FSB_INT_ROUTE ((volatile uint64_t *) \
-			(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_FSB_INT_ROUTE_REG))
+		(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_FSB_INT_ROUTE_REG))
 
 /* general capabilities register macros */
 
@@ -193,14 +197,14 @@ extern uint32_t _hw_irq_to_c_handler_latency;
 
 extern int32_t _sys_idle_elapsed_ticks;
 
-static uint32_t __noinit counter_load_value; /* main counter units
+/* main counter units per system tick */
-							    per system tick */
+static uint32_t __noinit counter_load_value;
-static uint64_t counter_last_value =
+/* counter value for most recent tick */
-	0; /* counter value for most recent tick */
+static uint64_t counter_last_value = 0;
-static int32_t programmed_ticks =
+/* # ticks timer is programmed for */
-	1; /* # ticks timer is programmed for */
+static int32_t programmed_ticks = 1;
-static int stale_irq_check =
+/* is stale interrupt possible? */
-	0; /* is stale interrupt possible? */
+static int stale_irq_check = 0;
 
 /**
  *
@@ -389,23 +393,22 @@ void _timer_idle_exit(void)
 		/*
 		 * update # of ticks since last tick event was announced,
 		 * so that this value is available to ISRs that run before the
-		 * timer
+		 * timer interrupt handler runs (which is unlikely, but could
-		 * interrupt handler runs (which is unlikely, but could happen)
+		 * happen)
 		 */
 
 		_sys_idle_elapsed_ticks = programmed_ticks - 1;
 
 		/*
 		 * Announce elapsed ticks to the microkernel. Note we are
-		 * guaranteed
+		 * guaranteed that the timer ISR will execute first before the
-		 * that the timer ISR will execute first before the tick event
+		 * tick event is serviced.
-		 * is
-		 * serviced.
 		 */
 		_sys_clock_tick_announce();
 
 		/* timer interrupt handler reprograms the timer for the next
-		 * tick */
+		 * tick
+		 */
 
 		return;
 	}
@@ -422,9 +425,8 @@ void _timer_idle_exit(void)
 	 * the microkernel, which gets informed of the correct number of elapsed
 	 * ticks when the following tick finally occurs; however, any ISRs that
 	 * access _sys_idle_elapsed_ticks to determine the current time may be
-	 *misled
+	 * misled during the (very brief) interval before the tick-in-progress
-	 * during the (very brief) interval before the tick-in-progress finishes
+	 * finishes and the following tick begins
-	 * and the following tick begins
 	 */
 
 	elapsedTicks =
@@ -458,10 +460,8 @@ void _timer_idle_exit(void)
 
 	/*
 	 * Any elapsed ticks have been accounted for so simply set the
-	 * programmed
+	 * programmed ticks to 1 since the timer has been programmed to fire on
-	 * ticks to 1 since the timer has been programmed to fire on the next
+	 * the next tick boundary.
-	 * tick
-	 * boundary.
 	 */
 
 	programmed_ticks = 1;
@@ -491,8 +491,7 @@ int _sys_clock_driver_init(struct device *device)
 
 	/*
 	 * Initial state of HPET is unknown, so put it back in a reset-like
-	 * state
+	 * state (i.e. set main counter to 0 and disable interrupts)
-	 * (i.e. set main counter to 0 and disable interrupts)
 	 */
 
 	*_HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
@@ -588,9 +587,9 @@ int _sys_clock_driver_init(struct device *device)
 	 */
 
 	/*
-	 * HPET timers IRQ field is 5 bits wide, and hence, can support only IRQ's
+	 * HPET timers IRQ field is 5 bits wide, and hence, can support only
-	 * up to 31. Some platforms, however, use IRQs greater than 31. In this
+	 * IRQ's up to 31. Some platforms, however, use IRQs greater than 31. In
-	 * case program leaves the IRQ fields blank.
+	 * this case program leaves the IRQ fields blank.
 	 */
 
 	*_HPET_TIMER0_CONFIG_CAPS =
@@ -609,8 +608,7 @@ int _sys_clock_driver_init(struct device *device)
 
 	/*
 	 * Although the stub has already been "connected", the vector number
-	 * still
+	 * still has to be programmed into the interrupt controller.
-	 * has to be programmed into the interrupt controller.
 	 */
 
 	IRQ_CONFIG(hpet, CONFIG_HPET_TIMER_IRQ, 0);

drivers/timer/loapic_timer.c

@@ -132,8 +132,8 @@ IRQ_CONNECT_STATIC(loapic, CONFIG_LOAPIC_TIMER_IRQ,
 			CONFIG_LOAPIC_TIMER_IRQ_PRIORITY,
 			_timer_int_handler, 0);
 
-static uint32_t __noinit cycles_per_tick; /* computed counter 0
+/* computed counter 0 initial count value */
-							  initial count value */
+static uint32_t __noinit cycles_per_tick;
 static uint32_t accumulated_cycle_count;
 
 #if defined(TIMER_SUPPORTS_TICKLESS)
@@ -596,13 +596,13 @@ int _sys_clock_driver_init(struct device *device)
 
 	/*
 	 * Although the stub has already been "connected", the vector number
-	 * still
+	 * still has to be programmed into the interrupt controller.
-	 * has to be programmed into the interrupt controller.
 	 */
 	IRQ_CONFIG(loapic, CONFIG_LOAPIC_TIMER_IRQ, 0);
 
 	/* Everything has been configured. It is now safe to enable the
-	 * interrupt */
+	 * interrupt
+	 */
 	irq_enable(CONFIG_LOAPIC_TIMER_IRQ);
 
 	return 0;

drivers/timer/sys_clock_init.c

@@ -17,14 +17,15 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Initializing the timer driver is done in this module to reduce code duplication.
+ * Initializing the timer driver is done in this module to reduce code
-Although both nanokernel and microkernel systems initialize the timer driver at
+ * duplication.  Although both nanokernel and microkernel systems initialize
-the same point, the two systems differ in when the system can begin to process
+ * the timer driver at the same point, the two systems differ in when the system
-system clock ticks.  A nanokernel system can process system clock ticks once
+ * can begin to process system clock ticks.  A nanokernel system can process
-the driver has initialized.  However, in a microkernel system all system clock
+ * system clock ticks once the driver has initialized.  However, in a
-ticks are deferred (and stored on the kernel server command stack) until the
+ * microkernel system all system clock ticks are deferred (and stored on the
-kernel server fiber starts and begins processing any queued ticks.
+ * kernel server command stack) until the kernel server fiber starts and begins
+ * processing any queued ticks.
 */
 
 #include <nanokernel.h>
@@ -32,6 +33,6 @@ kernel server fiber starts and begins processing any queued ticks.
 #include <drivers/system_timer.h>
 
 DECLARE_DEVICE_INIT_CONFIG(sys_clock, "sys_clock",
-						   _sys_clock_driver_init, NULL);
+			   _sys_clock_driver_init, NULL);
 
 nano_late_init(sys_clock, NULL);

include/arch/arc/arch.h

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header contains the ARC specific nanokernel interface.  It is
+ * This header contains the ARC specific nanokernel interface.  It is
-included by the nanokernel interface architecture-abstraction header
+ * included by the nanokernel interface architecture-abstraction header
-(nanokernel/cpu.h)
+ * (nanokernel/cpu.h)
  */
 
 #ifndef _ARC_ARCH__H_

include/arch/arc/v2/aux_regs.h

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-
+ *
-Definitions for auxiliary registers.
+ * Definitions for auxiliary registers.
  */
 
 #ifndef _ARC_V2_AUX_REGS__H_

include/arch/arc/v2/error.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARC-specific nanokernel error handling interface. Included by ARC/arch.h.
+ * ARC-specific nanokernel error handling interface. Included by ARC/arch.h.
  */
 
 #ifndef _ARCH_ARC_V2_ERROR_H_

include/arch/arc/v2/exc.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARC-specific nanokernel exception handling interface. Included by ARC/arch.h.
+ * ARC-specific nanokernel exception handling interface. Included by ARC/arch.h.
  */
 
 #ifndef _ARCH_ARC_V2_EXC_H_

include/arch/arc/v2/ffs.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARC-specific nanokernel ffs interface. Included by ARC/arch.h.
+ * ARC-specific nanokernel ffs interface. Included by ARC/arch.h.
  */
 
 #ifndef _ARCH_ARC_V2_FFS_H_

include/arch/arc/v2/misc.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h.
+ * ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h.
  */
 
 #ifndef _ARCH_ARC_V2_MISC_H_

include/arch/arm/arch.h

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This header contains the ARM specific nanokernel interface.  It is
+ * This header contains the ARM specific nanokernel interface.  It is
-included by the nanokernel interface architecture-abstraction header
+ * included by the nanokernel interface architecture-abstraction header
-(nanokernel/cpu.h)
+ * (nanokernel/cpu.h)
  */
 
 #ifndef _ARM_ARCH__H_

include/arch/arm/cortex_m/error.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
+ * ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
  */
 
 #ifndef _ARCH_ARM_CORTEXM_ERROR_H_

include/arch/arm/cortex_m/exc.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARM-specific nanokernel exception handling interface. Included by ARM/arch.h.
+ * ARM-specific nanokernel exception handling interface. Included by ARM/arch.h.
  */
 
 #ifndef _ARCH_ARM_CORTEXM_EXC_H_

include/arch/arm/cortex_m/gdb_stub.h

@@ -17,11 +17,11 @@
  */
 
 /*
-  DESCRIPTION
+ * DESCRIPTION
-
+ *
-  Prep work done when entering exceptions consists of saving the callee-saved
+ * Prep work done when entering exceptions consists of saving the callee-saved
-  registers before they get used by exception handlers, and recording the fact
+ * registers before they get used by exception handlers, and recording the fact
-  that we are running in an exception.
+ * that we are running in an exception.
  */
 
 #ifndef _GDB_STUB__H_

include/arch/arm/cortex_m/irq.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
+ * ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
  */
 
 #ifndef _ARCH_ARM_CORTEXM_IRQ_H_

include/arch/arm/cortex_m/memory_map-m3-m4.h

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module contains definitions for the memory map parts specific to the
+ * This module contains definitions for the memory map parts specific to the
-CORTEX-M3/M4 series of processors. It is included by nanokernel/ARM/memory_map.h
+ * CORTEX-M3/M4 series of processors. It is included by
-
+ * nanokernel/ARM/memory_map.h
  */
 
 #ifndef _MEMORY_MAP_M3_M4__H_

include/arch/arm/cortex_m/memory_map.h

@@ -17,10 +17,9 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-This module contains definitions for the memory map of the CORTEX-M series of
+ * This module contains definitions for the memory map of the CORTEX-M series of
-processors.
+ * processors.
-
  */
 
 #ifndef _CORTEXM_MEMORY_MAP__H_

include/arch/arm/cortex_m/misc.h

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h.
+ * ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h.
  */
 
 #ifndef _ARCH_ARM_CORTEXM_MISC_H_

include/arch/arm/cortex_m/nvic.h

@@ -17,21 +17,21 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Provide an interface to the Nested Vectored Interrupt Controller found on
+ * Provide an interface to the Nested Vectored Interrupt Controller found on
-ARM Cortex-M processors.
+ * ARM Cortex-M processors.
-
+ *
-The API does not account for all possible usages of the NVIC, only the
+ * The API does not account for all possible usages of the NVIC, only the
-functionalities needed by the kernel.
+ * functionalities needed by the kernel.
-
+ *
-The same effect can be achieved by directly writing in the registers of the
+ * The same effect can be achieved by directly writing in the registers of the
-NVIC, with the layout available from scs.h, using the __scs.nvic data
+ * NVIC, with the layout available from scs.h, using the __scs.nvic data
-structure (or hardcoded values), but these APIs are less error-prone,
+ * structure (or hardcoded values), but these APIs are less error-prone,
-especially for registers with multiple instances to account for potentially
+ * especially for registers with multiple instances to account for potentially
-240 interrupt lines. If access to a missing functionality is needed, this is
+ * 240 interrupt lines. If access to a missing functionality is needed, this is
-the way to implement it.
+ * the way to implement it.
-
+ *
-Supports up to 240 IRQs and 256 priority levels.
+ * Supports up to 240 IRQs and 256 priority levels.
  */
 
 #ifndef _NVIC_H_

include/arch/arm/cortex_m/scb.h

@@ -17,22 +17,23 @@
  */
 
 /*
-DESCRIPTION
+ * DESCRIPTION
-Provide an interface to the System Control Block found on ARM Cortex-M
+ * Provide an interface to the System Control Block found on ARM Cortex-M
-processors.
+ * processors.
-
+ *
-The API does not account for all possible usages of the SCB, only the
+ * The API does not account for all possible usages of the SCB, only the
-functionalities needed by the kernel. It does not contain NVIC
+ * functionalities needed by the kernel. It does not contain NVIC
-functionalities either: these can be found in nvic.h. MPU functionalities
+ * functionalities either: these can be found in nvic.h. MPU functionalities
-are not implemented.
+ * are not implemented.
-
+ *
-The same effect can be achieved by directly writing in the registers of the
+ * The same effect can be achieved by directly writing in the registers of the
-SCB, with the layout available from scs.h, using the __scs.scb data
+ * SCB, with the layout available from scs.h, using the __scs.scb data
-structure (or hardcoded values), but the APIs found here are less error-prone,
+ * structure (or hardcoded values), but the APIs found here are less
-especially for registers with multiple instances to account for 16 exceptions.
+ * error-prone, especially for registers with multiple instances to account
-
+ * for 16 exceptions.
-If access to a missing functionality is needed, directly writing to the
+ *
-registers is the way to implement it.
+ * If access to a missing functionality is needed, directly writing to the
+ * registers is the way to implement it.
  */
 
 #ifndef _SCB__H_