checkpatch: warning - block_comment_style

Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>

arch/arm/core/cortex_m/nmi.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
-Provides a boot time handler that simply hangs in a sleep loop, and a run time
-handler that resets the CPU. Also provides a mechanism for hooking a custom
-run time handler.
+ * DESCRIPTION
+ * Provides a boot time handler that simply hangs in a sleep loop, and a run
+ * time handler that resets the CPU. Also provides a mechanism for hooking a
+ * custom run time handler.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/prep_c.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
-
-Initialization of full C support: zero the .bss, copy the .data if XIP,
-call _Cstart().
-
-Stack is available in this module, but not the global data/bss until their
-initialization is performed.
+ * DESCRIPTION
+ *
+ * Initialization of full C support: zero the .bss, copy the .data if XIP,
+ * call _Cstart().
+ *
+ * Stack is available in this module, but not the global data/bss until their
+ * initialization is performed.
  */
 
 #include <stdint.h>

arch/arm/core/cortex_m/scb.c

@@ -17,11 +17,11 @@
  */
 
 /*
-DESCRIPTION
-
-Most of the SCB interface consists of simple bit-flipping methods, and is
-implemented as inline functions in scb.h. This module thus contains only data
-definitions and more complex routines, if needed.
+ * DESCRIPTION
+ *
+ * Most of the SCB interface consists of simple bit-flipping methods, and is
+ * implemented as inline functions in scb.h. This module thus contains only data
+ * definitions and more complex routines, if needed.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/scs.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
-Most of the SCS interface consists of simple bit-flipping methods, and is
-implemented as inline functions in scs.h. This module thus contains only data
-definitions and more complex routines, if needed.
+ * DESCRIPTION
+ * Most of the SCS interface consists of simple bit-flipping methods, and is
+ * implemented as inline functions in scs.h. This module thus contains only data
+ * definitions and more complex routines, if needed.
  */
 
 #include <nanokernel.h>

arch/arm/core/cortex_m/vector_table.h

@@ -17,15 +17,15 @@
  */
 
 /*
-DESCRIPTION
-
-Definitions for the boot vector table.
-
-System exception handler names all have the same format:
-
-  __<exception name with underscores>
-
-No other symbol has the same format, so they are easy to spot.
+ * DESCRIPTION
+ *
+ * Definitions for the boot vector table.
+ *
+ * System exception handler names all have the same format:
+ *
+ *   __<exception name with underscores>
+ *
+ * No other symbol has the same format, so they are easy to spot.
  */
 
 #ifndef _VECTOR_TABLE__H_

arch/arm/core/fatal.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
-This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
+ * DESCRIPTION
+ * This module provides the _NanoFatalErrorHandler() routine for ARM Cortex-M.
  */
 
 #include <toolchain.h>

arch/arm/core/fault.c

@@ -17,8 +17,8 @@
  */
 
 /*
-DESCRIPTION
-Common fault handler for ARM Cortex-M processors.
+ * DESCRIPTION
+ * Common fault handler for ARM Cortex-M processors.
  */
 
 #include <toolchain.h>

arch/arm/core/fiber_abort.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
-The ARM Cortex-M architecture provides its own fiber_abort() to deal with
-different CPU modes (handler vs thread) when a fiber aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
-call _Swap() (which triggers a service call), but when in handler mode, the
-CPU must exit handler mode to cause the context switch, and thus must queue
-the PendSV exception.
+ * DESCRIPTION
+ * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
+ * different CPU modes (handler vs thread) when a fiber aborts. When its entry
+ * point returns or when it aborts itself, the CPU is in thread mode and must
+ * call _Swap() (which triggers a service call), but when in handler mode, the
+ * CPU must exit handler mode to cause the context switch, and thus must queue
+ * the PendSV exception.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/arm/core/gdb_stub_irq_vector_table.c

@@ -17,10 +17,10 @@
  */
 
 /*
-DESCRIPTION
-When GDB is enabled, the static IRQ vector table needs to install the
-_irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
-user-installed ISRs.
+ * DESCRIPTION
+ * When GDB is enabled, the static IRQ vector table needs to install the
+ * _irq_vector_table_entry_with_gdb_stub stub to do some work before calling the
+ * user-installed ISRs.
  */
 
 #include <toolchain.h>

arch/arm/core/irq_init.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
-The ARM Cortex-M architecture provides its own fiber_abort() to deal with
-different CPU modes (handler vs thread) when a fiber aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
-call _Swap() (which triggers a service call), but when in handler mode, the
-CPU must exit handler mode to cause the context switch, and thus must queue
-the PendSV exception.
+ * DESCRIPTION
+ * The ARM Cortex-M architecture provides its own fiber_abort() to deal with
+ * different CPU modes (handler vs thread) when a fiber aborts. When its entry
+ * point returns or when it aborts itself, the CPU is in thread mode and must
+ * call _Swap() (which triggers a service call), but when in handler mode, the
+ * CPU must exit handler mode to cause the context switch, and thus must queue
+ * the PendSV exception.
  */
 
 #include <toolchain.h>

arch/arm/core/irq_manage.c

@@ -17,10 +17,11 @@
  */
 
 /*
-DESCRIPTION
-
-Interrupt management: enabling/disabling and dynamic ISR connecting/replacing.
-SW_ISR_TABLE_DYNAMIC has to be enabled for connecting ISRs at runtime.
+ * DESCRIPTION
+ *
+ * Interrupt management: enabling/disabling and dynamic ISR
+ * connecting/replacing.  SW_ISR_TABLE_DYNAMIC has to be enabled for
+ * connecting ISRs at runtime.
  */
 
 #include <nanokernel.h>

arch/arm/core/offsets/offsets.c

@@ -17,21 +17,20 @@
  */
 
 /*
-DESCRIPTION
-This module is responsible for the generation of the absolute symbols whose
-value represents the member offsets for various ARM nanokernel
-structures.
-
-All of the absolute symbols defined by this module will be present in the
-final microkernel or nanokernel ELF image (due to the linker's reference to
-the _OffsetAbsSyms symbol).
-
-INTERNAL
-It is NOT necessary to define the offset for every member of a structure.
-Typically, only those members that are accessed by assembly language routines
-are defined; however, it doesn't hurt to define all fields for the sake of
-completeness.
-
+ * DESCRIPTION
+ * This module is responsible for the generation of the absolute symbols whose
+ * value represents the member offsets for various ARM nanokernel
+ * structures.
+ *
+ * All of the absolute symbols defined by this module will be present in the
+ * final microkernel or nanokernel ELF image (due to the linker's reference to
+ * the _OffsetAbsSyms symbol).
+ *
+ * INTERNAL
+ * It is NOT necessary to define the offset for every member of a structure.
+ * Typically, only those members that are accessed by assembly language routines
+ * are defined; however, it doesn't hurt to define all fields for the sake of
+ * completeness.
  */
 
 #include <gen_offset.h>

arch/arm/core/sys_fatal_error_handler.c

@@ -17,8 +17,9 @@
  */
 
 /*
-DESCRIPTION
-This module provides the _SysFatalErrorHandler() routine for Cortex-M platforms.
+ * DESCRIPTION
+ * This module provides the _SysFatalErrorHandler() routine for Cortex-M
+ * platforms.
  */
 
 #include <nanokernel.h>

arch/arm/core/task_abort.c

@@ -17,13 +17,13 @@
  */
 
 /*
-DESCRIPTION
-The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
-different CPU modes (handler vs thread) when a task aborts. When its entry
-point returns or when it aborts itself, the CPU is in thread mode and must
-call the equivalent of task_abort(<self>), but when in handler mode, the
-CPU must queue a packet to _k_server(), then exit handler mode to queue the
-PendSV exception and cause the immediate context switch to _k_server.
+ * DESCRIPTION
+ * The ARM Cortex-M architecture provides its own _TaskAbort() to deal with
+ * different CPU modes (handler vs thread) when a task aborts. When its entry
+ * point returns or when it aborts itself, the CPU is in thread mode and must
+ * call the equivalent of task_abort(<self>), but when in handler mode, the
+ * CPU must queue a packet to _k_server(), then exit handler mode to queue the
+ * PendSV exception and cause the immediate context switch to _k_server.
  */
 
 #ifdef CONFIG_MICROKERNEL

arch/arm/core/thread.c

@@ -17,9 +17,9 @@
  */
 
 /*
-DESCRIPTION
-Core nanokernel fiber related primitives for the ARM Cortex-M processor
-architecture.
+ * DESCRIPTION
+ * Core nanokernel fiber related primitives for the ARM Cortex-M processor
+ * architecture.
  */
 
 #include <nanokernel.h>
@@ -57,8 +57,9 @@ static ALWAYS_INLINE void _thread_monitor_init(struct tcs *tcs /* thread */
 	unsigned int key;
 
 	/*
-	 * Add the newly initialized thread to head of the list of threads.  This
-	 * singly linked list of threads maintains ALL the threads in the system:
+	 * Add the newly initialized thread to head of the list of threads.
+	 * This singly linked list of threads maintains ALL the threads in the
+	 * system:
 	 * both tasks and fibers regardless of whether they are runnable.
 	 */