From d9571f641258429d7955b3c8621353e88af0da79 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 18 Mar 2025 08:59:59 +0800 Subject: [PATCH] soc: ITE: ilm: Enable instruction memory for it51xxx series Enable instruction memory for ITE it51xxx series. Signed-off-by: Tim Lin --- dts/riscv/ite/it51xxx.dtsi | 5 ++ soc/ite/ec/it51xxx/CMakeLists.txt | 2 + soc/ite/ec/it51xxx/Kconfig | 14 +++++ soc/ite/ec/it51xxx/chip_chipregs.h | 15 +++++- soc/ite/ec/it51xxx/ilm.h | 16 ++++++ soc/ite/ec/it51xxx/ilm_wrapper.c | 19 +++++++ soc/ite/ec/it51xxx/linker.ld | 22 ++++++++ soc/ite/ec/it51xxx/soc.c | 3 ++ soc/ite/ec/it8xxx2/chip_chipregs.h | 3 ++ soc/ite/ec/it8xxx2/ilm.c | 82 +++++++++++++----------------- 10 files changed, 132 insertions(+), 49 deletions(-) create mode 100644 soc/ite/ec/it51xxx/ilm.h create mode 100644 soc/ite/ec/it51xxx/ilm_wrapper.c diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index 7379eab7af3..22f3236628e 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -61,6 +61,11 @@ reg = <0x800000 DT_SIZE_K(128)>; }; + ilm: ilm@f01040 { + compatible = "ite,it8xxx2-ilm"; + reg = <0xf01040 3>; /* SCAR0 */ + }; + gpiogcr: gpio-gcr@f01600 { compatible = "ite,it51xxx-gpiogcr"; reg = <0x00f01600 0x100>; diff --git a/soc/ite/ec/it51xxx/CMakeLists.txt b/soc/ite/ec/it51xxx/CMakeLists.txt index f9ea7b8d84e..94ad7b7a0df 100644 --- a/soc/ite/ec/it51xxx/CMakeLists.txt +++ b/soc/ite/ec/it51xxx/CMakeLists.txt @@ -1,6 +1,8 @@ zephyr_sources(soc.c vector.S) zephyr_include_directories(.) +zephyr_sources_ifdef(CONFIG_SOC_IT51XXX_USE_ILM ../it8xxx2/ilm.c ilm_wrapper.c) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "SoC Linker script ${SOC_NAME}" ) diff --git a/soc/ite/ec/it51xxx/Kconfig b/soc/ite/ec/it51xxx/Kconfig index 35923428dca..1b910657b69 100644 --- a/soc/ite/ec/it51xxx/Kconfig +++ b/soc/ite/ec/it51xxx/Kconfig @@ -30,4 +30,18 @@ config SOC_IT51XXX_CPU_IDLE_GATING gated by individual drivers. When this option is disabled, CPU idle mode is always permitted. +config SOC_IT51XXX_USE_ILM + bool + default y + help + If enabled, Instruction Local Memory (ILM) will be configured to execute + code placed in the .__ram_code section out of RAM. This consumes RAM in + blocks of 4 kilobytes, but performance of code in ILM is much more + predictable than executing from Flash directly, and some code (such as code + that writes to the internal Flash) must execute out of RAM. + +config ILM_MAX_SIZE + int "ILM Size in kB" + default 4 + endif # SOC_SERIES_IT51XXX diff --git a/soc/ite/ec/it51xxx/chip_chipregs.h b/soc/ite/ec/it51xxx/chip_chipregs.h index 7111de3f166..a1c853d3cd8 100644 --- a/soc/ite/ec/it51xxx/chip_chipregs.h +++ b/soc/ite/ec/it51xxx/chip_chipregs.h @@ -69,6 +69,9 @@ struct smfi_it51xxx_regs { #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) /* Enable EC-indirect page program command */ #define IT51XXX_SMFI_MASK_ECINDPP BIT(3) +/* 0x42: Scratch SRAM 0 address high byte */ +#define SCARH_ENABLE BIT(7) +#define SCARH_ADDR_BIT19 BIT(3) /** * @@ -269,8 +272,14 @@ struct gctrl_it51xxx_regs { volatile uint8_t reserved_21_37[23]; /* 0x38: Special Control 9 */ volatile uint8_t GCTRL_SPCTRL9; - /* 0x39-0x84: reserved_39_84 */ - volatile uint8_t reserved_39_84[76]; + /* 0x39-0x46: reserved_39_46 */ + volatile uint8_t reserved_39_46[14]; + /* 0x47: Scratch SRAM0 Base Address */ + volatile uint8_t GCTRL_SCR0BAR; + /* 0x48: Scratch ROM 0 Size */ + volatile uint8_t GCTRL_SCR0SZR; + /* 0x49-0x84: reserved_49_84 */ + volatile uint8_t reserved_49_84[60]; /* 0x85: Chip ID Byte 1 */ volatile uint8_t GCTRL_ECHIPID1; /* 0x86: Chip ID Byte 2 */ @@ -298,6 +307,8 @@ struct gctrl_it51xxx_regs { #define IT51XXX_GCTRL_LRSIPGWR BIT(0) /* 0x38: Special Control 9 */ #define IT51XXX_GCTRL_ALTIE BIT(4) +/* 0x48: Scratch ROM 0 Size */ +#define IT51XXX_GCTRL_SCRSIZE_4K 0x03 /* Alias gpio_ite_ec_regs to gpio_it51xxx_regs for compatibility */ #define gpio_ite_ec_regs gpio_it51xxx_regs diff --git a/soc/ite/ec/it51xxx/ilm.h b/soc/ite/ec/it51xxx/ilm.h new file mode 100644 index 00000000000..40f3e57d110 --- /dev/null +++ b/soc/ite/ec/it51xxx/ilm.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* Places code in the section that gets mapped into ILM */ +#define __soc_ram_code __attribute__((section(".__ram_code"))) + +#ifndef _ASMLANGUAGE +void custom_reset_instr_cache(void); +bool it8xxx2_is_ilm_configured(void); + +#endif diff --git a/soc/ite/ec/it51xxx/ilm_wrapper.c b/soc/ite/ec/it51xxx/ilm_wrapper.c new file mode 100644 index 00000000000..be62c791777 --- /dev/null +++ b/soc/ite/ec/it51xxx/ilm_wrapper.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +void __soc_ram_code custom_reset_instr_cache(void) +{ + struct gctrl_it51xxx_regs *const gctrl_regs = GCTRL_IT51XXX_REGS_BASE; + + /* I-Cache tag sram reset */ + gctrl_regs->GCTRL_SCR0BAR = 0; + /* Make sure the I-Cache is reset */ + __asm__ volatile("fence.i" ::: "memory"); +} diff --git a/soc/ite/ec/it51xxx/linker.ld b/soc/ite/ec/it51xxx/linker.ld index c1000628324..3556f90ff4f 100644 --- a/soc/ite/ec/it51xxx/linker.ld +++ b/soc/ite/ec/it51xxx/linker.ld @@ -179,6 +179,17 @@ SECTIONS *(".text.*") *(.gnu.linkonce.t.*) #include + . = ALIGN(0x1000); + /* Mapping base address must be 4k-aligned */ + __ilm_flash_start = .; + /* Specially-tagged functions in SoC sources */ + KEEP(*(.__ram_code)) + *(.__ram_code.*) + __ilm_flash_end = .; + /* ILM mapping is always a multiple of 4k size; ensure following + * sections won't incorrectly redirect to RAM. */ + . = ALIGN(0x1000); + } GROUP_LINK_IN(ROMABLE_REGION) __text_region_end = .; @@ -242,6 +253,17 @@ SECTIONS GROUP_START(RAMABLE_REGION) . = RAM_BASE; + + /* Claim RAM for ILM mappings; must be 4k-aligned and each mapping is 4k in size */ + SECTION_PROLOGUE(ilm_ram,(NOLOAD),ALIGN(0x1000)) + { + __ilm_ram_start = .; + . += __ilm_flash_end - __ilm_flash_start; + __ilm_ram_end = .; + /* Aligning 4k ensures ILM doesn't overwritte RAM. */ + . = ALIGN(0x1000); + } GROUP_LINK_IN(RAMABLE_REGION) + _image_ram_start = .; /* Located in generated directory. This file is populated by the * zephyr_linker_sources() Cmake function. diff --git a/soc/ite/ec/it51xxx/soc.c b/soc/ite/ec/it51xxx/soc.c index 2f3c435228a..d91714bf7b2 100644 --- a/soc/ite/ec/it51xxx/soc.c +++ b/soc/ite/ec/it51xxx/soc.c @@ -105,6 +105,9 @@ void soc_prep_hook(void) /* Scratch ROM0 is 4kb size */ gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K; + /* Scratch ROM0 is 4kb size */ + gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K; + /* bit4: wake up CPU if it is in low power mode and an interrupt is pending. */ gctrl_regs->GCTRL_SPCTRL9 |= IT51XXX_GCTRL_ALTIE; diff --git a/soc/ite/ec/it8xxx2/chip_chipregs.h b/soc/ite/ec/it8xxx2/chip_chipregs.h index 9b0d8960cad..d7c9c1ca27e 100644 --- a/soc/ite/ec/it8xxx2/chip_chipregs.h +++ b/soc/ite/ec/it8xxx2/chip_chipregs.h @@ -922,6 +922,9 @@ struct smfi_it8xxx2_regs { /* Host RAM Window x Write Protect Enable (All protected) */ #define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4)) +/* 0x42: Scratch SRAM 0 address high byte */ +#define SCARH_ADDR_BIT19 BIT(7) +#define SCARH_ENABLE BIT(3) /** * diff --git a/soc/ite/ec/it8xxx2/ilm.c b/soc/ite/ec/it8xxx2/ilm.c index f586e38dd45..39be48c0634 100644 --- a/soc/ite/ec/it8xxx2/ilm.c +++ b/soc/ite/ec/it8xxx2/ilm.c @@ -3,6 +3,7 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include @@ -46,9 +47,6 @@ BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must #define ILM_NODE DT_NODELABEL(ilm) -#define SCARH_ENABLE BIT(3) -#define SCARH_ADDR_BIT19 BIT(7) - /* * SCAR registers contain 20-bit addresses in three registers, with one set * of SCAR registers for each ILM block that may be configured. @@ -158,51 +156,41 @@ static int it8xxx2_ilm_init(const struct device *dev) #define SCAR_REG(n) (volatile struct scar_reg *)DT_REG_ADDR_BY_IDX(ILM_NODE, n) static const struct ilm_config ilm_config = { - .scar_regs = { - /* SCAR0 SRAM 4KB */ - SCAR_REG(0), - SCAR_REG(1), - SCAR_REG(2), - SCAR_REG(3), - SCAR_REG(4), - SCAR_REG(5), - SCAR_REG(6), - SCAR_REG(7), - SCAR_REG(8), - SCAR_REG(9), - SCAR_REG(10), - SCAR_REG(11), - SCAR_REG(12), - SCAR_REG(13), - SCAR_REG(14), - /* - * Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX - * maximum ILM size are 60KB, the ILM size of other varients - * are equal to the SRAM size. - */ + .scar_regs = {/* SCAR0 SRAM 4KB */ + SCAR_REG(0), +#if (CONFIG_ILM_MAX_SIZE > 4) + SCAR_REG(1), SCAR_REG(2), SCAR_REG(3), SCAR_REG(4), SCAR_REG(5), SCAR_REG(6), + SCAR_REG(7), SCAR_REG(8), SCAR_REG(9), SCAR_REG(10), SCAR_REG(11), + SCAR_REG(12), SCAR_REG(13), SCAR_REG(14), +#endif +/* + * Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX + * maximum ILM size are 60KB, the ILM size of other variants + * are equal to the SRAM size. + */ #if (CONFIG_ILM_MAX_SIZE == 256) - /* SCAR15 SRAM 4KB */ - SCAR_REG(15), - /* SCAR16 SRAM 16KB */ - SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), - /* SCAR17 SRAM 16KB */ - SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), - /* SCAR18 SRAM 16KB */ - SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), - /* SCAR19 SRAM 16KB */ - SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), - /* SCAR20 SRAM 32KB */ - SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), - SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), - /* SCAR21 SRAM 32KB */ - SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), - SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), - /* SCAR22 SRAM 32KB */ - SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), - SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), - /* SCAR23 SRAM 32KB */ - SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), - SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23) + /* SCAR15 SRAM 4KB */ + SCAR_REG(15), + /* SCAR16 SRAM 16KB */ + SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), + /* SCAR17 SRAM 16KB */ + SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), + /* SCAR18 SRAM 16KB */ + SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), + /* SCAR19 SRAM 16KB */ + SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), + /* SCAR20 SRAM 32KB */ + SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), + SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), + /* SCAR21 SRAM 32KB */ + SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), + SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), + /* SCAR22 SRAM 32KB */ + SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), + SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), + /* SCAR23 SRAM 32KB */ + SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), + SCAR_REG(23), SCAR_REG(23), SCAR_REG(23) #endif }}; BUILD_ASSERT(ARRAY_SIZE(ilm_config.scar_regs) * ILM_BLOCK_SIZE == KB(CONFIG_ILM_MAX_SIZE),