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tests/drivers/clock_control: stm32u5: Rework to explicitly test HCLK

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Instead of testing SysClockFreq setting, we should instead check HCLK
setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
counterpart (core clock freq) and takes AHB prescaler setting into
account.

Additionally, update one test configuration to explicitly verify AHB
prescaler is correctly taken into account by clock driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-04-06 11:33:25 +02:00 • committed by Carles Cufí
commit d8f5ef725f
3 changed files with 12 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_80.overlay → tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay
View file

@ -20,9 +20,9 @@
};
&pll1 {
div-m = <2>;
div-m = <1>;
mul-n = <40>;
div-q = <2>;
div-q = <1>;
div-r = <1>;
clocks = <&clk_msis>;
status = "okay";
@ -30,8 +30,8 @@
&rcc {
clocks = <&pll1>;
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;

14
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/test_stm32_clock_configuration.c
View file

@ -11,15 +11,15 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(test);
static void test_sysclk_freq(void)
static void test_hclk_freq(void)
{
uint32_t soc_sys_clk_freq;
uint32_t soc_hclk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
soc_hclk_freq = HAL_RCC_GetHCLKFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq,
"Expected hclk_freq: %d. Actual hclk_freq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq);
}
static void test_sysclk_src(void)
@ -80,7 +80,7 @@ static void test_pll_src(void)
void test_main(void)
{
ztest_test_suite(test_stm32_syclck_config,
ztest_unit_test(test_sysclk_freq),
ztest_unit_test(test_hclk_freq),
ztest_unit_test(test_sysclk_src),
ztest_unit_test(test_pll_src)
);

4
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
View file

@ -4,8 +4,8 @@ common:
tests:
drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_80:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_80.overlay"
drivers.stm32_clock_configuration.u5.pll_msis_hab_2_80:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_80.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40: