From d8f5ef725f9cccfbc71643ef125e093fcefe9782 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Wed, 6 Apr 2022 11:33:25 +0200 Subject: [PATCH] tests/drivers/clock_control: stm32u5: Rework to explicitly test HCLK Instead of testing SysClockFreq setting, we should instead check HCLK setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC counterpart (core clock freq) and takes AHB prescaler setting into account. Additionally, update one test configuration to explicitly verify AHB prescaler is correctly taken into account by clock driver. Signed-off-by: Erwan Gouriou --- ...l_msis_80.overlay => pll_msis_ahb_2_80.overlay} | 6 +++--- .../src/test_stm32_clock_configuration.c | 14 +++++++------- .../stm32u5_core/testcase.yaml | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) rename tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/{pll_msis_80.overlay => pll_msis_ahb_2_80.overlay} (84%) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_80.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay similarity index 84% rename from tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_80.overlay rename to tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay index d3aa904ade3..d9c41e27f62 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_80.overlay +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay @@ -20,9 +20,9 @@ }; &pll1 { - div-m = <2>; + div-m = <1>; mul-n = <40>; - div-q = <2>; + div-q = <1>; div-r = <1>; clocks = <&clk_msis>; status = "okay"; @@ -30,8 +30,8 @@ &rcc { clocks = <&pll1>; + ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */ clock-frequency = ; - ahb-prescaler = <1>; apb1-prescaler = <1>; apb2-prescaler = <1>; apb3-prescaler = <1>; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/test_stm32_clock_configuration.c index 351f60c7e2b..3a2af7b5469 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/src/test_stm32_clock_configuration.c @@ -11,15 +11,15 @@ #include LOG_MODULE_REGISTER(test); -static void test_sysclk_freq(void) +static void test_hclk_freq(void) { - uint32_t soc_sys_clk_freq; + uint32_t soc_hclk_freq; - soc_sys_clk_freq = HAL_RCC_GetSysClockFreq(); + soc_hclk_freq = HAL_RCC_GetHCLKFreq(); - zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq, - "Expected sysclockfreq: %d. Actual sysclockfreq: %d", - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq); + zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq, + "Expected hclk_freq: %d. Actual hclk_freq: %d", + CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq); } static void test_sysclk_src(void) @@ -80,7 +80,7 @@ static void test_pll_src(void) void test_main(void) { ztest_test_suite(test_stm32_syclck_config, - ztest_unit_test(test_sysclk_freq), + ztest_unit_test(test_hclk_freq), ztest_unit_test(test_sysclk_src), ztest_unit_test(test_pll_src) ); diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml index 7a965df8bf6..5298b3416da 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml @@ -4,8 +4,8 @@ common: tests: drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160: extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay" - drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_80: - extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_80.overlay" + drivers.stm32_clock_configuration.u5.pll_msis_hab_2_80: + extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_80.overlay" drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160: extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay" drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40: