diff --git a/dts/arm/nucleo_l476rg.dts b/dts/arm/nucleo_l476rg.dts index c0b03ab2a00..04aff092acb 100644 --- a/dts/arm/nucleo_l476rg.dts +++ b/dts/arm/nucleo_l476rg.dts @@ -16,19 +16,9 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpioa 5 0>; - }; - }; -}; - -&clk_hse { - clock-frequency = <8000000>; }; &usart2 { + baud-rate = <115200>; status = "ok"; }; diff --git a/dts/arm/olimexino_stm32.dts b/dts/arm/olimexino_stm32.dts index dc47f33868d..5e78de632a0 100644 --- a/dts/arm/olimexino_stm32.dts +++ b/dts/arm/olimexino_stm32.dts @@ -16,22 +16,9 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; }; - - leds { - compatible = "gpio-leds"; - green { - gpios = <&gpioa 5 0>; - }; - yellow { - gpios = <&gpioa 1 0>; - }; - }; -}; - -&clk_hse { - clock-frequency = <72000000>; }; &usart1 { + baud-rate = <115200>; status = "ok"; }; diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h index 899ee42cdc3..76a04c484ba 100644 --- a/dts/arm/st/mem.h +++ b/dts/arm/st/mem.h @@ -4,10 +4,26 @@ #if defined(CONFIG_SOC_STM32F103XB) #define DT_FLASH_SIZE 0x20000 #define DT_SRAM_SIZE 0x5000 +#elif defined(CONFIG_SOC_STM32F103XE) +#define DT_FLASH_SIZE 0x80000 +#define DT_SRAM_SIZE 0x10000 +#elif defined(CONFIG_SOC_STM32F107XC) +#define DT_FLASH_SIZE 0x40000 +#define DT_SRAM_SIZE 0x10000 +#elif defined(CONFIG_SOC_STM32F334X8) +#define DT_FLASH_SIZE 0x10000 +#define DT_SRAM_SIZE 0x3000 +#elif defined(CONFIG_SOC_STM32F373XC) +#define DT_FLASH_SIZE 0x40000 +#define DT_SRAM_SIZE 0x8000 +#elif defined(CONFIG_SOC_STM32F401XE) || defined(CONFIG_SOC_STM32F411XE) +#define DT_FLASH_SIZE 0x80000 +#define DT_SRAM_SIZE 0x18000 #elif defined(CONFIG_SOC_STM32L476XX) #define DT_FLASH_SIZE 0x100000 #define DT_SRAM_SIZE 0x18000 #else +#error "Flash and RAM sizes not defined for this chip" #endif #endif /* __DT_BINDING_ST_MEM_H */ diff --git a/dts/arm/st/stm32f103xb.dtsi b/dts/arm/st/stm32f103xb.dtsi index d5a6b86fddd..1b98a7c0db9 100644 --- a/dts/arm/st/stm32f103xb.dtsi +++ b/dts/arm/st/stm32f103xb.dtsi @@ -16,20 +16,11 @@ reg = <0x20000000 DT_SRAM_SIZE>; }; - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - soc { usart1: uart@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; interrupts = <37 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -37,7 +28,6 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -45,51 +35,8 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39 0>; - baud-rate = <115200>; status = "disabled"; }; - - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f103xb-pinctrl"; - ranges = <0 0x40010800 0x1400>; - - gpioa: gpio@40010800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - st,bank-name = "GPIOA"; - }; - - gpiob: gpio@40010C00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@40011000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@40011400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@40011800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - st,bank-name = "GPIOE"; - }; - }; }; }; diff --git a/dts/arm/st/stm32f103xe.dtsi b/dts/arm/st/stm32f103xe.dtsi new file mode 100644 index 00000000000..1b98a7c0db9 --- /dev/null +++ b/dts/arm/st/stm32f103xe.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017 I-SENSE group of ICCS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32f107.dtsi b/dts/arm/st/stm32f107.dtsi new file mode 100644 index 00000000000..1b98a7c0db9 --- /dev/null +++ b/dts/arm/st/stm32f107.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017 I-SENSE group of ICCS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32f334.dtsi b/dts/arm/st/stm32f334.dtsi new file mode 100644 index 00000000000..0248b139ff1 --- /dev/null +++ b/dts/arm/st/stm32f334.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32f373.dtsi b/dts/arm/st/stm32f373.dtsi new file mode 100644 index 00000000000..0248b139ff1 --- /dev/null +++ b/dts/arm/st/stm32f373.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40013800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40013800 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart3: uart@40004800 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004800 0x400>; + interrupts = <39 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32f4.dtsi b/dts/arm/st/stm32f4.dtsi new file mode 100644 index 00000000000..8a96c2f8a7b --- /dev/null +++ b/dts/arm/st/stm32f4.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + flash0: flash { + reg = <0x08000000 DT_FLASH_SIZE>; + }; + + sram0: memory { + reg = <0x20000000 DT_SRAM_SIZE>; + }; + + soc { + usart1: uart@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37 0>; + status = "disabled"; + }; + + usart2: uart@40004400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40004400 0x400>; + interrupts = <38 0>; + status = "disabled"; + }; + + usart6: uart@40011400 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011400 0x400>; + interrupts = <71 0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/dts/arm/st/stm32f401.dtsi b/dts/arm/st/stm32f401.dtsi new file mode 100644 index 00000000000..c02702e5296 --- /dev/null +++ b/dts/arm/st/stm32f401.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/st/stm32f411.dtsi b/dts/arm/st/stm32f411.dtsi new file mode 100644 index 00000000000..c02702e5296 --- /dev/null +++ b/dts/arm/st/stm32f411.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/st/stm32l476.dtsi b/dts/arm/st/stm32l476.dtsi index ee0437fbfe9..19329faaf7a 100644 --- a/dts/arm/st/stm32l476.dtsi +++ b/dts/arm/st/stm32l476.dtsi @@ -16,20 +16,11 @@ reg = <0x20000000 DT_SRAM_SIZE>; }; - clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - }; - soc { usart1: uart@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; interrupts = <37 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -37,7 +28,6 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; interrupts = <38 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -45,7 +35,6 @@ compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; interrupts = <39 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -53,7 +42,6 @@ compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; interrupts = <52 0>; - baud-rate = <115200>; status = "disabled"; }; @@ -61,74 +49,8 @@ compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; interrupts = <53 0>; - baud-rate = <115200>; status = "disabled"; }; - - pin-controller { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32l4xx-pinctrl"; - ranges = <0 0x48000000 0x2000>; - - gpioa: gpio@48000000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x0 0x400>; - st,bank-name = "GPIOA"; - - }; - - gpiob: gpio@48000400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x400 0x400>; - st,bank-name = "GPIOB"; - }; - - gpioc: gpio@48000800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x800 0x400>; - st,bank-name = "GPIOC"; - }; - - gpiod: gpio@48000c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0xc00 0x400>; - st,bank-name = "GPIOD"; - }; - - gpioe: gpio@48001000 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1000 0x400>; - st,bank-name = "GPIOE"; - }; - - gpiof: gpio@48001400 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1400 0x400>; - st,bank-name = "GPIOF"; - }; - - gpiog: gpio@48001800 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1800 0x400>; - st,bank-name = "GPIOG"; - }; - - gpioh: gpio@48001c00 { - gpio-controller; - #gpio-cells = <2>; - reg = <0x1c00 0x400>; - st,bank-name = "GPIOH"; - }; - - }; }; };