driver: pl011: use new device model to map MMIO
Use the new device model introduced by device_mmio.h to map pl011 MMIO space. Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
This commit is contained in:
Luca Fancellu
Carles Cufí
parent
0cc9ad4f50
commit
d62645200b
1 changed files with 51 additions and 73 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 Linaro Limited
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* Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -12,6 +13,7 @@
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#include <zephyr/init.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/sys/device_mmio.h>
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#ifdef CONFIG_CPU_CORTEX_M
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#include <cmsis_compiler.h>
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@ -43,7 +45,7 @@ struct pl011_regs {
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};
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struct pl011_config {
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volatile struct pl011_regs *uart;
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DEVICE_MMIO_ROM;
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uint32_t sys_clk_freq;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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@ -52,6 +54,7 @@ struct pl011_config {
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/* Device data structure */
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struct pl011_data {
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DEVICE_MMIO_RAM;
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uint32_t baud_rate; /* Baud rate */
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bool sbsa; /* SBSA mode */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -153,39 +156,35 @@ struct pl011_data {
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PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
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PL011_IMSC_RTIM)
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static inline
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volatile struct pl011_regs *const get_uart(const struct device *dev)
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{
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return (volatile struct pl011_regs *const)DEVICE_MMIO_GET(dev);
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}
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static void pl011_enable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->cr |= PL011_CR_UARTEN;
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get_uart(dev)->cr |= PL011_CR_UARTEN;
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}
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static void pl011_disable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->cr &= ~PL011_CR_UARTEN;
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get_uart(dev)->cr &= ~PL011_CR_UARTEN;
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}
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static void pl011_enable_fifo(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->lcr_h |= PL011_LCRH_FEN;
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get_uart(dev)->lcr_h |= PL011_LCRH_FEN;
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}
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static void pl011_disable_fifo(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->lcr_h &= ~PL011_LCRH_FEN;
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get_uart(dev)->lcr_h &= ~PL011_LCRH_FEN;
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}
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static int pl011_set_baudrate(const struct device *dev,
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uint32_t clk, uint32_t baudrate)
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{
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const struct pl011_config *config = dev->config;
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/* Avoiding float calculations, bauddiv is left shifted by 6 */
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uint64_t bauddiv = (((uint64_t)clk) << PL011_FBRD_WIDTH)
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/ (baudrate * 16U);
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@ -199,8 +198,8 @@ static int pl011_set_baudrate(const struct device *dev,
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return -EINVAL;
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}
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config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH;
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config->uart->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
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get_uart(dev)->ibrd = bauddiv >> PL011_FBRD_WIDTH;
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get_uart(dev)->fbrd = bauddiv & ((1u << PL011_FBRD_WIDTH) - 1u);
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__DMB();
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@ -208,61 +207,55 @@ static int pl011_set_baudrate(const struct device *dev,
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* lcr_h write must always be performed at the end
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* ARM DDI 0183F, Pg 3-13
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*/
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config->uart->lcr_h = config->uart->lcr_h;
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get_uart(dev)->lcr_h = get_uart(dev)->lcr_h;
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return 0;
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}
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static bool pl011_is_readable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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struct pl011_data *data = dev->data;
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if (!data->sbsa &&
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(!(config->uart->cr & PL011_CR_UARTEN) ||
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!(config->uart->cr & PL011_CR_RXE)))
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(!(get_uart(dev)->cr & PL011_CR_UARTEN) ||
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!(get_uart(dev)->cr & PL011_CR_RXE)))
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return false;
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return (config->uart->fr & PL011_FR_RXFE) == 0U;
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return (get_uart(dev)->fr & PL011_FR_RXFE) == 0U;
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}
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static int pl011_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct pl011_config *config = dev->config;
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if (!pl011_is_readable(dev)) {
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return -1;
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}
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/* got a character */
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*c = (unsigned char)config->uart->dr;
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*c = (unsigned char)get_uart(dev)->dr;
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return config->uart->rsr & PL011_RSR_ERROR_MASK;
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return get_uart(dev)->rsr & PL011_RSR_ERROR_MASK;
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}
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static void pl011_poll_out(const struct device *dev,
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unsigned char c)
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{
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const struct pl011_config *config = dev->config;
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/* Wait for space in FIFO */
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while (config->uart->fr & PL011_FR_TXFF) {
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while (get_uart(dev)->fr & PL011_FR_TXFF) {
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; /* Wait */
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}
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/* Send a character */
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config->uart->dr = (uint32_t)c;
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get_uart(dev)->dr = (uint32_t)c;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int pl011_fifo_fill(const struct device *dev,
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const uint8_t *tx_data, int len)
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{
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const struct pl011_config *config = dev->config;
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uint8_t num_tx = 0U;
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while (!(config->uart->fr & PL011_FR_TXFF) && (len - num_tx > 0)) {
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config->uart->dr = tx_data[num_tx++];
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while (!(get_uart(dev)->fr & PL011_FR_TXFF) && (len - num_tx > 0)) {
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get_uart(dev)->dr = tx_data[num_tx++];
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}
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return num_tx;
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}
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@ -270,11 +263,10 @@ static int pl011_fifo_fill(const struct device *dev,
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static int pl011_fifo_read(const struct device *dev,
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uint8_t *rx_data, const int len)
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{
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const struct pl011_config *config = dev->config;
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uint8_t num_rx = 0U;
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while ((len - num_rx > 0) && !(config->uart->fr & PL011_FR_RXFE)) {
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rx_data[num_rx++] = config->uart->dr;
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while ((len - num_rx > 0) && !(get_uart(dev)->fr & PL011_FR_RXFE)) {
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rx_data[num_rx++] = get_uart(dev)->dr;
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}
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return num_rx;
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@ -282,77 +274,61 @@ static int pl011_fifo_read(const struct device *dev,
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static void pl011_irq_tx_enable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->imsc |= PL011_IMSC_TXIM;
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get_uart(dev)->imsc |= PL011_IMSC_TXIM;
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}
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static void pl011_irq_tx_disable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->imsc &= ~PL011_IMSC_TXIM;
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get_uart(dev)->imsc &= ~PL011_IMSC_TXIM;
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}
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static int pl011_irq_tx_complete(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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/* check for TX FIFO empty */
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return config->uart->fr & PL011_FR_TXFE;
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return get_uart(dev)->fr & PL011_FR_TXFE;
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}
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static int pl011_irq_tx_ready(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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struct pl011_data *data = dev->data;
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if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE))
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if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_TXE))
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return false;
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return ((config->uart->imsc & PL011_IMSC_TXIM) &&
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return ((get_uart(dev)->imsc & PL011_IMSC_TXIM) &&
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pl011_irq_tx_complete(dev));
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}
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static void pl011_irq_rx_enable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
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get_uart(dev)->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM;
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}
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static void pl011_irq_rx_disable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
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get_uart(dev)->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM);
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}
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static int pl011_irq_rx_ready(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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struct pl011_data *data = dev->data;
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if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE))
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if (!data->sbsa && !(get_uart(dev)->cr & PL011_CR_RXE))
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return false;
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return ((config->uart->imsc & PL011_IMSC_RXIM) &&
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(!(config->uart->fr & PL011_FR_RXFE)));
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return ((get_uart(dev)->imsc & PL011_IMSC_RXIM) &&
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(!(get_uart(dev)->fr & PL011_FR_RXFE)));
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}
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static void pl011_irq_err_enable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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/* enable framing, parity, break, and overrun */
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config->uart->imsc |= PL011_IMSC_ERROR_MASK;
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get_uart(dev)->imsc |= PL011_IMSC_ERROR_MASK;
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}
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static void pl011_irq_err_disable(const struct device *dev)
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{
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const struct pl011_config *config = dev->config;
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config->uart->imsc &= ~PL011_IMSC_ERROR_MASK;
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get_uart(dev)->imsc &= ~PL011_IMSC_ERROR_MASK;
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}
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static int pl011_irq_is_pending(const struct device *dev)
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@ -404,6 +380,8 @@ static int pl011_init(const struct device *dev)
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int ret;
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uint32_t lcrh;
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DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
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/*
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* If working in SBSA mode, we assume that UART is already configured,
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* or does not require configuration at all (if UART is emulated by
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@ -422,23 +400,23 @@ static int pl011_init(const struct device *dev)
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}
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/* Setting the default character format */
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lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
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lcrh = get_uart(dev)->lcr_h & ~(PL011_LCRH_FORMAT_MASK);
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lcrh &= ~(BIT(0) | BIT(7));
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lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT;
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config->uart->lcr_h = lcrh;
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get_uart(dev)->lcr_h = lcrh;
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/* Enabling the FIFOs */
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pl011_enable_fifo(dev);
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}
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/* initialize all IRQs as masked */
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config->uart->imsc = 0U;
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config->uart->icr = PL011_IMSC_MASK_ALL;
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get_uart(dev)->imsc = 0U;
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get_uart(dev)->icr = PL011_IMSC_MASK_ALL;
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if (!data->sbsa) {
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config->uart->dmacr = 0U;
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get_uart(dev)->dmacr = 0U;
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__ISB();
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config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1));
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config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE;
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get_uart(dev)->cr &= ~(BIT(14) | BIT(15) | BIT(1));
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get_uart(dev)->cr |= PL011_CR_RXE | PL011_CR_TXE;
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__ISB();
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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@ -481,7 +459,7 @@ void pl011_isr(const struct device *dev)
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}; \
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\
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static struct pl011_config pl011_cfg_port_##n = { \
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.uart = (volatile struct pl011_regs *)DT_INST_REG_ADDR(n), \
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), \
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.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency), \
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.irq_config_func = pl011_irq_config_func_##n, \
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};
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@ -521,7 +499,7 @@ static void pl011_irq_config_func_sbsa(const struct device *dev);
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#endif
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static struct pl011_config pl011_cfg_sbsa = {
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.uart = (volatile struct pl011_regs *)DT_INST_REG_ADDR(0),
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DEVICE_MMIO_ROM_INIT(DT_DRV_INST(0)),
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.irq_config_func = pl011_irq_config_func_sbsa,
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#endif
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