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soc/intel_adsp: Put initial stack into the CPU0 interrupt stack

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Zephyr's normal architecture is to do all initialization in the
interrupt stacks.  The CAVS code was traditionally written to start
the stack at the end of HP-SRAM, where it has no protection against
overlap with other uses (e.g. MP startup used the same region for
stacks and saw cache collisions, and the SOF heap lives in this area
too).  Put it where Zephyr expects and we'll have fewer surprises.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-02-16 10:09:25 -08:00 • committed by Anas Nashif
commit d60c8496e3
1 changed files with 3 additions and 4 deletions
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7
soc/xtensa/intel_adsp/cavs_v15/linker.ld
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@ -499,10 +499,9 @@ SECTIONS
/* Re-adjust to the upper mapping for the final symbols below */
. = SEGSTART_CACHED;
/* stack */
_end = ALIGN(8);
PROVIDE(end = ALIGN(8));
__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
/* Initial/boot stack lives in the CPU0 interrupt stack */
__stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE;
/* dma buffers */
.lpbuf (NOLOAD): ALIGN(4)
{