From d60c8496e343fbc932c3492e6cdc78b8c99c9217 Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Tue, 16 Feb 2021 10:09:25 -0800 Subject: [PATCH] soc/intel_adsp: Put initial stack into the CPU0 interrupt stack Zephyr's normal architecture is to do all initialization in the interrupt stacks. The CAVS code was traditionally written to start the stack at the end of HP-SRAM, where it has no protection against overlap with other uses (e.g. MP startup used the same region for stacks and saw cache collisions, and the SOF heap lives in this area too). Put it where Zephyr expects and we'll have fewer surprises. Signed-off-by: Andy Ross --- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index dd27ba428c3..3ff29df6584 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -499,10 +499,9 @@ SECTIONS /* Re-adjust to the upper mapping for the final symbols below */ . = SEGSTART_CACHED; - /* stack */ - _end = ALIGN(8); - PROVIDE(end = ALIGN(8)); - __stack = L2_SRAM_BASE + L2_SRAM_SIZE; + /* Initial/boot stack lives in the CPU0 interrupt stack */ + __stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE; + /* dma buffers */ .lpbuf (NOLOAD): ALIGN(4) {