board: arm: Add board support for mimxrt1020_evk

Add board support files for mimxrt1020_evk, the development board for
i.MXRT1021 (CM7) SoC.

- Add pinmux, dts, doc.
- Code can be loaded to SRAM.
- Tested samples: hello_world, philosophers, synchronization,
basic/blinky, and basic/button.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>

boards/arm/mimxrt1020_evk/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_library_sources(pinmux.c)

boards/arm/mimxrt1020_evk/Kconfig

@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MIMXRT1020_EVK
+
+choice
+	prompt "Code location selection"
+	default CODE_ITCM
+
+config CODE_ITCM
+	bool "Link code into internal instruction tightly coupled memory (ITCM)"
+
+config CODE_QSPI
+	depends on BOARD_MIMXRT1020_EVK
+	bool "Link code into external QSPI memory"
+
+endchoice
+
+endif # BOARD_MIMXRT1020_EVK

boards/arm/mimxrt1020_evk/Kconfig.board

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_MIMXRT1020_EVK
+	bool "NXP MIMXRT1020-EVK"
+	depends on SOC_SERIES_IMX_RT
+	select SOC_PART_NUMBER_MIMXRT1021DAG5A

boards/arm/mimxrt1020_evk/Kconfig.defconfig

@@ -0,0 +1,38 @@
+# Kconfig - MIMXRT1020-EVK board
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_MIMXRT1020_EVK
+
+config BOARD
+	default "mimxrt1020_evk" if BOARD_MIMXRT1020_EVK
+
+if GPIO_MCUX_IGPIO
+
+config GPIO_MCUX_IGPIO_1
+	default y
+
+config GPIO_MCUX_IGPIO_5
+	default y
+
+endif # GPIO_MCUX_IGPIO
+
+if UART_MCUX_LPUART
+
+config UART_MCUX_LPUART_1
+	default y
+
+endif # UART_MCUX_LPUART
+
+if CODE_QSPI
+
+# Reserve space for the IVT
+config TEXT_SECTION_OFFSET
+	default 0x2000
+
+endif
+
+endif # BOARD_MIMXRT1020_EVK

boards/arm/mimxrt1020_evk/board.cmake

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCIMXRT1021")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/mimxrt1020_evk/doc/mimxrt1020_evk.rst

@@ -0,0 +1,176 @@
+.. _mimxrt1020_evk:
+
+NXP MIMXRT1020-EVK
+##################
+
+Overview
+********
+
+The i.MX RT1020 expands the i.MX RT crossover processor families by providing
+high-performance feature set in low-cost LQFP packages, further simplifying
+board design and layout for customers. The i.MX RT1020 runs on the Arm®
+Cortex®-M7 core at 500 MHz.
+
+.. image:: mimxrt1020_evk.jpg
+   :width: 720px
+   :align: center
+   :alt: MIMXRT1020-EVK
+
+Hardware
+********
+
+- MIMXRT1021DAG5A MCU
+
+- Memory
+
+  - 256 Mbit SDRAM
+  - 64 Mbit QSPI Flash
+  - TF socket for SD card
+
+- Connectivity
+
+  - 10/100 Mbit/s Ethernet PHY
+  - Micro USB host and OTG connectors
+  - CAN transceivers
+  - Arduino interface
+
+- Audio
+
+  - Audio Codec
+  - 4-pole audio headphone jack
+  - Microphone
+  - External speaker connection
+
+- Power
+
+  - 5 V DC jack
+
+- Debug
+
+  - JTAG 20-pin connector
+  - OpenSDA with DAPLink
+
+For more information about the MIMXRT1020 SoC and MIMXRT1020-EVK board, see
+these references:
+
+- `i.MX RT1020 Website`_
+- `i.MX RT1020 Datasheet`_
+- `i.MX RT1020 Reference Manual`_
+- `MIMXRT1020-EVK Website`_
+- `MIMXRT1020-EVK User Guide`_
+- `MIMXRT1020-EVK Design Files`_
+
+Supported Features
+==================
+
+The mimxrt1020_evk board configuration supports the following hardware
+features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+``boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig``
+
+Other hardware features are not currently supported by the port.
+
+Connections and I/Os
+====================
+
+The MIMXRT1020 SoC has five pairs of pinmux/gpio controllers.
+
++---------------+-----------------+---------------------------+
+| Name          | Function        | Usage                     |
++===============+=================+===========================+
+| GPIO_AD_B0_05 | GPIO            | LED                       |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_06 | LPUART1_TX      | UART Console              |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_07 | LPUART1_RX      | UART Console              |
++---------------+-----------------+---------------------------+
+| WAKEUP        | GPIO            | SW0                       |
++---------------+-----------------+---------------------------+
+
+System Clock
+============
+
+The MIMXRT1020 SoC is configured to use the 24 MHz external oscillator on the
+board with the on-chip PLL to generate a 500 MHz core clock.
+
+Serial Port
+===========
+
+The MIMXRT1020 SoC has eight UARTs. One is configured for the console and the
+remaining are not used.
+
+Programming and Debugging
+*************************
+
+The MIMXRT1020-EVK includes the :ref:`nxp_opensda` serial and debug adapter
+built into the board to provide debugging, flash programming, and serial
+communication over USB.
+
+To use the Segger J-Link tools with OpenSDA, follow the instructions in the
+:ref:`nxp_opensda_jlink` page using the `Segger J-Link OpenSDA V2.1 Firmware`_.
+The Segger J-Link tools are the default for this board, therefore it is not
+necessary to set ``OPENSDA_FW=jlink`` explicitly when you invoke ``make
+debug``.
+
+With these mechanisms, applications for the ``mimxrt1020_evk`` board
+configuration can be built and debugged in the usual way (see
+:ref:`build_an_application` and :ref:`application_run` for more details).
+
+The pyOCD tools do not yet support this SoC.
+
+Flashing
+========
+
+The Segger J-Link firmware does not support command line flashing, therefore
+the usual ``flash`` build system target is not supported.
+Instead, see the https://www.nxp.com/docs/en/application-note/AN12108.pdf for flashing instructions.
+
+
+Debugging
+=========
+
+This example uses the :ref:`hello_world` sample with the
+:ref:`nxp_opensda_jlink` tools. Run the following to build your Zephyr
+application, invoke the J-Link GDB server, attach a GDB client, and program
+your Zephyr application to flash. It will leave you at a GDB prompt.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt1020_evk
+   :goals: debug
+
+
+.. _MIMXRT1020-EVK Website:
+   https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK
+
+.. _MIMXRT1020-EVK User Guide:
+   https://www.nxp.com/docs/en/user-guide/MIMXRT1020EVKHUG.pdf
+
+.. _MIMXRT1020-EVK Design Files:
+   https://www.nxp.com/webapp/Download?colCode=MIMXRT1020-EVK-Design-Files
+
+.. _i.MX RT1020 Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1020-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1020
+
+.. _i.MX RT1020 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/IMXRT1020CEC.pdf
+
+.. _i.MX RT1020 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=IMXRT1020RM
+
+.. _Segger J-Link OpenSDA V2.1 Firmware:
+   https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin

boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2018, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt.dtsi>
+
+/ {
+	model = "NXP MIMXRT1020-EVK board";
+	compatible = "nxp,mimxrt1021";
+
+	aliases {
+		gpio-1= &gpio1;
+		gpio-2= &gpio2;
+		gpio-3= &gpio3;
+		gpio-4= &gpio4;
+		gpio-5= &gpio5;
+		uart-1 = &uart1;
+		led0 = &green_led;
+		sw0 = &user_button;
+	};
+
+	chosen {
+#if defined(CONFIG_CODE_ITCM)
+		zephyr,flash = &itcm0;
+#elif defined(CONFIG_CODE_QSPI)
+		zephyr,flash = &qspi0;
+#endif
+		zephyr,sram = &dtcm0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+	};
+
+	sdram0: memory@80000000 {
+		/* ISSI IS42S16160J-6TLI */
+		device_type = "memory";
+		reg = <0x80000000 0x2000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led-1 {
+			gpios = <&gpio1 5 GPIO_INT_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button-1 {
+			label = "User SW8";
+			gpios = <&gpio5 0 GPIO_INT_ACTIVE_LOW>;
+		};
+	};
+};
+
+&flexspi0 {
+	qspi0: qspi@60000000 {
+		/* ISSI IS25LP064A-JBLE */
+		reg = <0x60000000 0x800000>;
+		status = "ok";
+	};
+};
+
+&uart1 {
+	status = "ok";
+	current-speed = <115200>;
+};

boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml

@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1020_evk
+name: NXP MIMXRT1020-EVK
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 128
+flash: 128

boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig

@@ -0,0 +1,16 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM=y
+CONFIG_SOC_MIMXRT1021=y
+CONFIG_SOC_SERIES_IMX_RT=y
+CONFIG_BOARD_MIMXRT1020_EVK=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_GPIO=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=500000000

boards/arm/mimxrt1020_evk/pinmux.c

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+#include <fsl_iomuxc.h>
+
+static int mimxrt1020_evk_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	/* LED */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+	/* SW0 */
+	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
+
+#ifdef CONFIG_UART_MCUX_LPUART_1
+	/* LPUART1 TX/RX */
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX,
+			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
+			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
+#endif
+
+	return 0;
+}
+
+SYS_INIT(mimxrt1020_evk_init, PRE_KERNEL_1, 0);