pci: Provide a simpler yet powerful PCI enumeration API
This fixes many issues around PCI enumeration from old API: - a static internal table was fed with scanning results, thus eating memory, and worse: due to the limit of its size, scanning for new classes was impossible unless growing statically the size of this table --> more memory eaten! Not to mention PCI enumeration is done once at boot time for driver initialization and that's all, so this table is hanging around for nothing afterwards. - one needs first to scan a class, then maybe he will be able to find his device via pci_dev_find. Where all could be done at once. - pci_dev_find was not trustworthy due again to the internal table. Now if the device is not found, one will know it really went through all the possbilities. - still let the possibility for hard-coded BARs value on driver side (thus no PCI scan required). However this is greatly advised not to do so as BARs might change over a firmware/BIOS update. Comparison: old pci_dev_scan: could only filter out via class mask. new pci_dev_scan: can filter out via a class, a vendor and device ID (it could easily do the same for Function and BAR index as these are usually fixed and informed through datasheet) old pci_dev_scan: was limited in its findings by the size of the internal result table. new pci_dev_scan: can proceed through all the buses and devices every time (there are optimizations to avoid useless work of course) old results did not tell about the function or BAR index. new one tells, and the structure has not bloated. old internal code: was storing a big table of results new internal code: is only storing a small lookup structure and an array of Bus:Dev pairs for each PCI class for optimizations purpose. (though, if needed, we could disable this through some #ifdef) Usage: - Have a local struct dev_info - Fill it with what you want to look for, currently: only class and vendor_id/device_id. Function and BAR index could be added if needed. - Call pci_bus_scan_init(): this will reset the internal lookup structure. - Call pci_dev_scan(<a pointer to your dev_info>): at first call, the internal lookup structure will pick up the informations from dev_info and will try to find out what has been requested. It will return 1 on success, or 0. On 1, your dev_info structure will be updated with the found informations. If more devices can be found against the same lookup informations, just call again pci_dev_scan(<a pointer to your dev_info>) as long as it returns 1. When 0 is hit, it will mean you found all. Change-Id: Ibc2a16c4485ee3fed7ef4946af0ece032ae406e4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Anas Nashif
parent
1425fd8449
commit
d3a4177d92
6 changed files with 226 additions and 207 deletions
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@ -138,6 +138,8 @@ the 'Quark' BSP.
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#endif
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/* PCI definitions */
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#define PCI_BUS_NUMBERS 2
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#define PCI_CTRL_ADDR_REG 0xCF8
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#define PCI_CTRL_DATA_REG 0xCFC
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@ -109,36 +109,32 @@ static void uartGenericInfoInit(struct uart_init_info *p_info)
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static void consoleInit(void)
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{
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struct pci_dev_info dev_info = {
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.class = PCI_CLASS_COMM_CTLR,
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.vendor_id = 0x8086,
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.device_id = 0x0936,
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};
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struct uart_init_info info;
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uint32_t addr;
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uint32_t size;
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int irq;
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int i;
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uartGenericInfoInit(&info);
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/*
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* Even though, pci_dev_find() returns an error if the device isn't found,
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* we
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* ignore it as an error means that the class and/or index supplied is
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* incorrect. The serial device *SHOULD* be found.
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*/
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__ASSERT_EVAL((void)pci_dev_find(PCI_CLASS_COMM_CTLR,
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CONFIG_UART_CONSOLE_PCI_IDX,
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&addr,
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&size,
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&irq),
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int res = pci_dev_find(PCI_CLASS_COMM_CTLR,
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CONFIG_UART_CONSOLE_PCI_IDX,
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&addr,
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&size,
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&irq),
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res != -1,
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"");
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pci_bus_scan_init();
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info.regs = _SysPciMap(addr, size);
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i = 0;
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while (pci_bus_scan(&dev_info) && i < CONFIG_UART_CONSOLE_PCI_IDX) {
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i++;
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}
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info.regs = _SysPciMap(dev_info.addr, dev_info.size);
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info.irq = dev_info.irq;
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uart_init(CONFIG_UART_CONSOLE_INDEX, &info);
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uart_console_init();
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#ifdef PCI_DEBUG
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pci_show(&dev_info);
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#endif /* PCI_DEBUG */
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}
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#else
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@ -165,8 +161,6 @@ void _InitHardware(void)
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_ioapic_irq_set(HPET_TIMER0_IRQ, HPET_TIMER0_VEC, HPET_IOAPIC_FLAGS);
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pci_bus_scan(1 << PCI_CLASS_COMM_CTLR);
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consoleInit(); /* NOP if not needed */
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#ifdef PCI_DEBUG
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@ -33,11 +33,11 @@
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/*
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DESCRIPTION
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Module implements routines for PCI bus initialization and query.
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Note that the BSP must call pci_bus_scan() before any other PCI
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API is called.
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USAGE
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In order to use the driver, BSP has to define:
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- Numbers of BUSes:
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- PCI_BUS_NUMBERS;
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- Register addresses:
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- PCI_CTRL_ADDR_REG;
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- PCI_CTRL_DATA_REG;
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@ -47,6 +47,72 @@ In order to use the driver, BSP has to define:
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- PLB_BYTE_REG_READ() / PLB_BYTE_REG_WRITE();
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- pci_pin2irq() - the routine that converts the PCI interrupt pin
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number to IRQ number.
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About scanning the PCI buses:
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At every new usage of this API, the code should call pci_bus_scan_init().
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It should own a struct pci_dev_info, filled in with the parameters it is
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interested to look for: class and/or vendor_id/device_id.
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Then it can loop on pci_bus_scan() providing a pointer on that structure.
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Such function can be called as long as it returns 1. At every successful
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return of pci_bus_scan() it means the provided structure pointer will have
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been updated with the current scan result which the code might be interested
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in. On pci_bus_scan() returning 0, the code should discard the result and
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stop calling pci_bus_scan(). If it wants to retrieve the result, it will
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have to restart the procedure all over again.
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EXAMPLE
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struct pci_dev_info info = {
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.class = PCI_CLASS_COMM_CTLR
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};
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pci_bus_scan_init();
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while (pci_bus_scan(&info) {
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// do something with "info" which holds a valid result, i.e. some
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// device information matching the PCI class PCI_CLASS_COMM_CTLR
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}
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INTERNALS
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The whole logic runs around a structure: struct lookup_data, which exists
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on one instanciation called 'lookup'.
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Such structure is used for 2 distinct roles:
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- to match devices the caller is looking for
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- to loop on PCI bus, devices, function and BARs
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The search criterias are the class and/or the vendor_id/device_id of a PCI
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device. The caller first initializes the lookup structure by calling
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pci_bus_scan_init(), which will reset the search criterias as well as the
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loop paramaters to 0. At the very first subsequent call of pci_bus_scan()
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the lookup structure will store the search criterias. Then the loop starts.
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For each bus it will run through each device on which it will loop on each
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function and BARs, as long as the criterias does not match or until it hit
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the limit of bus/dev/functions to scan.
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On a successful match, it will stop the loop, fill in the caller's
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pci_dev_info structure with the found device information, and return 1.
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Hopefully, the lookup structure still remembers where it stopped and the
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original search criterias. Thus, when the caller asks to scan again for
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a possible result next, the loop will restart where it stopped.
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That will work as long as there are relevant results found.
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Running through every buses and devices can be gready. Thus, in order to
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optimize any subsequent new search, the code holds another structure:
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struct bus_dev. Such structure exists for every possible PCI classes, in
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a table 'class_bd'.
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Every time a loop will hit a class, if such class is unknown yet from its
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relevant class_bd's bus_dev, it will fill in the information in class_bd.
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Basically, class_bd stores for every class, at which bus and which dev
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a search loop should start. This permits to accelerate a bit any
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class-specific bus scan since this is most of the time what the caller will
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be interested in.
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For instance, if a previous pci_bus_scan() searching for class z has hit
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various classes in between like classes x and y, class_bd will then know
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where to start a loop on these classes. Thus, a subsequent pci scan looking
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for class y will directly start at the relevant bus and device instead of
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restarting from 0.
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*/
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#include <nanokernel.h>
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@ -61,7 +127,7 @@ In order to use the driver, BSP has to define:
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#include <pci/pci.h>
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/* NOTE. These parameters may need to be configurable */
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#define LSPCI_MAX_BUS 256 /* maximum number of buses to scan */
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#define LSPCI_MAX_BUS PCI_BUS_NUMBERS /* maximum number of buses to scan */
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#define LSPCI_MAX_DEV 32 /* maximum number of devices to scan */
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#define LSPCI_MAX_FUNC 8 /* maximum device functions to scan */
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#define LSPCI_MAX_REG 64 /* maximum device registers to read */
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@ -82,8 +148,25 @@ In order to use the driver, BSP has to define:
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#define MAX_BARS 6
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static struct pci_dev_info __noinit dev_info[CONFIG_MAX_PCI_DEVS];
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static int dev_info_index = 0;
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struct bus_dev {
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uint16_t set:1;
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uint16_t bus:8;
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uint16_t dev:5;
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uint16_t unused:2;
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};
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struct lookup_data {
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struct pci_dev_info info;
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uint32_t bus:9;
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uint32_t dev:6;
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uint32_t func:4;
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uint32_t bar:4;
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uint32_t unused:9;
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};
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#define PCI_CLASS_MAX PCI_CLASS_DAQ_DSP + 1
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static struct bus_dev class_bd[PCI_CLASS_MAX] = {};
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static struct lookup_data __noinit lookup;
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/******************************************************************************
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*
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@ -92,22 +175,11 @@ static int dev_info_index = 0;
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* RETURNS: 0 if BAR is implemented, -1 if not.
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*/
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static int pci_bar_config_get(uint32_t bus,
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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uint32_t *config)
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static inline int pci_bar_config_get(union pci_addr_reg pci_ctrl_addr,
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uint32_t *config)
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{
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union pci_addr_reg pci_ctrl_addr;
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uint32_t old_value;
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.enable = 1;
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pci_ctrl_addr.field.bus = bus;
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pci_ctrl_addr.field.device = dev;
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pci_ctrl_addr.field.func = func;
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pci_ctrl_addr.field.reg = 4 + bar;
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/* save the current setting */
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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@ -145,44 +217,35 @@ static int pci_bar_config_get(uint32_t bus,
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*
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* pci_bar_params_get - retrieve the I/O address and IRQ of the specified BAR
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*
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* RETURN: -1 on error, 0 if 32 bit BAR retrieved or 1 if 64 bit BAR retrieved
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* RETURNS: -1 on error, 0 if 32 bit BAR retrieved or 1 if 64 bit BAR retrieved
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*
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* NOTE: Routine does not set up parameters for 64 bit BARS, they are ignored.
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*
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* \NOMANUAL
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*/
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static inline int pci_bar_params_get(uint32_t bus,
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uint32_t dev,
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uint32_t func,
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uint32_t bar,
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static inline int pci_bar_params_get(union pci_addr_reg pci_ctrl_addr,
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struct pci_dev_info *dev_info)
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{
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static union pci_addr_reg pci_ctrl_addr;
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uint32_t bar_value;
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uint32_t bar_config;
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uint32_t addr;
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uint32_t mask;
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.enable = 1;
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pci_ctrl_addr.field.bus = bus;
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pci_ctrl_addr.field.device = dev;
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pci_ctrl_addr.field.func = func;
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pci_ctrl_addr.field.reg = 4 + bar;
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pci_ctrl_addr.field.reg = 4 + lookup.bar;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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sizeof(bar_value),
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&bar_value);
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if (pci_bar_config_get(bus, dev, func, bar, &bar_config) != 0) {
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if (pci_bar_config_get(pci_ctrl_addr, &bar_config) != 0) {
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return -1;
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}
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if (BAR_SPACE(bar_config) == BAR_SPACE_MEM) {
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dev_info->mem_type = BAR_SPACE_MEM;
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mask = ~0xf;
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if (bar < 5 && BAR_TYPE(bar_config) == BAR_TYPE_64BIT) {
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if (lookup.bar < 5 && BAR_TYPE(bar_config) == BAR_TYPE_64BIT) {
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return 1; /* 64-bit MEM */
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}
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} else {
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@ -205,34 +268,21 @@ static inline int pci_bar_params_get(uint32_t bus,
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*
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* pci_dev_scan - scan the specified PCI device for all sub functions
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*
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* RETURNS: N/A
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* RETURNS: 1 if a device has been found, 0 otherwise.
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*
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* \NOMANUAL
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*/
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static void pci_dev_scan(uint32_t bus,
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uint32_t dev,
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uint32_t class_mask)
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static inline int pci_dev_scan(union pci_addr_reg pci_ctrl_addr,
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struct pci_dev_info *dev_info)
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{
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uint32_t func;
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uint32_t pci_data;
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static union pci_addr_reg pci_ctrl_addr;
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static union pci_dev pci_dev_header;
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int i;
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uint32_t pci_data;
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int max_bars;
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if (dev_info_index == CONFIG_MAX_PCI_DEVS) {
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/* No more room in the table */
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return;
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}
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/* initialise the PCI controller address register value */
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pci_ctrl_addr.value = 0;
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pci_ctrl_addr.field.enable = 1;
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pci_ctrl_addr.field.bus = bus;
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pci_ctrl_addr.field.device = dev;
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/* scan all the possible functions for this device */
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for (func = 0; func < LSPCI_MAX_FUNC; func++) {
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pci_ctrl_addr.field.func = func;
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for (; lookup.func < LSPCI_MAX_FUNC; lookup.bar = 0, lookup.func++) {
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pci_ctrl_addr.field.func = lookup.func;
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pci_read(DEFAULT_PCI_CONTROLLER,
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pci_ctrl_addr,
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@ -240,15 +290,34 @@ static void pci_dev_scan(uint32_t bus,
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&pci_data);
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if (pci_data == 0xffffffff) {
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if (lookup.func == 0) {
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return 0;
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}
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continue;
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}
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/* get the PCI header from the device */
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pci_header_get(DEFAULT_PCI_CONTROLLER,
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bus, dev, func, &pci_dev_header);
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pci_ctrl_addr,
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&pci_dev_header);
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/* Skip a device if it's class is not specified by the caller */
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if (!((1 << pci_dev_header.field.class) & class_mask)) {
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if (!class_bd[pci_dev_header.field.class].set) {
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class_bd[pci_dev_header.field.class].set = 1;
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class_bd[pci_dev_header.field.class].bus =
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pci_ctrl_addr.field.bus;
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class_bd[pci_dev_header.field.class].dev =
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pci_ctrl_addr.field.device;
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}
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/* Skip a device if its class is not specified by the caller */
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if (pci_dev_header.field.class != lookup.info.class) {
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continue;
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}
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if (lookup.info.vendor_id && lookup.info.device_id &&
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lookup.info.vendor_id != pci_dev_header.field.vendor_id &&
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lookup.info.device_id != pci_dev_header.field.device_id) {
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continue;
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}
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@ -259,148 +328,118 @@ static void pci_dev_scan(uint32_t bus,
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max_bars = MAX_BARS;
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}
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for (i = 0; i < max_bars; ++i) {
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for (; lookup.bar < max_bars; lookup.bar++) {
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/* Ignore BARs with errors and 64 bit BARs */
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if (pci_bar_params_get(bus, dev, func, i,
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dev_info + dev_info_index) != 0) {
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if (pci_bar_params_get(pci_ctrl_addr, dev_info) != 0) {
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continue;
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} else {
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dev_info[dev_info_index].vendor_id =
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dev_info->vendor_id =
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pci_dev_header.field.vendor_id;
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dev_info[dev_info_index].device_id =
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dev_info->device_id =
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pci_dev_header.field.device_id;
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dev_info[dev_info_index].class =
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dev_info->class =
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pci_dev_header.field.class;
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dev_info[dev_info_index].irq = pci_pin2irq(
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dev_info->irq = pci_pin2irq(
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pci_dev_header.field.interrupt_pin);
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dev_info_index++;
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if (dev_info_index == CONFIG_MAX_PCI_DEVS) {
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/* No more room in the table */
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return;
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}
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dev_info->function = lookup.func;
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dev_info->bar = lookup.bar;
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lookup.bar++;
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if (lookup.bar >= max_bars)
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lookup.bar = 0;
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return 1;
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}
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}
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}
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return 0;
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}
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void pci_bus_scan_init(void)
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{
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lookup.info.class = 0;
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lookup.info.vendor_id = 0;
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lookup.info.device_id = 0;
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lookup.bus = 0;
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lookup.dev = 0;
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lookup.func = 0;
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lookup.bar = 0;
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}
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/******************************************************************************
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*
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* pci_bus_scan - scans PCI bus for devices
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*
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* The routine scans the PCI bus for the devices, which classes are provided
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* in the classMask argument.
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* classMask is constructed as:
|
||||
* (1 << class1) | (1 << class2) | ... | (1 << classN)
|
||||
* The routine scans the PCI bus for the devices on criterias provided in the
|
||||
* given dev_info at first call. Which criterias can be class and/or
|
||||
* vendor_id/device_id.
|
||||
*
|
||||
* RETURNS: 1 on success, 0 otherwise. On success, dev_info is filled in with
|
||||
* currently found device information
|
||||
*
|
||||
* \NOMANUAL
|
||||
*/
|
||||
|
||||
void pci_bus_scan(uint32_t class_mask)
|
||||
int pci_bus_scan(struct pci_dev_info *dev_info)
|
||||
{
|
||||
uint32_t bus;
|
||||
uint32_t dev;
|
||||
union pci_addr_reg pci_ctrl_addr;
|
||||
uint32_t pci_data;
|
||||
|
||||
if (!lookup.info.class &&
|
||||
!lookup.info.vendor_id &&
|
||||
!lookup.info.device_id) {
|
||||
lookup.info.class = dev_info->class;
|
||||
lookup.info.vendor_id = dev_info->vendor_id;
|
||||
lookup.info.device_id = dev_info->device_id;
|
||||
|
||||
if (class_bd[lookup.info.class].set) {
|
||||
lookup.bus = class_bd[lookup.info.class].bus;
|
||||
lookup.dev = class_bd[lookup.info.class].dev;
|
||||
}
|
||||
}
|
||||
|
||||
/* initialise the PCI controller address register value */
|
||||
pci_ctrl_addr.value = 0;
|
||||
pci_ctrl_addr.field.enable = 1;
|
||||
|
||||
/* run through the buses and devices */
|
||||
for (bus = 0; bus < LSPCI_MAX_BUS; bus++) {
|
||||
for (dev = 0; (dev < LSPCI_MAX_DEV) &&
|
||||
(dev_info_index < CONFIG_MAX_PCI_DEVS);
|
||||
dev++) {
|
||||
pci_ctrl_addr.field.bus = bus;
|
||||
pci_ctrl_addr.field.device = dev;
|
||||
for (; lookup.bus < LSPCI_MAX_BUS; lookup.bus++) {
|
||||
for (; (lookup.dev < LSPCI_MAX_DEV);
|
||||
lookup.func = 0, lookup.dev++) {
|
||||
pci_ctrl_addr.field.bus = lookup.bus;
|
||||
pci_ctrl_addr.field.device = lookup.dev;
|
||||
|
||||
/* try and read register zero of the first function */
|
||||
pci_read(DEFAULT_PCI_CONTROLLER,
|
||||
pci_ctrl_addr,
|
||||
sizeof(pci_data),
|
||||
&pci_data);
|
||||
|
||||
/* scan the device if we found something */
|
||||
if (pci_data != 0xffffffff) {
|
||||
pci_dev_scan(bus, dev, class_mask);
|
||||
if (pci_dev_scan(pci_ctrl_addr, dev_info)) {
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* pci_info_get - returns list of PCI devices
|
||||
*
|
||||
* \NOMANUAL
|
||||
*/
|
||||
struct pci_dev_info *pci_info_get(void)
|
||||
{
|
||||
return dev_info;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* pci_dev_find - find PCI device of a specified class and specified index
|
||||
*
|
||||
* Routine looks through the list of detected PCI devices and if the device
|
||||
* of specified <class> and <index> exists, sets up <address>, <size> and <irq>.
|
||||
*
|
||||
* This function can return error if the specified device is not found. In most
|
||||
* cases the device class and index are known to exist and therefore will be
|
||||
* found. However, due to the somewhat dynamic nature of PCI, we allow for the
|
||||
* fact the device may not be found and another attempt with different
|
||||
* parameters maybe made.
|
||||
*
|
||||
* RETURNS: 0, if device is found, -1 otherwise
|
||||
*/
|
||||
|
||||
int pci_dev_find(int class, int idx, uint32_t *addr, uint32_t *size, int *irq)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
|
||||
for (i = 0, j = 0; i < dev_info_index; i++) {
|
||||
if (dev_info[i].class != class) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (j == idx) {
|
||||
*addr = dev_info[i].addr;
|
||||
*size = dev_info[i].size;
|
||||
*irq = dev_info[i].irq;
|
||||
return 0;
|
||||
}
|
||||
j++;
|
||||
}
|
||||
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef PCI_DEBUG
|
||||
/******************************************************************************
|
||||
*
|
||||
* pci_show - Show PCI devices
|
||||
* pci_show - Show PCI device
|
||||
*
|
||||
* Shows the PCI devices found.
|
||||
* Shows the PCI device found provided as parameter.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
void pci_show(void)
|
||||
void pci_show(struct pci_dev_info *dev_info)
|
||||
{
|
||||
int i;
|
||||
|
||||
printk("PCI devices:\n");
|
||||
for (i = 0; i < dev_info_index; i++) {
|
||||
printk("%X:%X class: 0x%X, %s, addrs: 0x%X-0x%X, IRQ %d\n",
|
||||
dev_info[i].vendor_id,
|
||||
dev_info[i].device_id,
|
||||
dev_info[i].class,
|
||||
(dev_info[i].mem_type == BAR_SPACE_MEM) ? "MEM" : "I/O",
|
||||
(uint32_t)dev_info[i].addr,
|
||||
(uint32_t)(dev_info[i].addr + dev_info[i].size - 1),
|
||||
dev_info[i].irq);
|
||||
}
|
||||
printk("PCI device:\n");
|
||||
printk("%X:%X class: 0x%X, %u, %u, %s, addrs: 0x%X-0x%X, IRQ %d\n",
|
||||
dev_info->vendor_id,
|
||||
dev_info->device_id,
|
||||
dev_info->class,
|
||||
dev_info->function,
|
||||
dev_info->bar,
|
||||
(dev_info->mem_type == BAR_SPACE_MEM) ? "MEM" : "I/O",
|
||||
(uint32_t)dev_info->addr,
|
||||
(uint32_t)(dev_info->addr + dev_info->size - 1),
|
||||
dev_info->irq);
|
||||
}
|
||||
#endif /* PCI_DEBUG */
|
||||
|
|
|
|||
|
|
@ -391,24 +391,12 @@ void pci_write(uint32_t controller, /* controller to use */
|
|||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
void pci_header_get(uint32_t controller, /* controller to use */
|
||||
uint32_t bus, /* PCI bus number */
|
||||
uint32_t dev, /* PCI device number */
|
||||
uint32_t func, /* PCI function number */
|
||||
union pci_dev *pci_dev_header /* output: device header */
|
||||
)
|
||||
void pci_header_get(uint32_t controller,
|
||||
union pci_addr_reg pci_ctrl_addr,
|
||||
union pci_dev *pci_dev_header)
|
||||
{
|
||||
union pci_addr_reg pci_ctrl_addr;
|
||||
uint32_t i;
|
||||
|
||||
/* initialise the PCI controller address register value */
|
||||
|
||||
pci_ctrl_addr.value = 0;
|
||||
pci_ctrl_addr.field.enable = 1;
|
||||
pci_ctrl_addr.field.bus = bus;
|
||||
pci_ctrl_addr.field.device = dev;
|
||||
pci_ctrl_addr.field.func = func;
|
||||
|
||||
/* clear out the header */
|
||||
|
||||
k_memset((char *)pci_dev_header, sizeof(union pci_dev), 0);
|
||||
|
|
|
|||
|
|
@ -49,22 +49,20 @@ struct pci_dev_info {
|
|||
uint32_t addr; /* I/O or memory region address */
|
||||
uint32_t size; /* memory region size */
|
||||
int irq;
|
||||
uint16_t mem_type; /* memory type: BAR_SPACE_MEM/BAR_SPACE_IO */
|
||||
uint16_t mem_type:1; /* memory type: BAR_SPACE_MEM/BAR_SPACE_IO */
|
||||
uint16_t class:8;
|
||||
uint16_t function:3;
|
||||
uint16_t bar:3;
|
||||
uint16_t unused:1;
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint16_t class;
|
||||
};
|
||||
|
||||
extern void pci_bus_scan(uint32_t classMask);
|
||||
extern struct pci_dev_info *pci_info_get(void);
|
||||
extern int pci_dev_find(int class,
|
||||
int idx,
|
||||
uint32_t *addr,
|
||||
uint32_t *size,
|
||||
int *irq);
|
||||
extern void pci_bus_scan_init(void);
|
||||
extern int pci_bus_scan(struct pci_dev_info *dev_info);
|
||||
|
||||
#ifdef PCI_DEBUG
|
||||
extern void pci_show(void);
|
||||
extern void pci_show(struct pci_dev_info *dev_info);
|
||||
#endif /* PCI_DEBUG */
|
||||
|
||||
#endif /* _PCI_H_ */
|
||||
|
|
|
|||
|
|
@ -730,9 +730,7 @@ extern void pci_write(uint32_t controller,
|
|||
uint32_t data);
|
||||
|
||||
extern void pci_header_get(uint32_t controller,
|
||||
uint32_t bus,
|
||||
uint32_t dev,
|
||||
uint32_t func,
|
||||
union pci_addr_reg pci_ctrl_addr,
|
||||
union pci_dev *pci_dev_header);
|
||||
|
||||
/* General PCI configuration access routines */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue